|
| #define | GET_ID(val) ((val & 0xF8) >> 3) |
| |
| #define | GET_REV(val) (val & 0x07) |
| |
| #define | ID 0x00 /* Product ID Code Register */ |
| |
| #define | STATUS1 0x01 /* Chip Status Register I */ |
| |
| #define | INFORM 0x02 /* Input Format */ |
| |
| #define | OPFORM 0x03 /* Output Format Control Register */ |
| |
| #define | DLYCTR 0x04 /* Hysteresis and HSYNC Delay Control */ |
| |
| #define | OUTCTR1 0x05 /* Output Control I */ |
| |
| #define | ACNTL1 0x06 /* Analog Control Register 1 */ |
| |
| #define | CROP_HI 0x07 /* Cropping Register, High */ |
| |
| #define | VDELAY_LO 0x08 /* Vertical Delay Register, Low */ |
| |
| #define | VACTIVE_LO 0x09 /* Vertical Active Register, Low */ |
| |
| #define | HDELAY_LO 0x0A /* Horizontal Delay Register, Low */ |
| |
| #define | HACTIVE_LO 0x0B /* Horizontal Active Register, Low */ |
| |
| #define | CNTRL1 0x0C /* Control Register I */ |
| |
| #define | VSCALE_LO 0x0D /* Vertical Scaling Register, Low */ |
| |
| #define | SCALE_HI 0x0E /* Scaling Register, High */ |
| |
| #define | HSCALE_LO 0x0F /* Horizontal Scaling Register, Low */ |
| |
| #define | BRIGHT 0x10 /* BRIGHTNESS Control Register */ |
| |
| #define | CONTRAST 0x11 /* CONTRAST Control Register */ |
| |
| #define | SHARPNESS 0x12 /* SHARPNESS Control Register I */ |
| |
| #define | SAT_U 0x13 /* Chroma (U) Gain Register */ |
| |
| #define | SAT_V 0x14 /* Chroma (V) Gain Register */ |
| |
| #define | HUE 0x15 /* Hue Control Register */ |
| |
| #define | CORING1 0x17 |
| |
| #define | CORING2 0x18 /* Coring and IF compensation */ |
| |
| #define | VBICNTL 0x19 /* VBI Control Register */ |
| |
| #define | ACNTL2 0x1A /* Analog Control 2 */ |
| |
| #define | OUTCTR2 0x1B /* Output Control 2 */ |
| |
| #define | SDT 0x1C /* Standard Selection */ |
| |
| #define | SDTR 0x1D /* Standard Recognition */ |
| |
| #define | TEST 0x1F /* Test Control Register */ |
| |
| #define | CLMPG 0x20 /* Clamping Gain */ |
| |
| #define | IAGC 0x21 /* Individual AGC Gain */ |
| |
| #define | AGCGAIN 0x22 /* AGC Gain */ |
| |
| #define | PEAKWT 0x23 /* White Peak Threshold */ |
| |
| #define | CLMPL 0x24 /* Clamp level */ |
| |
| #define | SYNCT 0x25 /* Sync Amplitude */ |
| |
| #define | MISSCNT 0x26 /* Sync Miss Count Register */ |
| |
| #define | PCLAMP 0x27 /* Clamp Position Register */ |
| |
| #define | VCNTL1 0x28 /* Vertical Control I */ |
| |
| #define | VCNTL2 0x29 /* Vertical Control II */ |
| |
| #define | CKILL 0x2A /* Color Killer Level Control */ |
| |
| #define | COMB 0x2B /* Comb Filter Control */ |
| |
| #define | LDLY 0x2C /* Luma Delay and H Filter Control */ |
| |
| #define | MISC1 0x2D /* Miscellaneous Control I */ |
| |
| #define | LOOP 0x2E /* LOOP Control Register */ |
| |
| #define | MISC2 0x2F /* Miscellaneous Control II */ |
| |
| #define | MVSN 0x30 /* Macrovision Detection */ |
| |
| #define | STATUS2 0x31 /* Chip STATUS II */ |
| |
| #define | HFREF 0x32 /* H monitor */ |
| |
| #define | CLMD 0x33 /* CLAMP MODE */ |
| |
| #define | IDCNTL 0x34 /* ID Detection Control */ |
| |
| #define | CLCNTL1 0x35 /* Clamp Control I */ |
| |
| #define | ANAPLLCTL 0x4C |
| |
| #define | VBIMIN 0x4D |
| |
| #define | HSLOWCTL 0x4E |
| |
| #define | WSS3 0x4F |
| |
| #define | FILLDATA 0x50 |
| |
| #define | SDID 0x51 |
| |
| #define | DID 0x52 |
| |
| #define | WSS1 0x53 |
| |
| #define | WSS2 0x54 |
| |
| #define | VVBI 0x55 |
| |
| #define | LCTL6 0x56 |
| |
| #define | LCTL7 0x57 |
| |
| #define | LCTL8 0x58 |
| |
| #define | LCTL9 0x59 |
| |
| #define | LCTL10 0x5A |
| |
| #define | LCTL11 0x5B |
| |
| #define | LCTL12 0x5C |
| |
| #define | LCTL13 0x5D |
| |
| #define | LCTL14 0x5E |
| |
| #define | LCTL15 0x5F |
| |
| #define | LCTL16 0x60 |
| |
| #define | LCTL17 0x61 |
| |
| #define | LCTL18 0x62 |
| |
| #define | LCTL19 0x63 |
| |
| #define | LCTL20 0x64 |
| |
| #define | LCTL21 0x65 |
| |
| #define | LCTL22 0x66 |
| |
| #define | LCTL23 0x67 |
| |
| #define | LCTL24 0x68 |
| |
| #define | LCTL25 0x69 |
| |
| #define | LCTL26 0x6A |
| |
| #define | HSBEGIN 0x6B |
| |
| #define | HSEND 0x6C |
| |
| #define | OVSDLY 0x6D |
| |
| #define | OVSEND 0x6E |
| |
| #define | VBIDELAY 0x6F |
| |
| #define | FC27_ON 0x40 /* 1 : Input crystal clock frequency is 27MHz */ |
| |
| #define | FC27_FF 0x00 /* 0 : Square pixel mode. */ |
| |
| #define | IFSEL_S 0x10 /* 01 : S-video decoding */ |
| |
| #define | IFSEL_C 0x00 /* 00 : Composite video decoding */ |
| |
| #define | YSEL_M0 0x00 /* 00 : Mux0 selected */ |
| |
| #define | YSEL_M1 0x04 /* 01 : Mux1 selected */ |
| |
| #define | YSEL_M2 0x08 /* 10 : Mux2 selected */ |
| |
| #define | YSEL_M3 0x10 /* 11 : Mux3 selected */ |
| |
| #define | MODE 0x80 /* 0 : CCIR601 compatible YCrCb 4:2:2 format */ |
| |
| #define | LEN 0x40 /* 0 : 8-bit YCrCb 4:2:2 output format */ |
| |
| #define | LLCMODE 0x20 /* 1 : LLC output mode. */ |
| |
| #define | AINC 0x10 /* Serial interface auto-indexing control */ |
| |
| #define | VSCTL 0x08 /* 1 : Vertical out ctrl by DVALID */ |
| |
| #define | OEN_TRI_SEL_MASK 0x07 |
| |
| #define | OEN_TRI_SEL_ALL_ON 0x00 /* Enable output for Rev0/Rev1 */ |
| |
| #define | OEN_TRI_SEL_ALL_OFF_r0 0x06 /* All tri-stated for Rev0 */ |
| |
| #define | OEN_TRI_SEL_ALL_OFF_r1 0x07 /* All tri-stated for Rev1 */ |
| |
| #define | VSP_LO 0x00 /* 0 : VS pin output polarity is active low */ |
| |
| #define | VSP_HI 0x80 /* 1 : VS pin output polarity is active high. */ |
| |
| #define | VSSL_VSYNC 0x00 /* 0 : VSYNC */ |
| |
| #define | VSSL_VACT 0x10 /* 1 : VACT */ |
| |
| #define | VSSL_FIELD 0x20 /* 2 : FIELD */ |
| |
| #define | VSSL_VVALID 0x30 /* 3 : VVALID */ |
| |
| #define | VSSL_ZERO 0x70 /* 7 : 0 */ |
| |
| #define | HSP_LOW 0x00 /* 0 : HS pin output polarity is active low */ |
| |
| #define | HSP_HI 0x08 /* 1 : HS pin output polarity is active high.*/ |
| |
| #define | HSSL_HACT 0x00 /* 0 : HACT */ |
| |
| #define | HSSL_HSYNC 0x01 /* 1 : HSYNC */ |
| |
| #define | HSSL_DVALID 0x02 /* 2 : DVALID */ |
| |
| #define | HSSL_HLOCK 0x03 /* 3 : HLOCK */ |
| |
| #define | HSSL_ASYNCW 0x04 /* 4 : ASYNCW */ |
| |
| #define | HSSL_ZERO 0x07 /* 7 : 0 */ |
| |
| #define | SRESET |
| |
| #define | ACNTL1_PDN_MASK 0x0e |
| |
| #define | CLK_PDN 0x08 /* system clock power down */ |
| |
| #define | Y_PDN 0x04 /* Luma ADC power down */ |
| |
| #define | C_PDN 0x02 /* Chroma ADC power down */ |
| |
| #define | ACNTL2_PDN_MASK 0x40 |
| |
| #define | PLL_PDN 0x40 /* PLL power down */ |
| |
| #define | RTSEL_MASK 0x07 |
| |
| #define | RTSEL_VLOSS 0x00 /* 0000 = Video loss */ |
| |
| #define | RTSEL_HLOCK 0x01 /* 0001 = H-lock */ |
| |
| #define | RTSEL_SLOCK 0x02 /* 0010 = S-lock */ |
| |
| #define | RTSEL_VLOCK 0x03 /* 0011 = V-lock */ |
| |
| #define | RTSEL_MONO 0x04 /* 0100 = MONO */ |
| |
| #define | RTSEL_DET50 0x05 /* 0101 = DET50 */ |
| |
| #define | RTSEL_FIELD 0x06 /* 0110 = FIELD */ |
| |
| #define | RTSEL_RTCO 0x07 /* 0111 = RTCO ( Real Time Control ) */ |
| |
| #define | HSYNC_START 0x0260 |
| |
| #define | HSYNC_END 0x0300 |
| |
1.8.2