|
| #define | MINOR_VERSION_NUM_MASK UFS_MASK(0xFFFF, 0) |
| |
| #define | MAJOR_VERSION_NUM_MASK UFS_MASK(0xFFFF, 16) |
| |
| #define | DEVICE_CLASS UFS_MASK(0xFFFF, 0) |
| |
| #define | DEVICE_ID UFS_MASK(0xFF, 24) |
| |
| #define | MANUFACTURE_ID_MASK UFS_MASK(0xFFFF, 0) |
| |
| #define | PRODUCT_ID_MASK UFS_MASK(0xFFFF, 16) |
| |
| #define | UFS_BIT(x) (1L << (x)) |
| |
| #define | UTP_TRANSFER_REQ_COMPL UFS_BIT(0) |
| |
| #define | UIC_DME_END_PT_RESET UFS_BIT(1) |
| |
| #define | UIC_ERROR UFS_BIT(2) |
| |
| #define | UIC_TEST_MODE UFS_BIT(3) |
| |
| #define | UIC_POWER_MODE UFS_BIT(4) |
| |
| #define | UIC_HIBERNATE_EXIT UFS_BIT(5) |
| |
| #define | UIC_HIBERNATE_ENTER UFS_BIT(6) |
| |
| #define | UIC_LINK_LOST UFS_BIT(7) |
| |
| #define | UIC_LINK_STARTUP UFS_BIT(8) |
| |
| #define | UTP_TASK_REQ_COMPL UFS_BIT(9) |
| |
| #define | UIC_COMMAND_COMPL UFS_BIT(10) |
| |
| #define | DEVICE_FATAL_ERROR UFS_BIT(11) |
| |
| #define | CONTROLLER_FATAL_ERROR UFS_BIT(16) |
| |
| #define | SYSTEM_BUS_FATAL_ERROR UFS_BIT(17) |
| |
| #define | UFSHCD_ERROR_MASK |
| |
| #define | INT_FATAL_ERRORS |
| |
| #define | DEVICE_PRESENT UFS_BIT(0) |
| |
| #define | UTP_TRANSFER_REQ_LIST_READY UFS_BIT(1) |
| |
| #define | UTP_TASK_REQ_LIST_READY UFS_BIT(2) |
| |
| #define | UIC_COMMAND_READY UFS_BIT(3) |
| |
| #define | HOST_ERROR_INDICATOR UFS_BIT(4) |
| |
| #define | DEVICE_ERROR_INDICATOR UFS_BIT(5) |
| |
| #define | UIC_POWER_MODE_CHANGE_REQ_STATUS_MASK UFS_MASK(0x7, 8) |
| |
| #define | CONTROLLER_ENABLE UFS_BIT(0) |
| |
| #define | CONTROLLER_DISABLE 0x0 |
| |
| #define | UIC_PHY_ADAPTER_LAYER_ERROR UFS_BIT(31) |
| |
| #define | UIC_PHY_ADAPTER_LAYER_ERROR_CODE_MASK 0x1F |
| |
| #define | UIC_DATA_LINK_LAYER_ERROR UFS_BIT(31) |
| |
| #define | UIC_DATA_LINK_LAYER_ERROR_CODE_MASK 0x7FFF |
| |
| #define | UIC_DATA_LINK_LAYER_ERROR_PA_INIT 0x2000 |
| |
| #define | UIC_NETWORK_LAYER_ERROR UFS_BIT(31) |
| |
| #define | UIC_NETWORK_LAYER_ERROR_CODE_MASK 0x7 |
| |
| #define | UIC_TRANSPORT_LAYER_ERROR UFS_BIT(31) |
| |
| #define | UIC_TRANSPORT_LAYER_ERROR_CODE_MASK 0x7F |
| |
| #define | UIC_DME_ERROR UFS_BIT(31) |
| |
| #define | UIC_DME_ERROR_CODE_MASK 0x1 |
| |
| #define | INT_AGGR_TIMEOUT_VAL_MASK 0xFF |
| |
| #define | INT_AGGR_COUNTER_THRESHOLD_MASK UFS_MASK(0x1F, 8) |
| |
| #define | INT_AGGR_COUNTER_AND_TIMER_RESET UFS_BIT(16) |
| |
| #define | INT_AGGR_STATUS_BIT UFS_BIT(20) |
| |
| #define | INT_AGGR_PARAM_WRITE UFS_BIT(24) |
| |
| #define | INT_AGGR_ENABLE UFS_BIT(31) |
| |
| #define | UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT UFS_BIT(0) |
| |
| #define | UTP_TASK_REQ_LIST_RUN_STOP_BIT UFS_BIT(0) |
| |
| #define | COMMAND_OPCODE_MASK 0xFF |
| |
| #define | GEN_SELECTOR_INDEX_MASK 0xFFFF |
| |
| #define | MIB_ATTRIBUTE_MASK UFS_MASK(0xFFFF, 16) |
| |
| #define | RESET_LEVEL 0xFF |
| |
| #define | ATTR_SET_TYPE_MASK UFS_MASK(0xFF, 16) |
| |
| #define | CONFIG_RESULT_CODE_MASK 0xFF |
| |
| #define | GENERIC_ERROR_CODE_MASK 0xFF |
| |
| #define | MASK_UIC_COMMAND_RESULT 0xFF |
| |
| #define | INT_AGGR_COUNTER_THRESHOLD_VALUE (0x1F << 8) |
| |
| #define | INT_AGGR_TIMEOUT_VALUE (0x02) |
| |
|
| enum | { TASK_REQ_UPIU_SIZE_DWORDS = 8,
TASK_RSP_UPIU_SIZE_DWORDS = 8,
ALIGNED_UPIU_SIZE = 128
} |
| |
| enum | {
REG_CONTROLLER_CAPABILITIES = 0x00,
REG_UFS_VERSION = 0x08,
REG_CONTROLLER_DEV_ID = 0x10,
REG_CONTROLLER_PROD_ID = 0x14,
REG_INTERRUPT_STATUS = 0x20,
REG_INTERRUPT_ENABLE = 0x24,
REG_CONTROLLER_STATUS = 0x30,
REG_CONTROLLER_ENABLE = 0x34,
REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER = 0x38,
REG_UIC_ERROR_CODE_DATA_LINK_LAYER = 0x3C,
REG_UIC_ERROR_CODE_NETWORK_LAYER = 0x40,
REG_UIC_ERROR_CODE_TRANSPORT_LAYER = 0x44,
REG_UIC_ERROR_CODE_DME = 0x48,
REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL = 0x4C,
REG_UTP_TRANSFER_REQ_LIST_BASE_L = 0x50,
REG_UTP_TRANSFER_REQ_LIST_BASE_H = 0x54,
REG_UTP_TRANSFER_REQ_DOOR_BELL = 0x58,
REG_UTP_TRANSFER_REQ_LIST_CLEAR = 0x5C,
REG_UTP_TRANSFER_REQ_LIST_RUN_STOP = 0x60,
REG_UTP_TASK_REQ_LIST_BASE_L = 0x70,
REG_UTP_TASK_REQ_LIST_BASE_H = 0x74,
REG_UTP_TASK_REQ_DOOR_BELL = 0x78,
REG_UTP_TASK_REQ_LIST_CLEAR = 0x7C,
REG_UTP_TASK_REQ_LIST_RUN_STOP = 0x80,
REG_UIC_COMMAND = 0x90,
REG_UIC_COMMAND_ARG_1 = 0x94,
REG_UIC_COMMAND_ARG_2 = 0x98,
REG_UIC_COMMAND_ARG_3 = 0x9C
} |
| |
| enum | {
MASK_TRANSFER_REQUESTS_SLOTS = 0x0000001F,
MASK_TASK_MANAGEMENT_REQUEST_SLOTS = 0x00070000,
MASK_64_ADDRESSING_SUPPORT = 0x01000000,
MASK_OUT_OF_ORDER_DATA_DELIVERY_SUPPORT = 0x02000000,
MASK_UIC_DME_TEST_MODE_SUPPORT = 0x04000000
} |
| |
| enum | { UFSHCI_VERSION_10 = 0x00010000,
UFSHCI_VERSION_11 = 0x00010100
} |
| |
| enum | {
UIC_CMD_DME_GET = 0x01,
UIC_CMD_DME_SET = 0x02,
UIC_CMD_DME_PEER_GET = 0x03,
UIC_CMD_DME_PEER_SET = 0x04,
UIC_CMD_DME_POWERON = 0x10,
UIC_CMD_DME_POWEROFF = 0x11,
UIC_CMD_DME_ENABLE = 0x12,
UIC_CMD_DME_RESET = 0x14,
UIC_CMD_DME_END_PT_RST = 0x15,
UIC_CMD_DME_LINK_STARTUP = 0x16,
UIC_CMD_DME_HIBER_ENTER = 0x17,
UIC_CMD_DME_HIBER_EXIT = 0x18,
UIC_CMD_DME_TEST_MODE = 0x1A
} |
| |
| enum | {
UIC_CMD_RESULT_SUCCESS = 0x00,
UIC_CMD_RESULT_INVALID_ATTR = 0x01,
UIC_CMD_RESULT_FAILURE = 0x01,
UIC_CMD_RESULT_INVALID_ATTR_VALUE = 0x02,
UIC_CMD_RESULT_READ_ONLY_ATTR = 0x03,
UIC_CMD_RESULT_WRITE_ONLY_ATTR = 0x04,
UIC_CMD_RESULT_BAD_INDEX = 0x05,
UIC_CMD_RESULT_LOCKED_ATTR = 0x06,
UIC_CMD_RESULT_BAD_TEST_FEATURE_INDEX = 0x07,
UIC_CMD_RESULT_PEER_COMM_FAILURE = 0x08,
UIC_CMD_RESULT_BUSY = 0x09,
UIC_CMD_RESULT_DME_FAILURE = 0x0A
} |
| |
| enum | { INTERRUPT_DISABLE_MASK_10 = 0xFFFF,
INTERRUPT_DISABLE_MASK_11 = 0x0
} |
| |
| enum | { UTP_CMD_TYPE_SCSI = 0x0,
UTP_CMD_TYPE_UFS = 0x1,
UTP_CMD_TYPE_DEV_MANAGE = 0x2
} |
| |
| enum | { UTP_SCSI_COMMAND = 0x00000000,
UTP_NATIVE_UFS_COMMAND = 0x10000000,
UTP_DEVICE_MANAGEMENT_FUNCTION = 0x20000000,
UTP_REQ_DESC_INT_CMD = 0x01000000
} |
| |
| enum | { UTP_NO_DATA_TRANSFER = 0x00000000,
UTP_HOST_TO_DEVICE = 0x02000000,
UTP_DEVICE_TO_HOST = 0x04000000
} |
| |
| enum | {
OCS_SUCCESS = 0x0,
OCS_INVALID_CMD_TABLE_ATTR = 0x1,
OCS_INVALID_PRDT_ATTR = 0x2,
OCS_MISMATCH_DATA_BUF_SIZE = 0x3,
OCS_MISMATCH_RESP_UPIU_SIZE = 0x4,
OCS_PEER_COMM_FAILURE = 0x5,
OCS_ABORTED = 0x6,
OCS_FATAL_ERROR = 0x7,
OCS_INVALID_COMMAND_STATUS = 0x0F,
MASK_OCS = 0x0F
} |
| |
1.8.2