cvmx_pow_tag_store_addr_t Union Reference

#include <cvmx-pow.h>

Data Fields
uint64_t	u64
struct {
uint64_t   mem_reg:2
uint64_t   reserved_49_61:13
uint64_t   is_io:1
uint64_t   did:8
uint64_t   reserved_36_39:4
uint64_t   addr:36
}	stag

Detailed Description

This structure describes the address used for stores to the POW. The store address is meaningful on stores to the POW. The hardware assumes that an aligned 64-bit store was used for all these stores. Note the assumption that the work queue entry is aligned on an 8-byte boundary (since the low-order 3 address bits must be zero). Note that not all fields are used by all operations.

NOTE: The following is the behavior of the pending switch bit at the PP for POW stores (i.e. when did<7:3> == 0xc)

• did<2:0> == 0 => pending switch bit is set
• did<2:0> == 1 => no affect on the pending switch bit
• did<2:0> == 3 => pending switch bit is cleared
• did<2:0> == 7 => no affect on the pending switch bit
• did<2:0> == others => must not be used
• No other loads/stores have an affect on the pending switch bit
• The switch bus from POW can clear the pending switch bit

NOTE: did<2:0> == 2 is used by the HW for a special single-cycle ADDWQ command that only contains the pointer). SW must never use did<2:0> == 2.

Definition at line 958 of file cvmx-pow.h.

Field Documentation

uint64_t addr

Definition at line 973 of file cvmx-pow.h.

uint64_t did

Definition at line 970 of file cvmx-pow.h.

uint64_t is_io

Definition at line 968 of file cvmx-pow.h.

uint64_t mem_reg

Definition at line 966 of file cvmx-pow.h.

uint64_t reserved_36_39

Definition at line 971 of file cvmx-pow.h.

uint64_t reserved_49_61

Definition at line 967 of file cvmx-pow.h.

struct { ... } stag

uint64_t u64

Unsigned 64 bit integer representation of store address

Definition at line 962 of file cvmx-pow.h.

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The documentation for this union was generated from the following file:

• arch/mips/include/asm/octeon/cvmx-pow.h