39 #define IA64_TR_VM_DATA 7
46 #define VP_INITIALIZE 1UL
47 #define VP_FR_PMC 1UL<<1
48 #define VP_OPCODE 1UL<<8
49 #define VP_CAUSE 1UL<<9
50 #define VP_FW_ACC 1UL<<63
53 #define VP_INIT_ENV_INITALIZE (VP_INITIALIZE | VP_FR_PMC |\
54 VP_OPCODE | VP_CAUSE | VP_FW_ACC)
56 #define VP_INIT_ENV VP_FR_PMC | VP_OPCODE | VP_CAUSE | VP_FW_ACC
58 #define PAL_VP_CREATE 265
62 #define PAL_VP_ENV_INFO 266
64 #define PAL_VP_EXIT_ENV 267
66 #define PAL_VP_INIT_ENV 268
68 #define PAL_VP_REGISTER 269
70 #define PAL_VP_RESUME 270
72 #define PAL_VP_RESTORE 270
74 #define PAL_VP_SUSPEND 271
76 #define PAL_VP_SAVE 271
80 #define PAL_VP_TERMINATE 272
166 #define PAL_PROC_VM_BIT (1UL << 40)
167 #define PAL_PROC_VMSW_BIT (1UL << 54)
169 static inline s64 ia64_pal_vp_env_info(
u64 *buffer_size,
174 *buffer_size = iprv.
v0;
175 *vp_env_info = iprv.
v1;
179 static inline s64 ia64_pal_vp_exit_env(
u64 iva)
187 static inline s64 ia64_pal_vp_init_env(
u64 config_options,
u64 pbase_addr,
188 u64 vbase_addr,
u64 *vsa_base)
199 static inline s64 ia64_pal_vp_restore(
u64 *
vpd,
u64 pal_proc_vector)
208 static inline s64 ia64_pal_vp_save(
u64 *vpd,
u64 pal_proc_vector)
220 #define VPD_VAC_START_OFFSET 0
221 #define VPD_VDC_START_OFFSET 8
222 #define VPD_VHPI_START_OFFSET 256
223 #define VPD_VGR_START_OFFSET 1024
224 #define VPD_VBGR_START_OFFSET 1152
225 #define VPD_VNAT_START_OFFSET 1280
226 #define VPD_VBNAT_START_OFFSET 1288
227 #define VPD_VCPUID_START_OFFSET 1296
228 #define VPD_VPSR_START_OFFSET 1424
229 #define VPD_VPR_START_OFFSET 1432
230 #define VPD_VRSE_CFLE_START_OFFSET 1440
231 #define VPD_VCR_START_OFFSET 2048
232 #define VPD_VTPR_START_OFFSET 2576
233 #define VPD_VRR_START_OFFSET 3072
234 #define VPD_VMM_VAIL_START_OFFSET 31744
238 #define EVENT_MOV_TO_AR 1
239 #define EVENT_MOV_TO_AR_IMM 2
240 #define EVENT_MOV_FROM_AR 3
241 #define EVENT_MOV_TO_CR 4
242 #define EVENT_MOV_FROM_CR 5
243 #define EVENT_MOV_TO_PSR 6
244 #define EVENT_MOV_FROM_PSR 7
245 #define EVENT_ITC_D 8
246 #define EVENT_ITC_I 9
247 #define EVENT_MOV_TO_RR 10
248 #define EVENT_MOV_TO_DBR 11
249 #define EVENT_MOV_TO_IBR 12
250 #define EVENT_MOV_TO_PKR 13
251 #define EVENT_MOV_TO_PMC 14
252 #define EVENT_MOV_TO_PMD 15
253 #define EVENT_ITR_D 16
254 #define EVENT_ITR_I 17
255 #define EVENT_MOV_FROM_RR 18
256 #define EVENT_MOV_FROM_DBR 19
257 #define EVENT_MOV_FROM_IBR 20
258 #define EVENT_MOV_FROM_PKR 21
259 #define EVENT_MOV_FROM_PMC 22
260 #define EVENT_MOV_FROM_CPUID 23
263 #define EVENT_PTC_L 26
264 #define EVENT_PTC_G 27
265 #define EVENT_PTC_GA 28
266 #define EVENT_PTR_D 29
267 #define EVENT_PTR_I 30
268 #define EVENT_THASH 31
269 #define EVENT_TTAG 32
272 #define EVENT_PTC_E 35
273 #define EVENT_COVER 36
275 #define EVENT_BSW_0 38
276 #define EVENT_BSW_1 39
277 #define EVENT_VMSW 40
280 #define PAL_VPS_RESUME_NORMAL 0x0000
281 #define PAL_VPS_RESUME_HANDLER 0x0400
282 #define PAL_VPS_SYNC_READ 0x0800
283 #define PAL_VPS_SYNC_WRITE 0x0c00
284 #define PAL_VPS_SET_PENDING_INTERRUPT 0x1000
285 #define PAL_VPS_THASH 0x1400
286 #define PAL_VPS_TTAG 0x1800
287 #define PAL_VPS_RESTORE 0x1c00
288 #define PAL_VPS_SAVE 0x2000