|
| #define | PAL_CACHE_FLUSH 1 /* flush i/d cache */ |
| |
| #define | PAL_CACHE_INFO 2 /* get detailed i/d cache info */ |
| |
| #define | PAL_CACHE_INIT 3 /* initialize i/d cache */ |
| |
| #define | PAL_CACHE_SUMMARY 4 /* get summary of cache hierarchy */ |
| |
| #define | PAL_MEM_ATTRIB 5 /* list supported memory attributes */ |
| |
| #define | PAL_PTCE_INFO 6 /* purge TLB info */ |
| |
| #define | PAL_VM_INFO 7 /* return supported virtual memory features */ |
| |
| #define | PAL_VM_SUMMARY 8 /* return summary on supported vm features */ |
| |
| #define | PAL_BUS_GET_FEATURES 9 /* return processor bus interface features settings */ |
| |
| #define | PAL_BUS_SET_FEATURES 10 /* set processor bus features */ |
| |
| #define | PAL_DEBUG_INFO 11 /* get number of debug registers */ |
| |
| #define | PAL_FIXED_ADDR 12 /* get fixed component of processors's directed address */ |
| |
| #define | PAL_FREQ_BASE 13 /* base frequency of the platform */ |
| |
| #define | PAL_FREQ_RATIOS 14 /* ratio of processor, bus and ITC frequency */ |
| |
| #define | PAL_PERF_MON_INFO 15 /* return performance monitor info */ |
| |
| #define | PAL_PLATFORM_ADDR 16 /* set processor interrupt block and IO port space addr */ |
| |
| #define | PAL_PROC_GET_FEATURES 17 /* get configurable processor features & settings */ |
| |
| #define | PAL_PROC_SET_FEATURES 18 /* enable/disable configurable processor features */ |
| |
| #define | PAL_RSE_INFO 19 /* return rse information */ |
| |
| #define | PAL_VERSION 20 /* return version of PAL code */ |
| |
| #define | PAL_MC_CLEAR_LOG 21 /* clear all processor log info */ |
| |
| #define | PAL_MC_DRAIN 22 /* drain operations which could result in an MCA */ |
| |
| #define | PAL_MC_EXPECTED 23 /* set/reset expected MCA indicator */ |
| |
| #define | PAL_MC_DYNAMIC_STATE 24 /* get processor dynamic state */ |
| |
| #define | PAL_MC_ERROR_INFO 25 /* get processor MCA info and static state */ |
| |
| #define | PAL_MC_RESUME 26 /* Return to interrupted process */ |
| |
| #define | PAL_MC_REGISTER_MEM 27 /* Register memory for PAL to use during MCAs and inits */ |
| |
| #define | PAL_HALT 28 /* enter the low power HALT state */ |
| |
| #define | PAL_HALT_LIGHT 29 /* enter the low power light halt state*/ |
| |
| #define | PAL_COPY_INFO 30 /* returns info needed to relocate PAL */ |
| |
| #define | PAL_CACHE_LINE_INIT 31 /* init tags & data of cache line */ |
| |
| #define | PAL_PMI_ENTRYPOINT 32 /* register PMI memory entry points with the processor */ |
| |
| #define | PAL_ENTER_IA_32_ENV 33 /* enter IA-32 system environment */ |
| |
| #define | PAL_VM_PAGE_SIZE 34 /* return vm TC and page walker page sizes */ |
| |
| #define | PAL_MEM_FOR_TEST 37 /* get amount of memory needed for late processor test */ |
| |
| #define | PAL_CACHE_PROT_INFO 38 /* get i/d cache protection info */ |
| |
| #define | PAL_REGISTER_INFO 39 /* return AR and CR register information*/ |
| |
| #define | PAL_SHUTDOWN 40 /* enter processor shutdown state */ |
| |
| #define | PAL_PREFETCH_VISIBILITY 41 /* Make Processor Prefetches Visible */ |
| |
| #define | PAL_LOGICAL_TO_PHYSICAL 42 /* returns information on logical to physical processor mapping */ |
| |
| #define | PAL_CACHE_SHARED_INFO 43 /* returns information on caches shared by logical processor */ |
| |
| #define | PAL_GET_HW_POLICY 48 /* Get current hardware resource sharing policy */ |
| |
| #define | PAL_SET_HW_POLICY 49 /* Set current hardware resource sharing policy */ |
| |
| #define | PAL_VP_INFO 50 /* Information about virtual processor features */ |
| |
| #define | PAL_MC_HW_TRACKING 51 /* Hardware tracking status */ |
| |
| #define | PAL_COPY_PAL 256 /* relocate PAL procedures and PAL PMI */ |
| |
| #define | PAL_HALT_INFO 257 /* return the low power capabilities of processor */ |
| |
| #define | PAL_TEST_PROC 258 /* perform late processor self-test */ |
| |
| #define | PAL_CACHE_READ 259 /* read tag & data of cacheline for diagnostic testing */ |
| |
| #define | PAL_CACHE_WRITE 260 /* write tag & data of cacheline for diagnostic testing */ |
| |
| #define | PAL_VM_TR_READ 261 /* read contents of translation register */ |
| |
| #define | PAL_GET_PSTATE 262 /* get the current P-state */ |
| |
| #define | PAL_SET_PSTATE 263 /* set the P-state */ |
| |
| #define | PAL_BRAND_INFO 274 /* Processor branding information */ |
| |
| #define | PAL_GET_PSTATE_TYPE_LASTSET 0 |
| |
| #define | PAL_GET_PSTATE_TYPE_AVGANDRESET 1 |
| |
| #define | PAL_GET_PSTATE_TYPE_AVGNORESET 2 |
| |
| #define | PAL_GET_PSTATE_TYPE_INSTANT 3 |
| |
| #define | PAL_MC_ERROR_INJECT 276 /* Injects processor error or returns injection capabilities */ |
| |
| #define | PAL_STATUS_SUCCESS 0 /* No error */ |
| |
| #define | PAL_STATUS_UNIMPLEMENTED (-1) /* Unimplemented procedure */ |
| |
| #define | PAL_STATUS_EINVAL (-2) /* Invalid argument */ |
| |
| #define | PAL_STATUS_ERROR (-3) /* Error */ |
| |
| #define | PAL_STATUS_CACHE_INIT_FAIL |
| |
| #define | PAL_STATUS_REQUIRES_MEMORY (-9) /* Call requires PAL memory buffer */ |
| |
| #define | PAL_CACHE_LEVEL_L0 0 /* L0 */ |
| |
| #define | PAL_CACHE_LEVEL_L1 1 /* L1 */ |
| |
| #define | PAL_CACHE_LEVEL_L2 2 /* L2 */ |
| |
| #define | PAL_CACHE_TYPE_INSTRUCTION 1 /* Instruction cache */ |
| |
| #define | PAL_CACHE_TYPE_DATA 2 /* Data or unified cache */ |
| |
| #define | PAL_CACHE_TYPE_INSTRUCTION_DATA 3 /* Both Data & Instruction */ |
| |
| #define | PAL_CACHE_FLUSH_INVALIDATE 1 /* Invalidate clean lines */ |
| |
| #define | PAL_CACHE_FLUSH_CHK_INTRS 2 /* check for interrupts/mc while flushing */ |
| |
| #define | PAL_CACHE_LINE_STATE_INVALID 0 /* Invalid */ |
| |
| #define | PAL_CACHE_LINE_STATE_SHARED 1 /* Shared */ |
| |
| #define | PAL_CACHE_LINE_STATE_EXCLUSIVE 2 /* Exclusive */ |
| |
| #define | PAL_CACHE_LINE_STATE_MODIFIED 3 /* Modified */ |
| |
| #define | pcci_ld_hints pcci_info_1.pcci1_bits.load_hints |
| |
| #define | pcci_st_hints pcci_info_1.pcci1_bits.store_hints |
| |
| #define | pcci_ld_latency pcci_info_1.pcci1_bits.load_latency |
| |
| #define | pcci_st_latency pcci_info_1.pcci1_bits.store_latency |
| |
| #define | pcci_stride pcci_info_1.pcci1_bits.stride |
| |
| #define | pcci_line_size pcci_info_1.pcci1_bits.line_size |
| |
| #define | pcci_assoc pcci_info_1.pcci1_bits.associativity |
| |
| #define | pcci_cache_attr pcci_info_1.pcci1_bits.at |
| |
| #define | pcci_unified pcci_info_1.pcci1_bits.u |
| |
| #define | pcci_tag_msb pcci_info_2.pcci2_bits.tag_ms_bit |
| |
| #define | pcci_tag_lsb pcci_info_2.pcci2_bits.tag_ls_bit |
| |
| #define | pcci_alias_boundary pcci_info_2.pcci2_bits.alias_boundary |
| |
| #define | pcci_cache_size pcci_info_2.pcci2_bits.cache_size |
| |
| #define | PAL_CACHE_ATTR_WT 0 /* Write through cache */ |
| |
| #define | PAL_CACHE_ATTR_WB 1 /* Write back cache */ |
| |
| #define | PAL_CACHE_ATTR_WT_OR_WB |
| |
| #define | PAL_CACHE_HINT_TEMP_1 0 /* Temporal level 1 */ |
| |
| #define | PAL_CACHE_HINT_NTEMP_1 1 /* Non-temporal level 1 */ |
| |
| #define | PAL_CACHE_HINT_NTEMP_ALL 3 /* Non-temporal all levels */ |
| |
| #define | pcpi_cache_prot_part pcp_info.t_d |
| |
| #define | pcpi_prot_method pcp_info.method |
| |
| #define | pcpi_prot_bits pcp_info.prot_bits |
| |
| #define | pcpi_tagprot_msb pcp_info.tagprot_msb |
| |
| #define | pcpi_tagprot_lsb pcp_info.tagprot_lsb |
| |
| #define | pcpi_data_bits pcp_info.data_bits |
| |
| #define | PAL_CACHE_PROT_PART_DATA 0 /* Data protection */ |
| |
| #define | PAL_CACHE_PROT_PART_TAG 1 /* Tag protection */ |
| |
| #define | PAL_CACHE_PROT_PART_TAG_DATA |
| |
| #define | PAL_CACHE_PROT_PART_DATA_TAG |
| |
| #define | PAL_CACHE_PROT_PART_MAX 6 |
| |
| #define | PAL_CACHE_PROT_METHOD_NONE 0 /* No protection */ |
| |
| #define | PAL_CACHE_PROT_METHOD_ODD_PARITY 1 /* Odd parity */ |
| |
| #define | PAL_CACHE_PROT_METHOD_EVEN_PARITY 2 /* Even parity */ |
| |
| #define | PAL_CACHE_PROT_METHOD_ECC 3 /* ECC protection */ |
| |
| #define | pclid_read_part pclid_info_read.part |
| |
| #define | pclid_read_way pclid_info_read.way |
| |
| #define | pclid_read_level pclid_info_read.level |
| |
| #define | pclid_read_cache_type pclid_info_read.cache_type |
| |
| #define | pclid_write_trigger pclid_info_write.trigger |
| |
| #define | pclid_write_length pclid_info_write.length |
| |
| #define | pclid_write_start pclid_info_write.start |
| |
| #define | pclid_write_mesi pclid_info_write.mesi |
| |
| #define | pclid_write_part pclid_info_write.part |
| |
| #define | pclid_write_way pclid_info_write.way |
| |
| #define | pclid_write_level pclid_info_write.level |
| |
| #define | pclid_write_cache_type pclid_info_write.cache_type |
| |
| #define | PAL_CACHE_LINE_ID_PART_DATA 0 /* Data */ |
| |
| #define | PAL_CACHE_LINE_ID_PART_TAG 1 /* Tag */ |
| |
| #define | PAL_CACHE_LINE_ID_PART_DATA_PROT 2 /* Data protection */ |
| |
| #define | PAL_CACHE_LINE_ID_PART_TAG_PROT 3 /* Tag protection */ |
| |
| #define | PAL_CACHE_LINE_ID_PART_DATA_TAG_PROT |
| |
| #define | PAL_MC_PENDING_MCA (1 << 0) |
| |
| #define | PAL_MC_PENDING_INIT (1 << 1) |
| |
| #define | PAL_MC_INFO_PROCESSOR 0 /* Processor */ |
| |
| #define | PAL_MC_INFO_CACHE_CHECK 1 /* Cache check */ |
| |
| #define | PAL_MC_INFO_TLB_CHECK 2 /* Tlb check */ |
| |
| #define | PAL_MC_INFO_BUS_CHECK 3 /* Bus check */ |
| |
| #define | PAL_MC_INFO_REQ_ADDR 4 /* Requestor address */ |
| |
| #define | PAL_MC_INFO_RESP_ADDR 5 /* Responder address */ |
| |
| #define | PAL_MC_INFO_TARGET_ADDR 6 /* Target address */ |
| |
| #define | PAL_MC_INFO_IMPL_DEP |
| |
| #define | PAL_TLB_CHECK_OP_PURGE 8 |
| |
| #define | pmci_proc_unknown_check pme_processor.uc |
| |
| #define | pmci_proc_bus_check pme_processor.bc |
| |
| #define | pmci_proc_tlb_check pme_processor.tc |
| |
| #define | pmci_proc_cache_check pme_processor.cc |
| |
| #define | pmci_proc_dynamic_state_size pme_processor.dsize |
| |
| #define | pmci_proc_gpr_valid pme_processor.gr |
| |
| #define | pmci_proc_preserved_bank0_gpr_valid pme_processor.b0 |
| |
| #define | pmci_proc_preserved_bank1_gpr_valid pme_processor.b1 |
| |
| #define | pmci_proc_fp_valid pme_processor.fp |
| |
| #define | pmci_proc_predicate_regs_valid pme_processor.pr |
| |
| #define | pmci_proc_branch_regs_valid pme_processor.br |
| |
| #define | pmci_proc_app_regs_valid pme_processor.ar |
| |
| #define | pmci_proc_region_regs_valid pme_processor.rr |
| |
| #define | pmci_proc_translation_regs_valid pme_processor.tr |
| |
| #define | pmci_proc_debug_regs_valid pme_processor.dr |
| |
| #define | pmci_proc_perf_counters_valid pme_processor.pc |
| |
| #define | pmci_proc_control_regs_valid pme_processor.cr |
| |
| #define | pmci_proc_machine_check_expected pme_processor.ex |
| |
| #define | pmci_proc_machine_check_corrected pme_processor.cm |
| |
| #define | pmci_proc_rse_valid pme_processor.rs |
| |
| #define | pmci_proc_machine_check_or_init pme_processor.in |
| |
| #define | pmci_proc_dynamic_state_valid pme_processor.dy |
| |
| #define | pmci_proc_operation pme_processor.op |
| |
| #define | pmci_proc_trap_lost pme_processor.tl |
| |
| #define | pmci_proc_hardware_damage pme_processor.hd |
| |
| #define | pmci_proc_uncontained_storage_damage pme_processor.us |
| |
| #define | pmci_proc_machine_check_isolated pme_processor.ci |
| |
| #define | pmci_proc_continuable pme_processor.co |
| |
| #define | pmci_proc_storage_intergrity_synced pme_processor.sy |
| |
| #define | pmci_proc_min_state_save_area_regd pme_processor.mn |
| |
| #define | pmci_proc_distinct_multiple_errors pme_processor.me |
| |
| #define | pmci_proc_pal_attempted_rendezvous pme_processor.ra |
| |
| #define | pmci_proc_pal_rendezvous_complete pme_processor.rz |
| |
| #define | pmci_cache_level pme_cache.level |
| |
| #define | pmci_cache_line_state pme_cache.mesi |
| |
| #define | pmci_cache_line_state_valid pme_cache.mv |
| |
| #define | pmci_cache_line_index pme_cache.index |
| |
| #define | pmci_cache_instr_cache_fail pme_cache.ic |
| |
| #define | pmci_cache_data_cache_fail pme_cache.dc |
| |
| #define | pmci_cache_line_tag_fail pme_cache.tl |
| |
| #define | pmci_cache_line_data_fail pme_cache.dl |
| |
| #define | pmci_cache_operation pme_cache.op |
| |
| #define | pmci_cache_way_valid pme_cache.wv |
| |
| #define | pmci_cache_target_address_valid pme_cache.tv |
| |
| #define | pmci_cache_way pme_cache.way |
| |
| #define | pmci_cache_mc pme_cache.mc |
| |
| #define | pmci_tlb_instr_translation_cache_fail pme_tlb.itc |
| |
| #define | pmci_tlb_data_translation_cache_fail pme_tlb.dtc |
| |
| #define | pmci_tlb_instr_translation_reg_fail pme_tlb.itr |
| |
| #define | pmci_tlb_data_translation_reg_fail pme_tlb.dtr |
| |
| #define | pmci_tlb_translation_reg_slot pme_tlb.tr_slot |
| |
| #define | pmci_tlb_mc pme_tlb.mc |
| |
| #define | pmci_bus_status_info pme_bus.bsi |
| |
| #define | pmci_bus_req_address_valid pme_bus.rq |
| |
| #define | pmci_bus_resp_address_valid pme_bus.rp |
| |
| #define | pmci_bus_target_address_valid pme_bus.tv |
| |
| #define | pmci_bus_error_severity pme_bus.sev |
| |
| #define | pmci_bus_transaction_type pme_bus.type |
| |
| #define | pmci_bus_cache_cache_transfer pme_bus.cc |
| |
| #define | pmci_bus_transaction_size pme_bus.size |
| |
| #define | pmci_bus_internal_error pme_bus.ib |
| |
| #define | pmci_bus_external_error pme_bus.eb |
| |
| #define | pmci_bus_mc pme_bus.mc |
| |
| #define | PAL_CALL(iprv, a0, a1, a2, a3) |
| |
| #define | PAL_CALL_STK(iprv, a0, a1, a2, a3) |
| |
| #define | PAL_CALL_PHYS(iprv, a0, a1, a2, a3) |
| |
| #define | PAL_CALL_PHYS_STK(iprv, a0, a1, a2, a3) |
| |
| #define | tc_reduce_tr pal_tc_info_s.reduce_tr |
| |
| #define | tc_unified pal_tc_info_s.unified |
| |
| #define | tc_pf pal_tc_info_s.pf |
| |
| #define | tc_num_entries pal_tc_info_s.num_entries |
| |
| #define | tc_associativity pal_tc_info_s.associativity |
| |
| #define | tc_num_sets pal_tc_info_s.num_sets |
| |
| #define | PAL_MAX_PURGES 0xFFFF /* all ones is means unlimited */ |
| |
| #define | PAL_VISIBILITY_VIRTUAL 0 |
| |
| #define | PAL_VISIBILITY_PHYSICAL 1 |
| |
| #define | PAL_VISIBILITY_OK 1 |
| |
| #define | PAL_VISIBILITY_OK_REMOTE_NEEDED 0 |
| |
| #define | PAL_VISIBILITY_INVAL_ARG -2 |
| |
| #define | PAL_VISIBILITY_ERROR -3 |
| |
| #define | overview_num_log overview.overview_bits.num_log |
| |
| #define | overview_tpc overview.overview_bits.tpc |
| |
| #define | overview_cpp overview.overview_bits.cpp |
| |
| #define | overview_ppid overview.overview_bits.ppid |
| |
| #define | log1_tid ppli1.ppli1_bits.tid |
| |
| #define | log1_cid ppli1.ppli1_bits.cid |
| |
| #define | log2_la ppli2.ppli2_bits.la |
| |
1.8.2