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54 #define CDSP_MAGIC 0xA7
56 #define VXP_CDSP_CLOCKIN_SEL_MASK 0x80
57 #define VXP_CDSP_DATAIN_SEL_MASK 0x40
58 #define VXP_CDSP_SMPTE_SEL_MASK 0x20
59 #define VXP_CDSP_RESERVED_MASK 0x10
60 #define VXP_CDSP_MIC_SEL_MASK 0x08
61 #define VXP_CDSP_VALID_IRQ_MASK 0x04
62 #define VXP_CDSP_CODEC_RESET_MASK 0x02
63 #define VXP_CDSP_DSP_RESET_MASK 0x01
65 #define P24_CDSP_MICS_SEL_MASK 0x18
66 #define P24_CDSP_MIC20_SEL_MASK 0x10
67 #define P24_CDSP_MIC38_SEL_MASK 0x08
70 #define P44_MEMIRQ_MASTER_SLAVE_SEL_MASK 0x08
71 #define P44_MEMIRQ_SYNCED_ALONE_SEL_MASK 0x04
72 #define P44_MEMIRQ_WCLK_OUT_IN_SEL_MASK 0x02
73 #define P44_MEMIRQ_WCLK_UER_SEL_MASK 0x01
78 #define VXP_DLG_XILINX_REPROG_MASK 0x80
79 #define VXP_DLG_DATA_XICOR_MASK 0x80
80 #define VXP_DLG_RESERVED4_0_MASK 0x40
81 #define VXP_DLG_RESERVED2_0_MASK 0x20
82 #define VXP_DLG_RESERVED1_0_MASK 0x10
83 #define VXP_DLG_DMAWRITE_SEL_MASK 0x08
84 #define VXP_DLG_DMAREAD_SEL_MASK 0x04
85 #define VXP_DLG_MEMIRQ_MASK 0x02
86 #define VXP_DLG_DMA16_SEL_MASK 0x02
87 #define VXP_DLG_ACK_MEMIRQ_MASK 0x01