|
| #define | VX_DRIVER_VERSION 0x010000 /* 1.0.0 */ |
| |
| #define | SIZE_MAX_CMD 0x10 |
| |
| #define | SIZE_MAX_STATUS 0x10 |
| |
| #define | VX_MAX_PIPES 16 |
| |
| #define | VX_MAX_PERIODS 32 |
| |
| #define | VX_MAX_CODECS 2 |
| |
| #define | SND_VX_HWDEP_ID "VX Loader" |
| |
| #define | VX_ANALOG_OUT_LEVEL_MAX 0xe3 |
| |
| #define | vx_inb(chip, reg) snd_vx_inb(chip, VX_##reg) |
| |
| #define | vx_outb(chip, reg, val) snd_vx_outb(chip, VX_##reg,val) |
| |
| #define | vx_inl(chip, reg) snd_vx_inl(chip, VX_##reg) |
| |
| #define | vx_outl(chip, reg, val) snd_vx_outl(chip, VX_##reg,val) |
| |
| #define | vx_check_isr(chip, mask, bit, time) snd_vx_check_reg_bit(chip, VX_ISR, mask, bit, time) |
| |
| #define | vx_wait_isr_bit(chip, bit) vx_check_isr(chip, bit, bit, 200) |
| |
| #define | vx_wait_for_rx_full(chip) vx_wait_isr_bit(chip, ISR_RX_FULL) |
| |
| #define | VX_ERR_MASK 0x1000000 |
| |
| #define | vx_get_error(err) (-(err) & ~VX_ERR_MASK) |
| |
| #define | vx_has_new_dsp(chip) ((chip)->type != VX_TYPE_BOARD) |
| |
| #define | vx_is_pcmcia(chip) ((chip)->type >= VX_TYPE_VXPOCKET) |
| |
| #define | ICR_HF1 0x10 |
| |
| #define | ICR_HF0 0x08 |
| |
| #define | ICR_TREQ 0x02 /* Interrupt mode + HREQ set on for transfer (->DSP) request */ |
| |
| #define | ICR_RREQ 0x01 /* Interrupt mode + RREQ set on for transfer (->PC) request */ |
| |
| #define | CVR_HC 0x80 |
| |
| #define | ISR_HF3 0x10 |
| |
| #define | ISR_HF2 0x08 |
| |
| #define | ISR_CHK 0x10 |
| |
| #define | ISR_ERR 0x08 |
| |
| #define | ISR_TX_READY 0x04 |
| |
| #define | ISR_TX_EMPTY 0x02 |
| |
| #define | ISR_RX_FULL 0x01 |
| |
| #define | VX_DATA_CODEC_MASK 0x80 |
| |
| #define | VX_DATA_XICOR_MASK 0x80 |
| |
| #define | VX_SUER_FREQ_MASK 0x0c |
| |
| #define | VX_SUER_FREQ_32KHz_MASK 0x0c |
| |
| #define | VX_SUER_FREQ_44KHz_MASK 0x00 |
| |
| #define | VX_SUER_FREQ_48KHz_MASK 0x04 |
| |
| #define | VX_SUER_DATA_PRESENT_MASK 0x02 |
| |
| #define | VX_SUER_CLOCK_PRESENT_MASK 0x01 |
| |
| #define | VX_CUER_HH_BITC_SEL_MASK 0x08 |
| |
| #define | VX_CUER_MH_BITC_SEL_MASK 0x04 |
| |
| #define | VX_CUER_ML_BITC_SEL_MASK 0x02 |
| |
| #define | VX_CUER_LL_BITC_SEL_MASK 0x01 |
| |
| #define | XX_UER_CBITS_OFFSET_MASK 0x1f |
| |
| #define | VX_AUDIO_INFO_REAL_TIME (1<<0) /* real-time processing available */ |
| |
| #define | VX_AUDIO_INFO_OFFLINE (1<<1) /* offline processing available */ |
| |
| #define | VX_AUDIO_INFO_MPEG1 (1<<5) |
| |
| #define | VX_AUDIO_INFO_MPEG2 (1<<6) |
| |
| #define | VX_AUDIO_INFO_LINEAR_8 (1<<7) |
| |
| #define | VX_AUDIO_INFO_LINEAR_16 (1<<8) |
| |
| #define | VX_AUDIO_INFO_LINEAR_24 (1<<9) |
| |
| #define | VXP_IRQ_OFFSET 0x40 /* add 0x40 offset for vxpocket and vx222/v2 */ |
| |
| #define | IRQ_MESS_WRITE_END 0x30 |
| |
| #define | IRQ_MESS_WRITE_NEXT 0x32 |
| |
| #define | IRQ_MESS_READ_NEXT 0x34 |
| |
| #define | IRQ_MESS_READ_END 0x36 |
| |
| #define | IRQ_MESSAGE 0x38 |
| |
| #define | IRQ_RESET_CHK 0x3A |
| |
| #define | IRQ_CONNECT_STREAM_NEXT 0x26 |
| |
| #define | IRQ_CONNECT_STREAM_END 0x28 |
| |
| #define | IRQ_PAUSE_START_CONNECT 0x2A |
| |
| #define | IRQ_END_CONNECTION 0x2C |
| |
| #define | ASYNC_EVENTS_PENDING 0x008000 |
| |
| #define | HBUFFER_EVENTS_PENDING 0x004000 |
| |
| #define | NOTIF_EVENTS_PENDING 0x002000 |
| |
| #define | TIME_CODE_EVENT_PENDING 0x001000 |
| |
| #define | FREQUENCY_CHANGE_EVENT_PENDING 0x000800 |
| |
| #define | END_OF_BUFFER_EVENTS_PENDING 0x000400 |
| |
| #define | FATAL_DSP_ERROR 0xff0000 |
| |
| #define | HEADER_FMT_BASE 0xFED00000 |
| |
| #define | HEADER_FMT_MONO 0x000000C0 |
| |
| #define | HEADER_FMT_INTEL 0x00008000 |
| |
| #define | HEADER_FMT_16BITS 0x00002000 |
| |
| #define | HEADER_FMT_24BITS 0x00004000 |
| |
| #define | HEADER_FMT_UPTO11 0x00000200 /* frequency is less or equ. to 11k.*/ |
| |
| #define | HEADER_FMT_UPTO32 0x00000100 /* frequency is over 11k and less then 32k.*/ |
| |
| #define | XX_CODEC_SELECTOR 0x20 |
| |
| #define | XX_CODEC_ADC_CONTROL_REGISTER 0x01 |
| |
| #define | XX_CODEC_DAC_CONTROL_REGISTER 0x02 |
| |
| #define | XX_CODEC_LEVEL_LEFT_REGISTER 0x03 |
| |
| #define | XX_CODEC_LEVEL_RIGHT_REGISTER 0x04 |
| |
| #define | XX_CODEC_PORT_MODE_REGISTER 0x05 |
| |
| #define | XX_CODEC_STATUS_REPORT_REGISTER 0x06 |
| |
| #define | XX_CODEC_CLOCK_CONTROL_REGISTER 0x07 |
| |
| #define | CVAL_M110DB 0x000 /* -110dB */ |
| |
| #define | CVAL_M99DB 0x02C |
| |
| #define | CVAL_M21DB 0x163 |
| |
| #define | CVAL_M18DB 0x16F |
| |
| #define | CVAL_M10DB 0x18F |
| |
| #define | CVAL_0DB 0x1B7 |
| |
| #define | CVAL_18DB 0x1FF /* +18dB */ |
| |
| #define | CVAL_MAX 0x1FF |
| |
| #define | AUDIO_IO_HAS_MUTE_LEVEL 0x400000 |
| |
| #define | AUDIO_IO_HAS_MUTE_MONITORING_1 0x200000 |
| |
| #define | AUDIO_IO_HAS_MUTE_MONITORING_2 0x100000 |
| |
| #define | VALID_AUDIO_IO_DIGITAL_LEVEL 0x01 |
| |
| #define | VALID_AUDIO_IO_MONITORING_LEVEL 0x02 |
| |
| #define | VALID_AUDIO_IO_MUTE_LEVEL 0x04 |
| |
| #define | VALID_AUDIO_IO_MUTE_MONITORING_1 0x08 |
| |
| #define | VALID_AUDIO_IO_MUTE_MONITORING_2 0x10 |
| |
|
| enum | {
VX_TYPE_BOARD,
VX_TYPE_V2,
VX_TYPE_MIC,
VX_TYPE_VXPOCKET,
VX_TYPE_VXP440,
VX_TYPE_NUMS
} |
| |
| enum | {
VX_STAT_XILINX_LOADED = (1 << 0),
VX_STAT_DEVICE_INIT = (1 << 1),
VX_STAT_CHIP_INIT = (1 << 2),
VX_STAT_IN_SUSPEND = (1 << 10),
VX_STAT_IS_STALE = (1 << 15)
} |
| |
| enum | { VX_AUDIO_SRC_DIGITAL,
VX_AUDIO_SRC_LINE,
VX_AUDIO_SRC_MIC
} |
| |
| enum | { INTERNAL_QUARTZ,
UER_SYNC
} |
| |
| enum | { VX_CLOCK_MODE_AUTO,
VX_CLOCK_MODE_INTERNAL,
VX_CLOCK_MODE_EXTERNAL
} |
| |
| enum | { VX_UER_MODE_CONSUMER,
VX_UER_MODE_PROFESSIONAL,
VX_UER_MODE_NOT_PRESENT
} |
| |
| enum | {
VX_ICR,
VX_CVR,
VX_ISR,
VX_IVR,
VX_RXH,
VX_TXH = VX_RXH,
VX_RXM,
VX_TXM = VX_RXM,
VX_RXL,
VX_TXL = VX_RXL,
VX_DMA,
VX_CDSP,
VX_RFREQ,
VX_RUER_V2,
VX_GAIN,
VX_DATA = VX_GAIN,
VX_MEMIRQ,
VX_ACQ,
VX_BIT0,
VX_BIT1,
VX_MIC0,
VX_MIC1,
VX_MIC2,
VX_MIC3,
VX_PLX0,
VX_PLX1,
VX_PLX2,
VX_LOFREQ,
VX_HIFREQ,
VX_CSUER,
VX_RUER,
VX_REG_MAX,
VX_RESET_DMA = VX_ISR,
VX_CFG = VX_RFREQ,
VX_STATUS = VX_MEMIRQ,
VX_SELMIC = VX_MIC0,
VX_COMPOT = VX_MIC1,
VX_SCOMPR = VX_MIC2,
VX_GLIMIT = VX_MIC3,
VX_INTCSR = VX_PLX0,
VX_CNTRL = VX_PLX1,
VX_GPIOC = VX_PLX2,
VX_MICRO = VX_MEMIRQ,
VX_CODEC2 = VX_MEMIRQ,
VX_DIALOG = VX_ACQ
} |
| |
| enum | { RMH_SSIZE_FIXED = 0,
RMH_SSIZE_ARG = 1,
RMH_SSIZE_MASK = 2
} |
| |
1.8.2