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| #define | DRV_NAME "w5300" |
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| #define | DRV_VERSION "2012-04-04" |
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| #define | W5300_MR 0x0000 /* Mode Register */ |
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| #define | MR_DBW (1 << 15) /* Data bus width */ |
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| #define | MR_MPF (1 << 14) /* Mac layer pause frame */ |
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| #define | MR_WDF(n) (((n)&7)<<11) /* Write data fetch time */ |
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| #define | MR_RDH (1 << 10) /* Read data hold time */ |
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| #define | MR_FS (1 << 8) /* FIFO swap */ |
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| #define | MR_RST (1 << 7) /* S/W reset */ |
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| #define | MR_PB (1 << 4) /* Ping block */ |
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| #define | MR_DBS (1 << 2) /* Data bus swap */ |
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| #define | MR_IND (1 << 0) /* Indirect mode */ |
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| #define | W5300_IR 0x0002 /* Interrupt Register */ |
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| #define | W5300_IMR 0x0004 /* Interrupt Mask Register */ |
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| #define | IR_S0 0x0001 /* S0 interrupt */ |
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| #define | W5300_SHARL 0x0008 /* Source MAC address (0123) */ |
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| #define | W5300_SHARH 0x000c /* Source MAC address (45) */ |
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| #define | W5300_TMSRL 0x0020 /* Transmit Memory Size (0123) */ |
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| #define | W5300_TMSRH 0x0024 /* Transmit Memory Size (4567) */ |
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| #define | W5300_RMSRL 0x0028 /* Receive Memory Size (0123) */ |
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| #define | W5300_RMSRH 0x002c /* Receive Memory Size (4567) */ |
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| #define | W5300_MTYPE 0x0030 /* Memory Type */ |
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| #define | W5300_IDR 0x00fe /* Chip ID register */ |
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| #define | IDR_W5300 0x5300 /* =0x5300 for WIZnet W5300 */ |
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| #define | W5300_S0_MR 0x0200 /* S0 Mode Register */ |
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| #define | S0_MR_CLOSED 0x0000 /* Close mode */ |
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| #define | S0_MR_MACRAW 0x0004 /* MAC RAW mode (promiscous) */ |
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| #define | S0_MR_MACRAW_MF 0x0044 /* MAC RAW mode (filtered) */ |
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| #define | W5300_S0_CR 0x0202 /* S0 Command Register */ |
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| #define | S0_CR_OPEN 0x0001 /* OPEN command */ |
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| #define | S0_CR_CLOSE 0x0010 /* CLOSE command */ |
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| #define | S0_CR_SEND 0x0020 /* SEND command */ |
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| #define | S0_CR_RECV 0x0040 /* RECV command */ |
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| #define | W5300_S0_IMR 0x0204 /* S0 Interrupt Mask Register */ |
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| #define | W5300_S0_IR 0x0206 /* S0 Interrupt Register */ |
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| #define | S0_IR_RECV 0x0004 /* Receive interrupt */ |
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| #define | S0_IR_SENDOK 0x0010 /* Send OK interrupt */ |
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| #define | W5300_S0_SSR 0x0208 /* S0 Socket Status Register */ |
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| #define | W5300_S0_TX_WRSR 0x0220 /* S0 TX Write Size Register */ |
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| #define | W5300_S0_TX_FSR 0x0224 /* S0 TX Free Size Register */ |
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| #define | W5300_S0_RX_RSR 0x0228 /* S0 Received data Size */ |
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| #define | W5300_S0_TX_FIFO 0x022e /* S0 Transmit FIFO */ |
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| #define | W5300_S0_RX_FIFO 0x0230 /* S0 Receive FIFO */ |
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| #define | W5300_REGS_LEN 0x0400 |
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| #define | W5300_IDM_AR 0x0002 /* Indirect Mode Address */ |
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| #define | W5300_IDM_DR 0x0004 /* Indirect Mode Data */ |
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| #define | w5300_read priv->read |
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| #define | w5300_write priv->write |
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1.8.2