#include <asm/io.h>
#include <linux/types.h>

Data Structures
struct	st_fifo_entry

struct	st_fifo

struct	w83977af_ir

Macros
#define	ENBNKSEL 0x01

#define	APEDCRC 0x02

#define	TXW4C 0x04

#define	RXW4C 0x08

#define	RBR 0x00 /* Receiver buffer register */

#define	TBR 0x00 /* Transmitter buffer register */

#define	ICR 0x01 /* Interrupt configuration register */

#define	ICR_ERBRI 0x01 /* Receiver buffer register interrupt */

#define	ICR_ETBREI 0x02 /* Transeiver empty interrupt */

#define	ICR_EUSRI 0x04

#define	ICR_EHSRI 0x04

#define	ICR_ETXURI 0x04 /* Tx underrun */

#define	ICR_EDMAI 0x10 /* DMA interrupt */

#define	ICR_ETXTHI 0x20 /* Transmitter threshold interrupt */

#define	ICR_EFSFI 0x40 /* Frame status FIFO interrupt */

#define	ICR_ETMRI 0x80 /* Timer interrupt */

#define	UFR 0x02 /* FIFO control register */

#define	UFR_EN_FIFO 0x01 /* Enable FIFO's */

#define	UFR_RXF_RST 0x02 /* Reset Rx FIFO */

#define	UFR_TXF_RST 0x04 /* Reset Tx FIFO */

#define	UFR_RXTL 0x80 /* Rx FIFO threshold (set to 16) */

#define	UFR_TXTL 0x20 /* Tx FIFO threshold (set to 17) */

#define	ISR 0x02 /* Interrupt status register */

#define	ISR_RXTH_I 0x01 /* Receive threshold interrupt */

#define	ISR_TXEMP_I 0x02 /* Transmitter empty interrupt */

#define	ISR_FEND_I 0x04

#define	ISR_DMA_I 0x10

#define	ISR_TXTH_I 0x20 /* Transmitter threshold interrupt */

#define	ISR_FSF_I 0x40

#define	ISR_TMR_I 0x80 /* Timer interrupt */

#define	UCR 0x03 /* Uart control register */

#define	UCR_DLS8 0x03 /* 8N1 */

#define	SSR 0x03 /* Sets select register */

#define	SET0 UCR_DLS8 /* Make sure we keep 8N1 */

#define	SET1 (0x80\|UCR_DLS8) /* Make sure we keep 8N1 */

#define	SET2 0xE0

#define	SET3 0xE4

#define	SET4 0xE8

#define	SET5 0xEC

#define	SET6 0xF0

#define	SET7 0xF4

#define	HCR 0x04

#define	HCR_MODE_MASK ~(0xD0)

#define	HCR_SIR 0x60

#define	HCR_MIR_576 0x20

#define	HCR_MIR_1152 0x80

#define	HCR_FIR 0xA0

#define	HCR_EN_DMA 0x04

#define	HCR_EN_IRQ 0x08

#define	HCR_TX_WT 0x08

#define	USR 0x05 /* IR status register */

#define	USR_RDR 0x01 /* Receive data ready */

#define	USR_TSRE 0x40 /* Transmitter empty? */

#define	AUDR 0x07

#define	AUDR_SFEND 0x08 /* Set a frame end */

#define	AUDR_RXBSY 0x20 /* Rx busy */

#define	AUDR_UNDR 0x40 /* Transeiver underrun */

#define	ABLL 0x00 /* Advanced baud rate divisor latch (low byte) */

#define	ABHL 0x01 /* Advanced baud rate divisor latch (high byte) */

#define	ADCR1 0x02

#define	ADCR1_ADV_SL 0x01

#define	ADCR1_D_CHSW 0x08 /* the specs are wrong. its bit 3, not 4 */

#define	ADCR1_DMA_F 0x02

#define	ADCR2 0x04

#define	ADCR2_TXFS32 0x01

#define	ADCR2_RXFS32 0x04

#define	RXFDTH 0x07

#define	AUID 0x00

#define	TMRL 0x00 /* Timer value register (low byte) */

#define	TMRH 0x01 /* Timer value register (high byte) */

#define	IR_MSL 0x02 /* Infrared mode select */

#define	IR_MSL_EN_TMR 0x01 /* Enable timer */

#define	TFRLL 0x04 /* Transmitter frame length (low byte) */

#define	TFRLH 0x05 /* Transmitter frame length (high byte) */

#define	RFRLL 0x06 /* Receiver frame length (low byte) */

#define	RFRLH 0x07 /* Receiver frame length (high byte) */

#define	FS_FO 0x05 /* Frame status FIFO */

#define	FS_FO_FSFDR 0x80 /* Frame status FIFO data ready */

#define	FS_FO_LST_FR 0x40 /* Frame lost */

#define	FS_FO_MX_LEX 0x10 /* Max frame len exceeded */

#define	FS_FO_PHY_ERR 0x08 /* Physical layer error */

#define	FS_FO_CRC_ERR 0x04

#define	FS_FO_RX_OV 0x02 /* Receive overrun */

#define	FS_FO_FSF_OV 0x01 /* Frame status FIFO overrun */

#define	FS_FO_ERR_MSK 0x5f /* Error mask */

#define	RFLFL 0x06

#define	RFLFH 0x07

#define	IR_CFG2 0x00

#define	IR_CFG2_DIS_CRC 0x02

#define	IRM_CR 0x07 /* Infrared module control register */

#define	IRM_CR_IRX_MSL 0x40

#define	IRM_CR_AF_MNT 0x80 /* Automatic format */

Macro Definition Documentation

#define ABHL 0x01 /* Advanced baud rate divisor latch (high byte) */

Definition at line 102 of file w83977af_ir.h.

#define ABLL 0x00 /* Advanced baud rate divisor latch (low byte) */

Definition at line 101 of file w83977af_ir.h.

#define ADCR1 0x02

Definition at line 104 of file w83977af_ir.h.

#define ADCR1_ADV_SL 0x01

Definition at line 105 of file w83977af_ir.h.

#define ADCR1_D_CHSW 0x08 /* the specs are wrong. its bit 3, not 4 */

Definition at line 106 of file w83977af_ir.h.

#define ADCR1_DMA_F 0x02

Definition at line 107 of file w83977af_ir.h.

#define ADCR2 0x04

Definition at line 109 of file w83977af_ir.h.

#define ADCR2_RXFS32 0x04

Definition at line 111 of file w83977af_ir.h.

#define ADCR2_TXFS32 0x01

Definition at line 110 of file w83977af_ir.h.

#define APEDCRC 0x02

Definition at line 33 of file w83977af_ir.h.

#define AUDR 0x07

Definition at line 95 of file w83977af_ir.h.

#define AUDR_RXBSY 0x20 /* Rx busy */

Definition at line 97 of file w83977af_ir.h.

#define AUDR_SFEND 0x08 /* Set a frame end */

Definition at line 96 of file w83977af_ir.h.

#define AUDR_UNDR 0x40 /* Transeiver underrun */

Definition at line 98 of file w83977af_ir.h.

#define AUID 0x00

Definition at line 116 of file w83977af_ir.h.

#define ENBNKSEL 0x01

Definition at line 32 of file w83977af_ir.h.

#define FS_FO 0x05 /* Frame status FIFO */

Definition at line 132 of file w83977af_ir.h.

#define FS_FO_CRC_ERR 0x04

Definition at line 137 of file w83977af_ir.h.

#define FS_FO_ERR_MSK 0x5f /* Error mask */

Definition at line 140 of file w83977af_ir.h.

#define FS_FO_FSF_OV 0x01 /* Frame status FIFO overrun */

Definition at line 139 of file w83977af_ir.h.

#define FS_FO_FSFDR 0x80 /* Frame status FIFO data ready */

Definition at line 133 of file w83977af_ir.h.

#define FS_FO_LST_FR 0x40 /* Frame lost */

Definition at line 134 of file w83977af_ir.h.

#define FS_FO_MX_LEX 0x10 /* Max frame len exceeded */

Definition at line 135 of file w83977af_ir.h.

#define FS_FO_PHY_ERR 0x08 /* Physical layer error */

Definition at line 136 of file w83977af_ir.h.

#define FS_FO_RX_OV 0x02 /* Receive overrun */

Definition at line 138 of file w83977af_ir.h.

#define HCR 0x04

Definition at line 81 of file w83977af_ir.h.

#define HCR_EN_DMA 0x04

Definition at line 87 of file w83977af_ir.h.

#define HCR_EN_IRQ 0x08

Definition at line 88 of file w83977af_ir.h.

#define HCR_FIR 0xA0

Definition at line 86 of file w83977af_ir.h.

#define HCR_MIR_1152 0x80

Definition at line 85 of file w83977af_ir.h.

#define HCR_MIR_576 0x20

Definition at line 84 of file w83977af_ir.h.

#define HCR_MODE_MASK ~(0xD0)

Definition at line 82 of file w83977af_ir.h.

#define HCR_SIR 0x60

Definition at line 83 of file w83977af_ir.h.

#define HCR_TX_WT 0x08

Definition at line 89 of file w83977af_ir.h.

#define ICR 0x01 /* Interrupt configuration register */

Definition at line 41 of file w83977af_ir.h.

#define ICR_EDMAI 0x10 /* DMA interrupt */

Definition at line 47 of file w83977af_ir.h.

#define ICR_EFSFI 0x40 /* Frame status FIFO interrupt */

Definition at line 49 of file w83977af_ir.h.

#define ICR_EHSRI 0x04

Definition at line 45 of file w83977af_ir.h.

#define ICR_ERBRI 0x01 /* Receiver buffer register interrupt */

Definition at line 42 of file w83977af_ir.h.

#define ICR_ETBREI 0x02 /* Transeiver empty interrupt */

Definition at line 43 of file w83977af_ir.h.

#define ICR_ETMRI 0x80 /* Timer interrupt */

Definition at line 50 of file w83977af_ir.h.

#define ICR_ETXTHI 0x20 /* Transmitter threshold interrupt */

Definition at line 48 of file w83977af_ir.h.

#define ICR_ETXURI 0x04 /* Tx underrun */

Definition at line 46 of file w83977af_ir.h.

#define ICR_EUSRI 0x04

Definition at line 44 of file w83977af_ir.h.

#define IR_CFG2 0x00

Definition at line 146 of file w83977af_ir.h.

#define IR_CFG2_DIS_CRC 0x02

Definition at line 147 of file w83977af_ir.h.

#define IR_MSL 0x02 /* Infrared mode select */

Definition at line 122 of file w83977af_ir.h.

#define IR_MSL_EN_TMR 0x01 /* Enable timer */

Definition at line 123 of file w83977af_ir.h.

#define IRM_CR 0x07 /* Infrared module control register */

Definition at line 150 of file w83977af_ir.h.

#define IRM_CR_AF_MNT 0x80 /* Automatic format */

Definition at line 152 of file w83977af_ir.h.

#define IRM_CR_IRX_MSL 0x40

Definition at line 151 of file w83977af_ir.h.

#define ISR 0x02 /* Interrupt status register */

Definition at line 59 of file w83977af_ir.h.

#define ISR_DMA_I 0x10

Definition at line 63 of file w83977af_ir.h.

#define ISR_FEND_I 0x04

Definition at line 62 of file w83977af_ir.h.

#define ISR_FSF_I 0x40

Definition at line 65 of file w83977af_ir.h.

#define ISR_RXTH_I 0x01 /* Receive threshold interrupt */

Definition at line 60 of file w83977af_ir.h.

#define ISR_TMR_I 0x80 /* Timer interrupt */

Definition at line 66 of file w83977af_ir.h.

#define ISR_TXEMP_I 0x02 /* Transmitter empty interrupt */

Definition at line 61 of file w83977af_ir.h.

#define ISR_TXTH_I 0x20 /* Transmitter threshold interrupt */

Definition at line 64 of file w83977af_ir.h.

#define RBR 0x00 /* Receiver buffer register */

Definition at line 38 of file w83977af_ir.h.

#define RFLFH 0x07

Definition at line 143 of file w83977af_ir.h.

#define RFLFL 0x06

Definition at line 142 of file w83977af_ir.h.

#define RFRLH 0x07 /* Receiver frame length (high byte) */

Definition at line 128 of file w83977af_ir.h.

#define RFRLL 0x06 /* Receiver frame length (low byte) */

Definition at line 127 of file w83977af_ir.h.

#define RXFDTH 0x07

Definition at line 113 of file w83977af_ir.h.

#define RXW4C 0x08

Definition at line 35 of file w83977af_ir.h.

#define SET0 UCR_DLS8 /* Make sure we keep 8N1 */

Definition at line 72 of file w83977af_ir.h.

#define SET1 (0x80|UCR_DLS8) /* Make sure we keep 8N1 */

Definition at line 73 of file w83977af_ir.h.

#define SET2 0xE0

Definition at line 74 of file w83977af_ir.h.

#define SET3 0xE4

Definition at line 75 of file w83977af_ir.h.

#define SET4 0xE8

Definition at line 76 of file w83977af_ir.h.

#define SET5 0xEC

Definition at line 77 of file w83977af_ir.h.

#define SET6 0xF0

Definition at line 78 of file w83977af_ir.h.

#define SET7 0xF4

Definition at line 79 of file w83977af_ir.h.

#define SSR 0x03 /* Sets select register */

Definition at line 71 of file w83977af_ir.h.

#define TBR 0x00 /* Transmitter buffer register */

Definition at line 39 of file w83977af_ir.h.

#define TFRLH 0x05 /* Transmitter frame length (high byte) */

Definition at line 126 of file w83977af_ir.h.

#define TFRLL 0x04 /* Transmitter frame length (low byte) */

Definition at line 125 of file w83977af_ir.h.

#define TMRH 0x01 /* Timer value register (high byte) */

Definition at line 120 of file w83977af_ir.h.

#define TMRL 0x00 /* Timer value register (low byte) */

Definition at line 119 of file w83977af_ir.h.

#define TXW4C 0x04

Definition at line 34 of file w83977af_ir.h.

#define UCR 0x03 /* Uart control register */

Definition at line 68 of file w83977af_ir.h.

#define UCR_DLS8 0x03 /* 8N1 */

Definition at line 69 of file w83977af_ir.h.

#define UFR 0x02 /* FIFO control register */

Definition at line 52 of file w83977af_ir.h.

#define UFR_EN_FIFO 0x01 /* Enable FIFO's */

Definition at line 53 of file w83977af_ir.h.

#define UFR_RXF_RST 0x02 /* Reset Rx FIFO */

Definition at line 54 of file w83977af_ir.h.

#define UFR_RXTL 0x80 /* Rx FIFO threshold (set to 16) */

Definition at line 56 of file w83977af_ir.h.

#define UFR_TXF_RST 0x04 /* Reset Tx FIFO */

Definition at line 55 of file w83977af_ir.h.

#define UFR_TXTL 0x20 /* Tx FIFO threshold (set to 17) */

Definition at line 57 of file w83977af_ir.h.

#define USR 0x05 /* IR status register */

Definition at line 91 of file w83977af_ir.h.

#define USR_RDR 0x01 /* Receive data ready */

Definition at line 92 of file w83977af_ir.h.

#define USR_TSRE 0x40 /* Transmitter empty? */

Definition at line 93 of file w83977af_ir.h.

Data Structures

Macros

Macro Definition Documentation