Macros
#define	PERFMON_CMD_DISABLE 0

#define	PERFMON_CMD_ENABLE 1

#define	PERFMON_CMD_DESIRED_EVENTS 2

#define	PERFMON_CMD_LOGGING_OPTIONS 3

#define	PERFMON_CMD_INT_FREQ 4

#define	PERFMON_CMD_ENABLE_CLEAR 7

#define	PERFMON_CMD_READ 5

#define	PERFMON_CMD_WRITE 6

#define	PERFMON_CMD_ENABLE_WRITE 7

#define	PERFMON_CMD_I_STAT 8

#define	PERFMON_CMD_PMPC 9

#define	EV5_PCTR_0 (1UL<<0)

#define	EV5_PCTR_1 (1UL<<1)

#define	EV5_PCTR_2 (1UL<<2)

#define	EV5_PCTR_0_COUNT_SHIFT 48

#define	EV5_PCTR_1_COUNT_SHIFT 32

#define	EV5_PCTR_2_COUNT_SHIFT 16

#define	EV5_PCTR_0_COUNT_MASK 0xffffUL

#define	EV5_PCTR_1_COUNT_MASK 0xffffUL

#define	EV5_PCTR_2_COUNT_MASK 0x3fffUL

#define	EV6_PCTR_0 (1UL<<0)

#define	EV6_PCTR_1 (1UL<<1)

#define	EV6_PCTR_0_COUNT_SHIFT 28

#define	EV6_PCTR_1_COUNT_SHIFT 6

#define	EV6_PCTR_0_COUNT_MASK 0xfffffUL

#define	EV6_PCTR_1_COUNT_MASK 0xfffffUL

#define	EV67_PCTR_0 (1UL<<0)

#define	EV67_PCTR_1 (1UL<<1)

#define	EV67_PCTR_0_COUNT_SHIFT 28

#define	EV67_PCTR_1_COUNT_SHIFT 6

#define	EV67_PCTR_0_COUNT_MASK 0xfffffUL

#define	EV67_PCTR_1_COUNT_MASK 0xfffffUL

#define	EV6_PCTR_0_EVENT_MASK 0x10UL

#define	EV6_PCTR_1_EVENT_MASK 0x0fUL

#define	EV6_PCTR_0_CYCLES (0UL << 4)

#define	EV6_PCTR_0_INSTRUCTIONS (1UL << 4)

#define	EV6_PCTR_1_CYCLES 0

#define	EV6_PCTR_1_BRANCHES 1

#define	EV6_PCTR_1_BRANCH_MISPREDICTS 2

#define	EV6_PCTR_1_DTB_SINGLE_MISSES 3

#define	EV6_PCTR_1_DTB_DOUBLE_MISSES 4

#define	EV6_PCTR_1_ITB_MISSES 5

#define	EV6_PCTR_1_UNALIGNED_TRAPS 6

#define	EV6_PCTR_1_REPLY_TRAPS 7

#define	EV67_PCTR_MODE_MASK 0x10UL

#define	EV67_PCTR_EVENT_MASK 0x0CUL

#define	EV67_PCTR_MODE_PROFILEME (1UL<<4)

#define	EV67_PCTR_MODE_AGGREGATE (0UL<<4)

#define	EV67_PCTR_INSTR_CYCLES (0UL<<2)

#define	EV67_PCTR_CYCLES_UNDEF (1UL<<2)

#define	EV67_PCTR_INSTR_BCACHEMISS (2UL<<2)

#define	EV67_PCTR_CYCLES_MBOX (3UL<<2)

Macro Definition Documentation

#define EV5_PCTR_0 (1UL<<0)

Definition at line 27 of file wrperfmon.h.

#define EV5_PCTR_0_COUNT_MASK 0xffffUL

Definition at line 35 of file wrperfmon.h.

#define EV5_PCTR_0_COUNT_SHIFT 48

Definition at line 31 of file wrperfmon.h.

#define EV5_PCTR_1 (1UL<<1)

Definition at line 28 of file wrperfmon.h.

#define EV5_PCTR_1_COUNT_MASK 0xffffUL

Definition at line 36 of file wrperfmon.h.

#define EV5_PCTR_1_COUNT_SHIFT 32

Definition at line 32 of file wrperfmon.h.

#define EV5_PCTR_2 (1UL<<2)

Definition at line 29 of file wrperfmon.h.

#define EV5_PCTR_2_COUNT_MASK 0x3fffUL

Definition at line 37 of file wrperfmon.h.

#define EV5_PCTR_2_COUNT_SHIFT 16

Definition at line 33 of file wrperfmon.h.

#define EV67_PCTR_0 (1UL<<0)

Definition at line 50 of file wrperfmon.h.

#define EV67_PCTR_0_COUNT_MASK 0xfffffUL

Definition at line 56 of file wrperfmon.h.

#define EV67_PCTR_0_COUNT_SHIFT 28

Definition at line 53 of file wrperfmon.h.

#define EV67_PCTR_1 (1UL<<1)

Definition at line 51 of file wrperfmon.h.

#define EV67_PCTR_1_COUNT_MASK 0xfffffUL

Definition at line 57 of file wrperfmon.h.

#define EV67_PCTR_1_COUNT_SHIFT 6

Definition at line 54 of file wrperfmon.h.

#define EV67_PCTR_CYCLES_MBOX (3UL<<2)

Definition at line 91 of file wrperfmon.h.

#define EV67_PCTR_CYCLES_UNDEF (1UL<<2)

Definition at line 89 of file wrperfmon.h.

#define EV67_PCTR_EVENT_MASK 0x0CUL

Definition at line 83 of file wrperfmon.h.

#define EV67_PCTR_INSTR_BCACHEMISS (2UL<<2)

Definition at line 90 of file wrperfmon.h.

#define EV67_PCTR_INSTR_CYCLES (0UL<<2)

Definition at line 88 of file wrperfmon.h.

#define EV67_PCTR_MODE_AGGREGATE (0UL<<4)

Definition at line 86 of file wrperfmon.h.

#define EV67_PCTR_MODE_MASK 0x10UL

Definition at line 82 of file wrperfmon.h.

#define EV67_PCTR_MODE_PROFILEME (1UL<<4)

Definition at line 85 of file wrperfmon.h.

#define EV6_PCTR_0 (1UL<<0)

Definition at line 40 of file wrperfmon.h.

#define EV6_PCTR_0_COUNT_MASK 0xfffffUL

Definition at line 46 of file wrperfmon.h.

#define EV6_PCTR_0_COUNT_SHIFT 28

Definition at line 43 of file wrperfmon.h.

#define EV6_PCTR_0_CYCLES (0UL << 4)

Definition at line 69 of file wrperfmon.h.

#define EV6_PCTR_0_EVENT_MASK 0x10UL

Definition at line 65 of file wrperfmon.h.

#define EV6_PCTR_0_INSTRUCTIONS (1UL << 4)

Definition at line 70 of file wrperfmon.h.

#define EV6_PCTR_1 (1UL<<1)

Definition at line 41 of file wrperfmon.h.

#define EV6_PCTR_1_BRANCH_MISPREDICTS 2

Definition at line 74 of file wrperfmon.h.

#define EV6_PCTR_1_BRANCHES 1

Definition at line 73 of file wrperfmon.h.

#define EV6_PCTR_1_COUNT_MASK 0xfffffUL

Definition at line 47 of file wrperfmon.h.

#define EV6_PCTR_1_COUNT_SHIFT 6

Definition at line 44 of file wrperfmon.h.

#define EV6_PCTR_1_CYCLES 0

Definition at line 72 of file wrperfmon.h.

#define EV6_PCTR_1_DTB_DOUBLE_MISSES 4

Definition at line 76 of file wrperfmon.h.

#define EV6_PCTR_1_DTB_SINGLE_MISSES 3

Definition at line 75 of file wrperfmon.h.

#define EV6_PCTR_1_EVENT_MASK 0x0fUL

Definition at line 66 of file wrperfmon.h.

#define EV6_PCTR_1_ITB_MISSES 5

Definition at line 77 of file wrperfmon.h.

#define EV6_PCTR_1_REPLY_TRAPS 7

Definition at line 79 of file wrperfmon.h.

#define EV6_PCTR_1_UNALIGNED_TRAPS 6

Definition at line 78 of file wrperfmon.h.

#define PERFMON_CMD_DESIRED_EVENTS 2

Definition at line 11 of file wrperfmon.h.

#define PERFMON_CMD_DISABLE 0

Definition at line 9 of file wrperfmon.h.

#define PERFMON_CMD_ENABLE 1

Definition at line 10 of file wrperfmon.h.

#define PERFMON_CMD_ENABLE_CLEAR 7

Definition at line 15 of file wrperfmon.h.

#define PERFMON_CMD_ENABLE_WRITE 7

Definition at line 20 of file wrperfmon.h.

#define PERFMON_CMD_I_STAT 8

Definition at line 22 of file wrperfmon.h.

#define PERFMON_CMD_INT_FREQ 4

Definition at line 14 of file wrperfmon.h.

#define PERFMON_CMD_LOGGING_OPTIONS 3

Definition at line 12 of file wrperfmon.h.

#define PERFMON_CMD_PMPC 9

Definition at line 23 of file wrperfmon.h.

#define PERFMON_CMD_READ 5

Definition at line 17 of file wrperfmon.h.

#define PERFMON_CMD_WRITE 6

Definition at line 18 of file wrperfmon.h.

Macros

Macro Definition Documentation