#include <linux/platform_device.h>
#include <linux/serial.h>
#include <linux/serial_core.h>
#include <linux/tty.h>
#include <linux/tty_flip.h>
#include <linux/console.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/module.h>

Macros
#define	XUARTPS_TTY_NAME "ttyPS"

#define	XUARTPS_NAME "xuartps"

#define	XUARTPS_MAJOR 0 /* use dynamic node allocation */

#define	XUARTPS_MINOR 0 /* works best with devtmpfs */

#define	XUARTPS_NR_PORTS 2

#define	XUARTPS_FIFO_SIZE 16 /* FIFO size */

#define	XUARTPS_REGISTER_SPACE 0xFFF

#define	xuartps_readl(offset) ioread32(port->membase + offset)

#define	xuartps_writel(val, offset) iowrite32(val, port->membase + offset)

#define	XUARTPS_CR_OFFSET 0x00 /* Control Register [8:0] */

#define	XUARTPS_MR_OFFSET 0x04 /* Mode Register [10:0] */

#define	XUARTPS_IER_OFFSET 0x08 /* Interrupt Enable [10:0] */

#define	XUARTPS_IDR_OFFSET 0x0C /* Interrupt Disable [10:0] */

#define	XUARTPS_IMR_OFFSET 0x10 /* Interrupt Mask [10:0] */

#define	XUARTPS_ISR_OFFSET 0x14 /* Interrupt Status [10:0]*/

#define	XUARTPS_BAUDGEN_OFFSET 0x18 /* Baud Rate Generator [15:0] */

#define	XUARTPS_RXTOUT_OFFSET 0x1C /* RX Timeout [7:0] */

#define	XUARTPS_RXWM_OFFSET 0x20 /* RX FIFO Trigger Level [5:0] */

#define	XUARTPS_MODEMCR_OFFSET 0x24 /* Modem Control [5:0] */

#define	XUARTPS_MODEMSR_OFFSET 0x28 /* Modem Status [8:0] */

#define	XUARTPS_SR_OFFSET 0x2C /* Channel Status [11:0] */

#define	XUARTPS_FIFO_OFFSET 0x30 /* FIFO [15:0] or [7:0] */

#define	XUARTPS_BAUDDIV_OFFSET 0x34 /* Baud Rate Divider [7:0] */

#define	XUARTPS_FLOWDEL_OFFSET 0x38 /* Flow Delay [15:0] */

#define	XUARTPS_IRRX_PWIDTH_OFFSET

#define	XUARTPS_IRTX_PWIDTH_OFFSET

#define	XUARTPS_TXWM_OFFSET 0x44 /* TX FIFO Trigger Level [5:0] */

#define	XUARTPS_CR_STOPBRK 0x00000100 /* Stop TX break */

#define	XUARTPS_CR_STARTBRK 0x00000080 /* Set TX break */

#define	XUARTPS_CR_TX_DIS 0x00000020 /* TX disabled. */

#define	XUARTPS_CR_TX_EN 0x00000010 /* TX enabled */

#define	XUARTPS_CR_RX_DIS 0x00000008 /* RX disabled. */

#define	XUARTPS_CR_RX_EN 0x00000004 /* RX enabled */

#define	XUARTPS_CR_TXRST 0x00000002 /* TX logic reset */

#define	XUARTPS_CR_RXRST 0x00000001 /* RX logic reset */

#define	XUARTPS_CR_RST_TO 0x00000040 /* Restart Timeout Counter */

#define	XUARTPS_MR_CLKSEL 0x00000001 /* Pre-scalar selection */

#define	XUARTPS_MR_CHMODE_L_LOOP 0x00000200 /* Local loop back mode */

#define	XUARTPS_MR_CHMODE_NORM 0x00000000 /* Normal mode */

#define	XUARTPS_MR_STOPMODE_2_BIT 0x00000080 /* 2 stop bits */

#define	XUARTPS_MR_STOPMODE_1_BIT 0x00000000 /* 1 stop bit */

#define	XUARTPS_MR_PARITY_NONE 0x00000020 /* No parity mode */

#define	XUARTPS_MR_PARITY_MARK 0x00000018 /* Mark parity mode */

#define	XUARTPS_MR_PARITY_SPACE 0x00000010 /* Space parity mode */

#define	XUARTPS_MR_PARITY_ODD 0x00000008 /* Odd parity mode */

#define	XUARTPS_MR_PARITY_EVEN 0x00000000 /* Even parity mode */

#define	XUARTPS_MR_CHARLEN_6_BIT 0x00000006 /* 6 bits data */

#define	XUARTPS_MR_CHARLEN_7_BIT 0x00000004 /* 7 bits data */

#define	XUARTPS_MR_CHARLEN_8_BIT 0x00000000 /* 8 bits data */

#define	XUARTPS_IXR_TOUT 0x00000100 /* RX Timeout error interrupt */

#define	XUARTPS_IXR_PARITY 0x00000080 /* Parity error interrupt */

#define	XUARTPS_IXR_FRAMING 0x00000040 /* Framing error interrupt */

#define	XUARTPS_IXR_OVERRUN 0x00000020 /* Overrun error interrupt */

#define	XUARTPS_IXR_TXFULL 0x00000010 /* TX FIFO Full interrupt */

#define	XUARTPS_IXR_TXEMPTY 0x00000008 /* TX FIFO empty interrupt */

#define	XUARTPS_ISR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt */

#define	XUARTPS_IXR_RXTRIG 0x00000001 /* RX FIFO trigger interrupt */

#define	XUARTPS_IXR_RXFULL 0x00000004 /* RX FIFO full interrupt. */

#define	XUARTPS_IXR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt. */

#define	XUARTPS_IXR_MASK 0x00001FFF /* Valid bit mask */

#define	XUARTPS_SR_RXEMPTY 0x00000002 /* RX FIFO empty */

#define	XUARTPS_SR_TXEMPTY 0x00000008 /* TX FIFO empty */

#define	XUARTPS_SR_TXFULL 0x00000010 /* TX FIFO full */

#define	XUARTPS_SR_RXTRIG 0x00000001 /* Rx Trigger */

#define	xuartps_of_match NULL

Functions
	module_init (xuartps_init)

	module_exit (xuartps_exit)

	MODULE_DESCRIPTION ("Driver for PS UART")

	MODULE_AUTHOR ("Xilinx Inc.")

	MODULE_LICENSE ("GPL")

Macro Definition Documentation

#define XUARTPS_BAUDDIV_OFFSET 0x34 /* Baud Rate Divider [7:0] */

Definition at line 55 of file xilinx_uartps.c.

#define XUARTPS_BAUDGEN_OFFSET 0x18 /* Baud Rate Generator [15:0] */

Definition at line 48 of file xilinx_uartps.c.

#define XUARTPS_CR_OFFSET 0x00 /* Control Register [8:0] */

UART

Register offsets for the UART.

Definition at line 42 of file xilinx_uartps.c.

#define XUARTPS_CR_RST_TO 0x00000040 /* Restart Timeout Counter */

Definition at line 75 of file xilinx_uartps.c.

#define XUARTPS_CR_RX_DIS 0x00000008 /* RX disabled. */

Definition at line 71 of file xilinx_uartps.c.

#define XUARTPS_CR_RX_EN 0x00000004 /* RX enabled */

Definition at line 72 of file xilinx_uartps.c.

#define XUARTPS_CR_RXRST 0x00000001 /* RX logic reset */

Definition at line 74 of file xilinx_uartps.c.

#define XUARTPS_CR_STARTBRK 0x00000080 /* Set TX break */

Definition at line 68 of file xilinx_uartps.c.

#define XUARTPS_CR_STOPBRK 0x00000100 /* Stop TX break */

Control Register

The Control register (CR) controls the major functions of the device.

Control Register Bit Definitions

Definition at line 67 of file xilinx_uartps.c.

#define XUARTPS_CR_TX_DIS 0x00000020 /* TX disabled. */

Definition at line 69 of file xilinx_uartps.c.

#define XUARTPS_CR_TX_EN 0x00000010 /* TX enabled */

Definition at line 70 of file xilinx_uartps.c.

#define XUARTPS_CR_TXRST 0x00000002 /* TX logic reset */

Definition at line 73 of file xilinx_uartps.c.

#define XUARTPS_FIFO_OFFSET 0x30 /* FIFO [15:0] or [7:0] */

Definition at line 54 of file xilinx_uartps.c.

#define XUARTPS_FIFO_SIZE 16 /* FIFO size */

Definition at line 30 of file xilinx_uartps.c.

#define XUARTPS_FLOWDEL_OFFSET 0x38 /* Flow Delay [15:0] */

Definition at line 56 of file xilinx_uartps.c.

#define XUARTPS_IDR_OFFSET 0x0C /* Interrupt Disable [10:0] */

Definition at line 45 of file xilinx_uartps.c.

#define XUARTPS_IER_OFFSET 0x08 /* Interrupt Enable [10:0] */

Definition at line 44 of file xilinx_uartps.c.

#define XUARTPS_IMR_OFFSET 0x10 /* Interrupt Mask [10:0] */

Definition at line 46 of file xilinx_uartps.c.

#define XUARTPS_IRRX_PWIDTH_OFFSET

Value:

0x3C /* IR Minimum Received Pulse

Width [15:0] */

Definition at line 57 of file xilinx_uartps.c.

#define XUARTPS_IRTX_PWIDTH_OFFSET

Value:

0x40 /* IR Transmitted pulse

Width [7:0] */

Definition at line 58 of file xilinx_uartps.c.

#define XUARTPS_ISR_OFFSET 0x14 /* Interrupt Status [10:0]*/

Definition at line 47 of file xilinx_uartps.c.

#define XUARTPS_ISR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt */

Definition at line 121 of file xilinx_uartps.c.

#define XUARTPS_IXR_FRAMING 0x00000040 /* Framing error interrupt */

Definition at line 117 of file xilinx_uartps.c.

#define XUARTPS_IXR_MASK 0x00001FFF /* Valid bit mask */

Definition at line 125 of file xilinx_uartps.c.

#define XUARTPS_IXR_OVERRUN 0x00000020 /* Overrun error interrupt */

Definition at line 118 of file xilinx_uartps.c.

#define XUARTPS_IXR_PARITY 0x00000080 /* Parity error interrupt */

Definition at line 116 of file xilinx_uartps.c.

#define XUARTPS_IXR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt. */

Definition at line 124 of file xilinx_uartps.c.

#define XUARTPS_IXR_RXFULL 0x00000004 /* RX FIFO full interrupt. */

Definition at line 123 of file xilinx_uartps.c.

#define XUARTPS_IXR_RXTRIG 0x00000001 /* RX FIFO trigger interrupt */

Definition at line 122 of file xilinx_uartps.c.

#define XUARTPS_IXR_TOUT 0x00000100 /* RX Timeout error interrupt */

Interrupt Registers

Interrupt control logic uses the interrupt enable register (IER) and the interrupt disable register (IDR) to set the value of the bits in the interrupt mask register (IMR). The IMR determines whether to pass an interrupt to the interrupt status register (ISR). Writing a 1 to IER Enables an interrupt, writing a 1 to IDR disables an interrupt. IMR and ISR are read only, and IER and IDR are write only. Reading either IER or IDR returns 0x00.

All four registers have the same bit definitions.

Definition at line 115 of file xilinx_uartps.c.

#define XUARTPS_IXR_TXEMPTY 0x00000008 /* TX FIFO empty interrupt */

Definition at line 120 of file xilinx_uartps.c.

#define XUARTPS_IXR_TXFULL 0x00000010 /* TX FIFO Full interrupt */

Definition at line 119 of file xilinx_uartps.c.

#define XUARTPS_MAJOR 0 /* use dynamic node allocation */

Definition at line 27 of file xilinx_uartps.c.

#define XUARTPS_MINOR 0 /* works best with devtmpfs */

Definition at line 28 of file xilinx_uartps.c.

#define XUARTPS_MODEMCR_OFFSET 0x24 /* Modem Control [5:0] */

Definition at line 51 of file xilinx_uartps.c.

#define XUARTPS_MODEMSR_OFFSET 0x28 /* Modem Status [8:0] */

Definition at line 52 of file xilinx_uartps.c.

#define XUARTPS_MR_CHARLEN_6_BIT 0x00000006 /* 6 bits data */

Definition at line 99 of file xilinx_uartps.c.

#define XUARTPS_MR_CHARLEN_7_BIT 0x00000004 /* 7 bits data */

Definition at line 100 of file xilinx_uartps.c.

#define XUARTPS_MR_CHARLEN_8_BIT 0x00000000 /* 8 bits data */

Definition at line 101 of file xilinx_uartps.c.

#define XUARTPS_MR_CHMODE_L_LOOP 0x00000200 /* Local loop back mode */

Definition at line 87 of file xilinx_uartps.c.

#define XUARTPS_MR_CHMODE_NORM 0x00000000 /* Normal mode */

Definition at line 88 of file xilinx_uartps.c.

#define XUARTPS_MR_CLKSEL 0x00000001 /* Pre-scalar selection */

Mode Register

The mode register (MR) defines the mode of transfer as well as the data format. If this register is modified during transmission or reception, data validity cannot be guaranteed.

Mode Register Bit Definitions

Definition at line 86 of file xilinx_uartps.c.

#define XUARTPS_MR_OFFSET 0x04 /* Mode Register [10:0] */

Definition at line 43 of file xilinx_uartps.c.

#define XUARTPS_MR_PARITY_EVEN 0x00000000 /* Even parity mode */

Definition at line 97 of file xilinx_uartps.c.

#define XUARTPS_MR_PARITY_MARK 0x00000018 /* Mark parity mode */

Definition at line 94 of file xilinx_uartps.c.

#define XUARTPS_MR_PARITY_NONE 0x00000020 /* No parity mode */

Definition at line 93 of file xilinx_uartps.c.

#define XUARTPS_MR_PARITY_ODD 0x00000008 /* Odd parity mode */

Definition at line 96 of file xilinx_uartps.c.

#define XUARTPS_MR_PARITY_SPACE 0x00000010 /* Space parity mode */

Definition at line 95 of file xilinx_uartps.c.

#define XUARTPS_MR_STOPMODE_1_BIT 0x00000000 /* 1 stop bit */

Definition at line 91 of file xilinx_uartps.c.

#define XUARTPS_MR_STOPMODE_2_BIT 0x00000080 /* 2 stop bits */

Definition at line 90 of file xilinx_uartps.c.

#define XUARTPS_NAME "xuartps"

Definition at line 26 of file xilinx_uartps.c.

#define XUARTPS_NR_PORTS 2

Definition at line 29 of file xilinx_uartps.c.

#define xuartps_of_match NULL

Definition at line 1053 of file xilinx_uartps.c.

#define xuartps_readl ( offset ) ioread32(port->membase + offset)

Definition at line 33 of file xilinx_uartps.c.

#define XUARTPS_REGISTER_SPACE 0xFFF

Definition at line 31 of file xilinx_uartps.c.

#define XUARTPS_RXTOUT_OFFSET 0x1C /* RX Timeout [7:0] */

Definition at line 49 of file xilinx_uartps.c.

#define XUARTPS_RXWM_OFFSET 0x20 /* RX FIFO Trigger Level [5:0] */

Definition at line 50 of file xilinx_uartps.c.

#define XUARTPS_SR_OFFSET 0x2C /* Channel Status [11:0] */

Definition at line 53 of file xilinx_uartps.c.

#define XUARTPS_SR_RXEMPTY 0x00000002 /* RX FIFO empty */

Channel Status Register

The channel status register (CSR) is provided to enable the control logic to monitor the status of bits in the channel interrupt status register, even if these are masked out by the interrupt mask register.

Definition at line 133 of file xilinx_uartps.c.

#define XUARTPS_SR_RXTRIG 0x00000001 /* Rx Trigger */

Definition at line 136 of file xilinx_uartps.c.

#define XUARTPS_SR_TXEMPTY 0x00000008 /* TX FIFO empty */

Definition at line 134 of file xilinx_uartps.c.

#define XUARTPS_SR_TXFULL 0x00000010 /* TX FIFO full */

Definition at line 135 of file xilinx_uartps.c.

#define XUARTPS_TTY_NAME "ttyPS"

Definition at line 25 of file xilinx_uartps.c.

#define XUARTPS_TXWM_OFFSET 0x44 /* TX FIFO Trigger Level [5:0] */

Definition at line 59 of file xilinx_uartps.c.

#define xuartps_writel	(	val,
		offset
	)	iowrite32(val, port->membase + offset)

Definition at line 34 of file xilinx_uartps.c.

Function Documentation

MODULE_AUTHOR ( "Xilinx Inc." )

MODULE_DESCRIPTION ( "Driver for PS UART" )

module_exit ( xuartps_exit )

module_init ( xuartps_init )

MODULE_LICENSE ( "GPL" )

Macros

Functions

Macro Definition Documentation

Function Documentation