1.7.6.1Copyright © 2003-2014 University of Illinois at Urbana-Champaign. All Rights Reserved.
LLVM API Documentation
00001 //===-- AArch64BaseInfo.h - Top level definitions for AArch64 ---*- C++ -*-===// 00002 // 00003 // The LLVM Compiler Infrastructure 00004 // 00005 // This file is distributed under the University of Illinois Open Source 00006 // License. See LICENSE.TXT for details. 00007 // 00008 //===----------------------------------------------------------------------===// 00009 // 00010 // This file contains small standalone helper functions and enum definitions for 00011 // the AArch64 target useful for the compiler back-end and the MC libraries. 00012 // As such, it deliberately does not include references to LLVM core 00013 // code gen types, passes, etc.. 00014 // 00015 //===----------------------------------------------------------------------===// 00016 00017 #ifndef LLVM_LIB_TARGET_AARCH64_UTILS_AARCH64BASEINFO_H 00018 #define LLVM_LIB_TARGET_AARCH64_UTILS_AARCH64BASEINFO_H 00019 00020 // FIXME: Is it easiest to fix this layering violation by moving the .inc 00021 // #includes from AArch64MCTargetDesc.h to here? 00022 #include "MCTargetDesc/AArch64MCTargetDesc.h" // For AArch64::X0 and friends. 00023 #include "llvm/ADT/STLExtras.h" 00024 #include "llvm/ADT/StringSwitch.h" 00025 #include "llvm/Support/ErrorHandling.h" 00026 00027 namespace llvm { 00028 00029 inline static unsigned getWRegFromXReg(unsigned Reg) { 00030 switch (Reg) { 00031 case AArch64::X0: return AArch64::W0; 00032 case AArch64::X1: return AArch64::W1; 00033 case AArch64::X2: return AArch64::W2; 00034 case AArch64::X3: return AArch64::W3; 00035 case AArch64::X4: return AArch64::W4; 00036 case AArch64::X5: return AArch64::W5; 00037 case AArch64::X6: return AArch64::W6; 00038 case AArch64::X7: return AArch64::W7; 00039 case AArch64::X8: return AArch64::W8; 00040 case AArch64::X9: return AArch64::W9; 00041 case AArch64::X10: return AArch64::W10; 00042 case AArch64::X11: return AArch64::W11; 00043 case AArch64::X12: return AArch64::W12; 00044 case AArch64::X13: return AArch64::W13; 00045 case AArch64::X14: return AArch64::W14; 00046 case AArch64::X15: return AArch64::W15; 00047 case AArch64::X16: return AArch64::W16; 00048 case AArch64::X17: return AArch64::W17; 00049 case AArch64::X18: return AArch64::W18; 00050 case AArch64::X19: return AArch64::W19; 00051 case AArch64::X20: return AArch64::W20; 00052 case AArch64::X21: return AArch64::W21; 00053 case AArch64::X22: return AArch64::W22; 00054 case AArch64::X23: return AArch64::W23; 00055 case AArch64::X24: return AArch64::W24; 00056 case AArch64::X25: return AArch64::W25; 00057 case AArch64::X26: return AArch64::W26; 00058 case AArch64::X27: return AArch64::W27; 00059 case AArch64::X28: return AArch64::W28; 00060 case AArch64::FP: return AArch64::W29; 00061 case AArch64::LR: return AArch64::W30; 00062 case AArch64::SP: return AArch64::WSP; 00063 case AArch64::XZR: return AArch64::WZR; 00064 } 00065 // For anything else, return it unchanged. 00066 return Reg; 00067 } 00068 00069 inline static unsigned getXRegFromWReg(unsigned Reg) { 00070 switch (Reg) { 00071 case AArch64::W0: return AArch64::X0; 00072 case AArch64::W1: return AArch64::X1; 00073 case AArch64::W2: return AArch64::X2; 00074 case AArch64::W3: return AArch64::X3; 00075 case AArch64::W4: return AArch64::X4; 00076 case AArch64::W5: return AArch64::X5; 00077 case AArch64::W6: return AArch64::X6; 00078 case AArch64::W7: return AArch64::X7; 00079 case AArch64::W8: return AArch64::X8; 00080 case AArch64::W9: return AArch64::X9; 00081 case AArch64::W10: return AArch64::X10; 00082 case AArch64::W11: return AArch64::X11; 00083 case AArch64::W12: return AArch64::X12; 00084 case AArch64::W13: return AArch64::X13; 00085 case AArch64::W14: return AArch64::X14; 00086 case AArch64::W15: return AArch64::X15; 00087 case AArch64::W16: return AArch64::X16; 00088 case AArch64::W17: return AArch64::X17; 00089 case AArch64::W18: return AArch64::X18; 00090 case AArch64::W19: return AArch64::X19; 00091 case AArch64::W20: return AArch64::X20; 00092 case AArch64::W21: return AArch64::X21; 00093 case AArch64::W22: return AArch64::X22; 00094 case AArch64::W23: return AArch64::X23; 00095 case AArch64::W24: return AArch64::X24; 00096 case AArch64::W25: return AArch64::X25; 00097 case AArch64::W26: return AArch64::X26; 00098 case AArch64::W27: return AArch64::X27; 00099 case AArch64::W28: return AArch64::X28; 00100 case AArch64::W29: return AArch64::FP; 00101 case AArch64::W30: return AArch64::LR; 00102 case AArch64::WSP: return AArch64::SP; 00103 case AArch64::WZR: return AArch64::XZR; 00104 } 00105 // For anything else, return it unchanged. 00106 return Reg; 00107 } 00108 00109 static inline unsigned getBRegFromDReg(unsigned Reg) { 00110 switch (Reg) { 00111 case AArch64::D0: return AArch64::B0; 00112 case AArch64::D1: return AArch64::B1; 00113 case AArch64::D2: return AArch64::B2; 00114 case AArch64::D3: return AArch64::B3; 00115 case AArch64::D4: return AArch64::B4; 00116 case AArch64::D5: return AArch64::B5; 00117 case AArch64::D6: return AArch64::B6; 00118 case AArch64::D7: return AArch64::B7; 00119 case AArch64::D8: return AArch64::B8; 00120 case AArch64::D9: return AArch64::B9; 00121 case AArch64::D10: return AArch64::B10; 00122 case AArch64::D11: return AArch64::B11; 00123 case AArch64::D12: return AArch64::B12; 00124 case AArch64::D13: return AArch64::B13; 00125 case AArch64::D14: return AArch64::B14; 00126 case AArch64::D15: return AArch64::B15; 00127 case AArch64::D16: return AArch64::B16; 00128 case AArch64::D17: return AArch64::B17; 00129 case AArch64::D18: return AArch64::B18; 00130 case AArch64::D19: return AArch64::B19; 00131 case AArch64::D20: return AArch64::B20; 00132 case AArch64::D21: return AArch64::B21; 00133 case AArch64::D22: return AArch64::B22; 00134 case AArch64::D23: return AArch64::B23; 00135 case AArch64::D24: return AArch64::B24; 00136 case AArch64::D25: return AArch64::B25; 00137 case AArch64::D26: return AArch64::B26; 00138 case AArch64::D27: return AArch64::B27; 00139 case AArch64::D28: return AArch64::B28; 00140 case AArch64::D29: return AArch64::B29; 00141 case AArch64::D30: return AArch64::B30; 00142 case AArch64::D31: return AArch64::B31; 00143 } 00144 // For anything else, return it unchanged. 00145 return Reg; 00146 } 00147 00148 00149 static inline unsigned getDRegFromBReg(unsigned Reg) { 00150 switch (Reg) { 00151 case AArch64::B0: return AArch64::D0; 00152 case AArch64::B1: return AArch64::D1; 00153 case AArch64::B2: return AArch64::D2; 00154 case AArch64::B3: return AArch64::D3; 00155 case AArch64::B4: return AArch64::D4; 00156 case AArch64::B5: return AArch64::D5; 00157 case AArch64::B6: return AArch64::D6; 00158 case AArch64::B7: return AArch64::D7; 00159 case AArch64::B8: return AArch64::D8; 00160 case AArch64::B9: return AArch64::D9; 00161 case AArch64::B10: return AArch64::D10; 00162 case AArch64::B11: return AArch64::D11; 00163 case AArch64::B12: return AArch64::D12; 00164 case AArch64::B13: return AArch64::D13; 00165 case AArch64::B14: return AArch64::D14; 00166 case AArch64::B15: return AArch64::D15; 00167 case AArch64::B16: return AArch64::D16; 00168 case AArch64::B17: return AArch64::D17; 00169 case AArch64::B18: return AArch64::D18; 00170 case AArch64::B19: return AArch64::D19; 00171 case AArch64::B20: return AArch64::D20; 00172 case AArch64::B21: return AArch64::D21; 00173 case AArch64::B22: return AArch64::D22; 00174 case AArch64::B23: return AArch64::D23; 00175 case AArch64::B24: return AArch64::D24; 00176 case AArch64::B25: return AArch64::D25; 00177 case AArch64::B26: return AArch64::D26; 00178 case AArch64::B27: return AArch64::D27; 00179 case AArch64::B28: return AArch64::D28; 00180 case AArch64::B29: return AArch64::D29; 00181 case AArch64::B30: return AArch64::D30; 00182 case AArch64::B31: return AArch64::D31; 00183 } 00184 // For anything else, return it unchanged. 00185 return Reg; 00186 } 00187 00188 namespace AArch64CC { 00189 00190 // The CondCodes constants map directly to the 4-bit encoding of the condition 00191 // field for predicated instructions. 00192 enum CondCode { // Meaning (integer) Meaning (floating-point) 00193 EQ = 0x0, // Equal Equal 00194 NE = 0x1, // Not equal Not equal, or unordered 00195 HS = 0x2, // Unsigned higher or same >, ==, or unordered 00196 LO = 0x3, // Unsigned lower Less than 00197 MI = 0x4, // Minus, negative Less than 00198 PL = 0x5, // Plus, positive or zero >, ==, or unordered 00199 VS = 0x6, // Overflow Unordered 00200 VC = 0x7, // No overflow Not unordered 00201 HI = 0x8, // Unsigned higher Greater than, or unordered 00202 LS = 0x9, // Unsigned lower or same Less than or equal 00203 GE = 0xa, // Greater than or equal Greater than or equal 00204 LT = 0xb, // Less than Less than, or unordered 00205 GT = 0xc, // Greater than Greater than 00206 LE = 0xd, // Less than or equal <, ==, or unordered 00207 AL = 0xe, // Always (unconditional) Always (unconditional) 00208 NV = 0xf, // Always (unconditional) Always (unconditional) 00209 // Note the NV exists purely to disassemble 0b1111. Execution is "always". 00210 Invalid 00211 }; 00212 00213 inline static const char *getCondCodeName(CondCode Code) { 00214 switch (Code) { 00215 default: llvm_unreachable("Unknown condition code"); 00216 case EQ: return "eq"; 00217 case NE: return "ne"; 00218 case HS: return "hs"; 00219 case LO: return "lo"; 00220 case MI: return "mi"; 00221 case PL: return "pl"; 00222 case VS: return "vs"; 00223 case VC: return "vc"; 00224 case HI: return "hi"; 00225 case LS: return "ls"; 00226 case GE: return "ge"; 00227 case LT: return "lt"; 00228 case GT: return "gt"; 00229 case LE: return "le"; 00230 case AL: return "al"; 00231 case NV: return "nv"; 00232 } 00233 } 00234 00235 inline static CondCode getInvertedCondCode(CondCode Code) { 00236 // To reverse a condition it's necessary to only invert the low bit: 00237 00238 return static_cast<CondCode>(static_cast<unsigned>(Code) ^ 0x1); 00239 } 00240 00241 /// Given a condition code, return NZCV flags that would satisfy that condition. 00242 /// The flag bits are in the format expected by the ccmp instructions. 00243 /// Note that many different flag settings can satisfy a given condition code, 00244 /// this function just returns one of them. 00245 inline static unsigned getNZCVToSatisfyCondCode(CondCode Code) { 00246 // NZCV flags encoded as expected by ccmp instructions, ARMv8 ISA 5.5.7. 00247 enum { N = 8, Z = 4, C = 2, V = 1 }; 00248 switch (Code) { 00249 default: llvm_unreachable("Unknown condition code"); 00250 case EQ: return Z; // Z == 1 00251 case NE: return 0; // Z == 0 00252 case HS: return C; // C == 1 00253 case LO: return 0; // C == 0 00254 case MI: return N; // N == 1 00255 case PL: return 0; // N == 0 00256 case VS: return V; // V == 1 00257 case VC: return 0; // V == 0 00258 case HI: return C; // C == 1 && Z == 0 00259 case LS: return 0; // C == 0 || Z == 1 00260 case GE: return 0; // N == V 00261 case LT: return N; // N != V 00262 case GT: return 0; // Z == 0 && N == V 00263 case LE: return Z; // Z == 1 || N != V 00264 } 00265 } 00266 } // end namespace AArch64CC 00267 00268 /// Instances of this class can perform bidirectional mapping from random 00269 /// identifier strings to operand encodings. For example "MSR" takes a named 00270 /// system-register which must be encoded somehow and decoded for printing. This 00271 /// central location means that the information for those transformations is not 00272 /// duplicated and remains in sync. 00273 /// 00274 /// FIXME: currently the algorithm is a completely unoptimised linear 00275 /// search. Obviously this could be improved, but we would probably want to work 00276 /// out just how often these instructions are emitted before working on it. It 00277 /// might even be optimal to just reorder the tables for the common instructions 00278 /// rather than changing the algorithm. 00279 struct AArch64NamedImmMapper { 00280 struct Mapping { 00281 const char *Name; 00282 uint32_t Value; 00283 }; 00284 00285 template<int N> 00286 AArch64NamedImmMapper(const Mapping (&Pairs)[N], uint32_t TooBigImm) 00287 : Pairs(&Pairs[0]), NumPairs(N), TooBigImm(TooBigImm) {} 00288 00289 StringRef toString(uint32_t Value, bool &Valid) const; 00290 uint32_t fromString(StringRef Name, bool &Valid) const; 00291 00292 /// Many of the instructions allow an alternative assembly form consisting of 00293 /// a simple immediate. Currently the only valid forms are ranges [0, N) where 00294 /// N being 0 indicates no immediate syntax-form is allowed. 00295 bool validImm(uint32_t Value) const; 00296 protected: 00297 const Mapping *Pairs; 00298 size_t NumPairs; 00299 uint32_t TooBigImm; 00300 }; 00301 00302 namespace AArch64AT { 00303 enum ATValues { 00304 Invalid = -1, // Op0 Op1 CRn CRm Op2 00305 S1E1R = 0x43c0, // 01 000 0111 1000 000 00306 S1E2R = 0x63c0, // 01 100 0111 1000 000 00307 S1E3R = 0x73c0, // 01 110 0111 1000 000 00308 S1E1W = 0x43c1, // 01 000 0111 1000 001 00309 S1E2W = 0x63c1, // 01 100 0111 1000 001 00310 S1E3W = 0x73c1, // 01 110 0111 1000 001 00311 S1E0R = 0x43c2, // 01 000 0111 1000 010 00312 S1E0W = 0x43c3, // 01 000 0111 1000 011 00313 S12E1R = 0x63c4, // 01 100 0111 1000 100 00314 S12E1W = 0x63c5, // 01 100 0111 1000 101 00315 S12E0R = 0x63c6, // 01 100 0111 1000 110 00316 S12E0W = 0x63c7 // 01 100 0111 1000 111 00317 }; 00318 00319 struct ATMapper : AArch64NamedImmMapper { 00320 const static Mapping ATPairs[]; 00321 00322 ATMapper(); 00323 }; 00324 00325 } 00326 namespace AArch64DB { 00327 enum DBValues { 00328 Invalid = -1, 00329 OSHLD = 0x1, 00330 OSHST = 0x2, 00331 OSH = 0x3, 00332 NSHLD = 0x5, 00333 NSHST = 0x6, 00334 NSH = 0x7, 00335 ISHLD = 0x9, 00336 ISHST = 0xa, 00337 ISH = 0xb, 00338 LD = 0xd, 00339 ST = 0xe, 00340 SY = 0xf 00341 }; 00342 00343 struct DBarrierMapper : AArch64NamedImmMapper { 00344 const static Mapping DBarrierPairs[]; 00345 00346 DBarrierMapper(); 00347 }; 00348 } 00349 00350 namespace AArch64DC { 00351 enum DCValues { 00352 Invalid = -1, // Op1 CRn CRm Op2 00353 ZVA = 0x5ba1, // 01 011 0111 0100 001 00354 IVAC = 0x43b1, // 01 000 0111 0110 001 00355 ISW = 0x43b2, // 01 000 0111 0110 010 00356 CVAC = 0x5bd1, // 01 011 0111 1010 001 00357 CSW = 0x43d2, // 01 000 0111 1010 010 00358 CVAU = 0x5bd9, // 01 011 0111 1011 001 00359 CIVAC = 0x5bf1, // 01 011 0111 1110 001 00360 CISW = 0x43f2 // 01 000 0111 1110 010 00361 }; 00362 00363 struct DCMapper : AArch64NamedImmMapper { 00364 const static Mapping DCPairs[]; 00365 00366 DCMapper(); 00367 }; 00368 00369 } 00370 00371 namespace AArch64IC { 00372 enum ICValues { 00373 Invalid = -1, // Op1 CRn CRm Op2 00374 IALLUIS = 0x0388, // 000 0111 0001 000 00375 IALLU = 0x03a8, // 000 0111 0101 000 00376 IVAU = 0x1ba9 // 011 0111 0101 001 00377 }; 00378 00379 00380 struct ICMapper : AArch64NamedImmMapper { 00381 const static Mapping ICPairs[]; 00382 00383 ICMapper(); 00384 }; 00385 00386 static inline bool NeedsRegister(ICValues Val) { 00387 return Val == IVAU; 00388 } 00389 } 00390 00391 namespace AArch64ISB { 00392 enum ISBValues { 00393 Invalid = -1, 00394 SY = 0xf 00395 }; 00396 struct ISBMapper : AArch64NamedImmMapper { 00397 const static Mapping ISBPairs[]; 00398 00399 ISBMapper(); 00400 }; 00401 } 00402 00403 namespace AArch64PRFM { 00404 enum PRFMValues { 00405 Invalid = -1, 00406 PLDL1KEEP = 0x00, 00407 PLDL1STRM = 0x01, 00408 PLDL2KEEP = 0x02, 00409 PLDL2STRM = 0x03, 00410 PLDL3KEEP = 0x04, 00411 PLDL3STRM = 0x05, 00412 PLIL1KEEP = 0x08, 00413 PLIL1STRM = 0x09, 00414 PLIL2KEEP = 0x0a, 00415 PLIL2STRM = 0x0b, 00416 PLIL3KEEP = 0x0c, 00417 PLIL3STRM = 0x0d, 00418 PSTL1KEEP = 0x10, 00419 PSTL1STRM = 0x11, 00420 PSTL2KEEP = 0x12, 00421 PSTL2STRM = 0x13, 00422 PSTL3KEEP = 0x14, 00423 PSTL3STRM = 0x15 00424 }; 00425 00426 struct PRFMMapper : AArch64NamedImmMapper { 00427 const static Mapping PRFMPairs[]; 00428 00429 PRFMMapper(); 00430 }; 00431 } 00432 00433 namespace AArch64PState { 00434 enum PStateValues { 00435 Invalid = -1, 00436 SPSel = 0x05, 00437 DAIFSet = 0x1e, 00438 DAIFClr = 0x1f 00439 }; 00440 00441 struct PStateMapper : AArch64NamedImmMapper { 00442 const static Mapping PStatePairs[]; 00443 00444 PStateMapper(); 00445 }; 00446 00447 } 00448 00449 namespace AArch64SE { 00450 enum ShiftExtSpecifiers { 00451 Invalid = -1, 00452 LSL, 00453 MSL, 00454 LSR, 00455 ASR, 00456 ROR, 00457 00458 UXTB, 00459 UXTH, 00460 UXTW, 00461 UXTX, 00462 00463 SXTB, 00464 SXTH, 00465 SXTW, 00466 SXTX 00467 }; 00468 } 00469 00470 namespace AArch64Layout { 00471 enum VectorLayout { 00472 Invalid = -1, 00473 VL_8B, 00474 VL_4H, 00475 VL_2S, 00476 VL_1D, 00477 00478 VL_16B, 00479 VL_8H, 00480 VL_4S, 00481 VL_2D, 00482 00483 // Bare layout for the 128-bit vector 00484 // (only show ".b", ".h", ".s", ".d" without vector number) 00485 VL_B, 00486 VL_H, 00487 VL_S, 00488 VL_D 00489 }; 00490 } 00491 00492 inline static const char * 00493 AArch64VectorLayoutToString(AArch64Layout::VectorLayout Layout) { 00494 switch (Layout) { 00495 case AArch64Layout::VL_8B: return ".8b"; 00496 case AArch64Layout::VL_4H: return ".4h"; 00497 case AArch64Layout::VL_2S: return ".2s"; 00498 case AArch64Layout::VL_1D: return ".1d"; 00499 case AArch64Layout::VL_16B: return ".16b"; 00500 case AArch64Layout::VL_8H: return ".8h"; 00501 case AArch64Layout::VL_4S: return ".4s"; 00502 case AArch64Layout::VL_2D: return ".2d"; 00503 case AArch64Layout::VL_B: return ".b"; 00504 case AArch64Layout::VL_H: return ".h"; 00505 case AArch64Layout::VL_S: return ".s"; 00506 case AArch64Layout::VL_D: return ".d"; 00507 default: llvm_unreachable("Unknown Vector Layout"); 00508 } 00509 } 00510 00511 inline static AArch64Layout::VectorLayout 00512 AArch64StringToVectorLayout(StringRef LayoutStr) { 00513 return StringSwitch<AArch64Layout::VectorLayout>(LayoutStr) 00514 .Case(".8b", AArch64Layout::VL_8B) 00515 .Case(".4h", AArch64Layout::VL_4H) 00516 .Case(".2s", AArch64Layout::VL_2S) 00517 .Case(".1d", AArch64Layout::VL_1D) 00518 .Case(".16b", AArch64Layout::VL_16B) 00519 .Case(".8h", AArch64Layout::VL_8H) 00520 .Case(".4s", AArch64Layout::VL_4S) 00521 .Case(".2d", AArch64Layout::VL_2D) 00522 .Case(".b", AArch64Layout::VL_B) 00523 .Case(".h", AArch64Layout::VL_H) 00524 .Case(".s", AArch64Layout::VL_S) 00525 .Case(".d", AArch64Layout::VL_D) 00526 .Default(AArch64Layout::Invalid); 00527 } 00528 00529 namespace AArch64SysReg { 00530 enum SysRegROValues { 00531 MDCCSR_EL0 = 0x9808, // 10 011 0000 0001 000 00532 DBGDTRRX_EL0 = 0x9828, // 10 011 0000 0101 000 00533 MDRAR_EL1 = 0x8080, // 10 000 0001 0000 000 00534 OSLSR_EL1 = 0x808c, // 10 000 0001 0001 100 00535 DBGAUTHSTATUS_EL1 = 0x83f6, // 10 000 0111 1110 110 00536 PMCEID0_EL0 = 0xdce6, // 11 011 1001 1100 110 00537 PMCEID1_EL0 = 0xdce7, // 11 011 1001 1100 111 00538 MIDR_EL1 = 0xc000, // 11 000 0000 0000 000 00539 CCSIDR_EL1 = 0xc800, // 11 001 0000 0000 000 00540 CLIDR_EL1 = 0xc801, // 11 001 0000 0000 001 00541 CTR_EL0 = 0xd801, // 11 011 0000 0000 001 00542 MPIDR_EL1 = 0xc005, // 11 000 0000 0000 101 00543 REVIDR_EL1 = 0xc006, // 11 000 0000 0000 110 00544 AIDR_EL1 = 0xc807, // 11 001 0000 0000 111 00545 DCZID_EL0 = 0xd807, // 11 011 0000 0000 111 00546 ID_PFR0_EL1 = 0xc008, // 11 000 0000 0001 000 00547 ID_PFR1_EL1 = 0xc009, // 11 000 0000 0001 001 00548 ID_DFR0_EL1 = 0xc00a, // 11 000 0000 0001 010 00549 ID_AFR0_EL1 = 0xc00b, // 11 000 0000 0001 011 00550 ID_MMFR0_EL1 = 0xc00c, // 11 000 0000 0001 100 00551 ID_MMFR1_EL1 = 0xc00d, // 11 000 0000 0001 101 00552 ID_MMFR2_EL1 = 0xc00e, // 11 000 0000 0001 110 00553 ID_MMFR3_EL1 = 0xc00f, // 11 000 0000 0001 111 00554 ID_ISAR0_EL1 = 0xc010, // 11 000 0000 0010 000 00555 ID_ISAR1_EL1 = 0xc011, // 11 000 0000 0010 001 00556 ID_ISAR2_EL1 = 0xc012, // 11 000 0000 0010 010 00557 ID_ISAR3_EL1 = 0xc013, // 11 000 0000 0010 011 00558 ID_ISAR4_EL1 = 0xc014, // 11 000 0000 0010 100 00559 ID_ISAR5_EL1 = 0xc015, // 11 000 0000 0010 101 00560 ID_A64PFR0_EL1 = 0xc020, // 11 000 0000 0100 000 00561 ID_A64PFR1_EL1 = 0xc021, // 11 000 0000 0100 001 00562 ID_A64DFR0_EL1 = 0xc028, // 11 000 0000 0101 000 00563 ID_A64DFR1_EL1 = 0xc029, // 11 000 0000 0101 001 00564 ID_A64AFR0_EL1 = 0xc02c, // 11 000 0000 0101 100 00565 ID_A64AFR1_EL1 = 0xc02d, // 11 000 0000 0101 101 00566 ID_A64ISAR0_EL1 = 0xc030, // 11 000 0000 0110 000 00567 ID_A64ISAR1_EL1 = 0xc031, // 11 000 0000 0110 001 00568 ID_A64MMFR0_EL1 = 0xc038, // 11 000 0000 0111 000 00569 ID_A64MMFR1_EL1 = 0xc039, // 11 000 0000 0111 001 00570 MVFR0_EL1 = 0xc018, // 11 000 0000 0011 000 00571 MVFR1_EL1 = 0xc019, // 11 000 0000 0011 001 00572 MVFR2_EL1 = 0xc01a, // 11 000 0000 0011 010 00573 RVBAR_EL1 = 0xc601, // 11 000 1100 0000 001 00574 RVBAR_EL2 = 0xe601, // 11 100 1100 0000 001 00575 RVBAR_EL3 = 0xf601, // 11 110 1100 0000 001 00576 ISR_EL1 = 0xc608, // 11 000 1100 0001 000 00577 CNTPCT_EL0 = 0xdf01, // 11 011 1110 0000 001 00578 CNTVCT_EL0 = 0xdf02, // 11 011 1110 0000 010 00579 00580 // Trace registers 00581 TRCSTATR = 0x8818, // 10 001 0000 0011 000 00582 TRCIDR8 = 0x8806, // 10 001 0000 0000 110 00583 TRCIDR9 = 0x880e, // 10 001 0000 0001 110 00584 TRCIDR10 = 0x8816, // 10 001 0000 0010 110 00585 TRCIDR11 = 0x881e, // 10 001 0000 0011 110 00586 TRCIDR12 = 0x8826, // 10 001 0000 0100 110 00587 TRCIDR13 = 0x882e, // 10 001 0000 0101 110 00588 TRCIDR0 = 0x8847, // 10 001 0000 1000 111 00589 TRCIDR1 = 0x884f, // 10 001 0000 1001 111 00590 TRCIDR2 = 0x8857, // 10 001 0000 1010 111 00591 TRCIDR3 = 0x885f, // 10 001 0000 1011 111 00592 TRCIDR4 = 0x8867, // 10 001 0000 1100 111 00593 TRCIDR5 = 0x886f, // 10 001 0000 1101 111 00594 TRCIDR6 = 0x8877, // 10 001 0000 1110 111 00595 TRCIDR7 = 0x887f, // 10 001 0000 1111 111 00596 TRCOSLSR = 0x888c, // 10 001 0001 0001 100 00597 TRCPDSR = 0x88ac, // 10 001 0001 0101 100 00598 TRCDEVAFF0 = 0x8bd6, // 10 001 0111 1010 110 00599 TRCDEVAFF1 = 0x8bde, // 10 001 0111 1011 110 00600 TRCLSR = 0x8bee, // 10 001 0111 1101 110 00601 TRCAUTHSTATUS = 0x8bf6, // 10 001 0111 1110 110 00602 TRCDEVARCH = 0x8bfe, // 10 001 0111 1111 110 00603 TRCDEVID = 0x8b97, // 10 001 0111 0010 111 00604 TRCDEVTYPE = 0x8b9f, // 10 001 0111 0011 111 00605 TRCPIDR4 = 0x8ba7, // 10 001 0111 0100 111 00606 TRCPIDR5 = 0x8baf, // 10 001 0111 0101 111 00607 TRCPIDR6 = 0x8bb7, // 10 001 0111 0110 111 00608 TRCPIDR7 = 0x8bbf, // 10 001 0111 0111 111 00609 TRCPIDR0 = 0x8bc7, // 10 001 0111 1000 111 00610 TRCPIDR1 = 0x8bcf, // 10 001 0111 1001 111 00611 TRCPIDR2 = 0x8bd7, // 10 001 0111 1010 111 00612 TRCPIDR3 = 0x8bdf, // 10 001 0111 1011 111 00613 TRCCIDR0 = 0x8be7, // 10 001 0111 1100 111 00614 TRCCIDR1 = 0x8bef, // 10 001 0111 1101 111 00615 TRCCIDR2 = 0x8bf7, // 10 001 0111 1110 111 00616 TRCCIDR3 = 0x8bff, // 10 001 0111 1111 111 00617 00618 // GICv3 registers 00619 ICC_IAR1_EL1 = 0xc660, // 11 000 1100 1100 000 00620 ICC_IAR0_EL1 = 0xc640, // 11 000 1100 1000 000 00621 ICC_HPPIR1_EL1 = 0xc662, // 11 000 1100 1100 010 00622 ICC_HPPIR0_EL1 = 0xc642, // 11 000 1100 1000 010 00623 ICC_RPR_EL1 = 0xc65b, // 11 000 1100 1011 011 00624 ICH_VTR_EL2 = 0xe659, // 11 100 1100 1011 001 00625 ICH_EISR_EL2 = 0xe65b, // 11 100 1100 1011 011 00626 ICH_ELSR_EL2 = 0xe65d // 11 100 1100 1011 101 00627 }; 00628 00629 enum SysRegWOValues { 00630 DBGDTRTX_EL0 = 0x9828, // 10 011 0000 0101 000 00631 OSLAR_EL1 = 0x8084, // 10 000 0001 0000 100 00632 PMSWINC_EL0 = 0xdce4, // 11 011 1001 1100 100 00633 00634 // Trace Registers 00635 TRCOSLAR = 0x8884, // 10 001 0001 0000 100 00636 TRCLAR = 0x8be6, // 10 001 0111 1100 110 00637 00638 // GICv3 registers 00639 ICC_EOIR1_EL1 = 0xc661, // 11 000 1100 1100 001 00640 ICC_EOIR0_EL1 = 0xc641, // 11 000 1100 1000 001 00641 ICC_DIR_EL1 = 0xc659, // 11 000 1100 1011 001 00642 ICC_SGI1R_EL1 = 0xc65d, // 11 000 1100 1011 101 00643 ICC_ASGI1R_EL1 = 0xc65e, // 11 000 1100 1011 110 00644 ICC_SGI0R_EL1 = 0xc65f // 11 000 1100 1011 111 00645 }; 00646 00647 enum SysRegValues { 00648 Invalid = -1, // Op0 Op1 CRn CRm Op2 00649 OSDTRRX_EL1 = 0x8002, // 10 000 0000 0000 010 00650 OSDTRTX_EL1 = 0x801a, // 10 000 0000 0011 010 00651 TEECR32_EL1 = 0x9000, // 10 010 0000 0000 000 00652 MDCCINT_EL1 = 0x8010, // 10 000 0000 0010 000 00653 MDSCR_EL1 = 0x8012, // 10 000 0000 0010 010 00654 DBGDTR_EL0 = 0x9820, // 10 011 0000 0100 000 00655 OSECCR_EL1 = 0x8032, // 10 000 0000 0110 010 00656 DBGVCR32_EL2 = 0xa038, // 10 100 0000 0111 000 00657 DBGBVR0_EL1 = 0x8004, // 10 000 0000 0000 100 00658 DBGBVR1_EL1 = 0x800c, // 10 000 0000 0001 100 00659 DBGBVR2_EL1 = 0x8014, // 10 000 0000 0010 100 00660 DBGBVR3_EL1 = 0x801c, // 10 000 0000 0011 100 00661 DBGBVR4_EL1 = 0x8024, // 10 000 0000 0100 100 00662 DBGBVR5_EL1 = 0x802c, // 10 000 0000 0101 100 00663 DBGBVR6_EL1 = 0x8034, // 10 000 0000 0110 100 00664 DBGBVR7_EL1 = 0x803c, // 10 000 0000 0111 100 00665 DBGBVR8_EL1 = 0x8044, // 10 000 0000 1000 100 00666 DBGBVR9_EL1 = 0x804c, // 10 000 0000 1001 100 00667 DBGBVR10_EL1 = 0x8054, // 10 000 0000 1010 100 00668 DBGBVR11_EL1 = 0x805c, // 10 000 0000 1011 100 00669 DBGBVR12_EL1 = 0x8064, // 10 000 0000 1100 100 00670 DBGBVR13_EL1 = 0x806c, // 10 000 0000 1101 100 00671 DBGBVR14_EL1 = 0x8074, // 10 000 0000 1110 100 00672 DBGBVR15_EL1 = 0x807c, // 10 000 0000 1111 100 00673 DBGBCR0_EL1 = 0x8005, // 10 000 0000 0000 101 00674 DBGBCR1_EL1 = 0x800d, // 10 000 0000 0001 101 00675 DBGBCR2_EL1 = 0x8015, // 10 000 0000 0010 101 00676 DBGBCR3_EL1 = 0x801d, // 10 000 0000 0011 101 00677 DBGBCR4_EL1 = 0x8025, // 10 000 0000 0100 101 00678 DBGBCR5_EL1 = 0x802d, // 10 000 0000 0101 101 00679 DBGBCR6_EL1 = 0x8035, // 10 000 0000 0110 101 00680 DBGBCR7_EL1 = 0x803d, // 10 000 0000 0111 101 00681 DBGBCR8_EL1 = 0x8045, // 10 000 0000 1000 101 00682 DBGBCR9_EL1 = 0x804d, // 10 000 0000 1001 101 00683 DBGBCR10_EL1 = 0x8055, // 10 000 0000 1010 101 00684 DBGBCR11_EL1 = 0x805d, // 10 000 0000 1011 101 00685 DBGBCR12_EL1 = 0x8065, // 10 000 0000 1100 101 00686 DBGBCR13_EL1 = 0x806d, // 10 000 0000 1101 101 00687 DBGBCR14_EL1 = 0x8075, // 10 000 0000 1110 101 00688 DBGBCR15_EL1 = 0x807d, // 10 000 0000 1111 101 00689 DBGWVR0_EL1 = 0x8006, // 10 000 0000 0000 110 00690 DBGWVR1_EL1 = 0x800e, // 10 000 0000 0001 110 00691 DBGWVR2_EL1 = 0x8016, // 10 000 0000 0010 110 00692 DBGWVR3_EL1 = 0x801e, // 10 000 0000 0011 110 00693 DBGWVR4_EL1 = 0x8026, // 10 000 0000 0100 110 00694 DBGWVR5_EL1 = 0x802e, // 10 000 0000 0101 110 00695 DBGWVR6_EL1 = 0x8036, // 10 000 0000 0110 110 00696 DBGWVR7_EL1 = 0x803e, // 10 000 0000 0111 110 00697 DBGWVR8_EL1 = 0x8046, // 10 000 0000 1000 110 00698 DBGWVR9_EL1 = 0x804e, // 10 000 0000 1001 110 00699 DBGWVR10_EL1 = 0x8056, // 10 000 0000 1010 110 00700 DBGWVR11_EL1 = 0x805e, // 10 000 0000 1011 110 00701 DBGWVR12_EL1 = 0x8066, // 10 000 0000 1100 110 00702 DBGWVR13_EL1 = 0x806e, // 10 000 0000 1101 110 00703 DBGWVR14_EL1 = 0x8076, // 10 000 0000 1110 110 00704 DBGWVR15_EL1 = 0x807e, // 10 000 0000 1111 110 00705 DBGWCR0_EL1 = 0x8007, // 10 000 0000 0000 111 00706 DBGWCR1_EL1 = 0x800f, // 10 000 0000 0001 111 00707 DBGWCR2_EL1 = 0x8017, // 10 000 0000 0010 111 00708 DBGWCR3_EL1 = 0x801f, // 10 000 0000 0011 111 00709 DBGWCR4_EL1 = 0x8027, // 10 000 0000 0100 111 00710 DBGWCR5_EL1 = 0x802f, // 10 000 0000 0101 111 00711 DBGWCR6_EL1 = 0x8037, // 10 000 0000 0110 111 00712 DBGWCR7_EL1 = 0x803f, // 10 000 0000 0111 111 00713 DBGWCR8_EL1 = 0x8047, // 10 000 0000 1000 111 00714 DBGWCR9_EL1 = 0x804f, // 10 000 0000 1001 111 00715 DBGWCR10_EL1 = 0x8057, // 10 000 0000 1010 111 00716 DBGWCR11_EL1 = 0x805f, // 10 000 0000 1011 111 00717 DBGWCR12_EL1 = 0x8067, // 10 000 0000 1100 111 00718 DBGWCR13_EL1 = 0x806f, // 10 000 0000 1101 111 00719 DBGWCR14_EL1 = 0x8077, // 10 000 0000 1110 111 00720 DBGWCR15_EL1 = 0x807f, // 10 000 0000 1111 111 00721 TEEHBR32_EL1 = 0x9080, // 10 010 0001 0000 000 00722 OSDLR_EL1 = 0x809c, // 10 000 0001 0011 100 00723 DBGPRCR_EL1 = 0x80a4, // 10 000 0001 0100 100 00724 DBGCLAIMSET_EL1 = 0x83c6, // 10 000 0111 1000 110 00725 DBGCLAIMCLR_EL1 = 0x83ce, // 10 000 0111 1001 110 00726 CSSELR_EL1 = 0xd000, // 11 010 0000 0000 000 00727 VPIDR_EL2 = 0xe000, // 11 100 0000 0000 000 00728 VMPIDR_EL2 = 0xe005, // 11 100 0000 0000 101 00729 CPACR_EL1 = 0xc082, // 11 000 0001 0000 010 00730 SCTLR_EL1 = 0xc080, // 11 000 0001 0000 000 00731 SCTLR_EL2 = 0xe080, // 11 100 0001 0000 000 00732 SCTLR_EL3 = 0xf080, // 11 110 0001 0000 000 00733 ACTLR_EL1 = 0xc081, // 11 000 0001 0000 001 00734 ACTLR_EL2 = 0xe081, // 11 100 0001 0000 001 00735 ACTLR_EL3 = 0xf081, // 11 110 0001 0000 001 00736 HCR_EL2 = 0xe088, // 11 100 0001 0001 000 00737 SCR_EL3 = 0xf088, // 11 110 0001 0001 000 00738 MDCR_EL2 = 0xe089, // 11 100 0001 0001 001 00739 SDER32_EL3 = 0xf089, // 11 110 0001 0001 001 00740 CPTR_EL2 = 0xe08a, // 11 100 0001 0001 010 00741 CPTR_EL3 = 0xf08a, // 11 110 0001 0001 010 00742 HSTR_EL2 = 0xe08b, // 11 100 0001 0001 011 00743 HACR_EL2 = 0xe08f, // 11 100 0001 0001 111 00744 MDCR_EL3 = 0xf099, // 11 110 0001 0011 001 00745 TTBR0_EL1 = 0xc100, // 11 000 0010 0000 000 00746 TTBR0_EL2 = 0xe100, // 11 100 0010 0000 000 00747 TTBR0_EL3 = 0xf100, // 11 110 0010 0000 000 00748 TTBR1_EL1 = 0xc101, // 11 000 0010 0000 001 00749 TCR_EL1 = 0xc102, // 11 000 0010 0000 010 00750 TCR_EL2 = 0xe102, // 11 100 0010 0000 010 00751 TCR_EL3 = 0xf102, // 11 110 0010 0000 010 00752 VTTBR_EL2 = 0xe108, // 11 100 0010 0001 000 00753 VTCR_EL2 = 0xe10a, // 11 100 0010 0001 010 00754 DACR32_EL2 = 0xe180, // 11 100 0011 0000 000 00755 SPSR_EL1 = 0xc200, // 11 000 0100 0000 000 00756 SPSR_EL2 = 0xe200, // 11 100 0100 0000 000 00757 SPSR_EL3 = 0xf200, // 11 110 0100 0000 000 00758 ELR_EL1 = 0xc201, // 11 000 0100 0000 001 00759 ELR_EL2 = 0xe201, // 11 100 0100 0000 001 00760 ELR_EL3 = 0xf201, // 11 110 0100 0000 001 00761 SP_EL0 = 0xc208, // 11 000 0100 0001 000 00762 SP_EL1 = 0xe208, // 11 100 0100 0001 000 00763 SP_EL2 = 0xf208, // 11 110 0100 0001 000 00764 SPSel = 0xc210, // 11 000 0100 0010 000 00765 NZCV = 0xda10, // 11 011 0100 0010 000 00766 DAIF = 0xda11, // 11 011 0100 0010 001 00767 CurrentEL = 0xc212, // 11 000 0100 0010 010 00768 SPSR_irq = 0xe218, // 11 100 0100 0011 000 00769 SPSR_abt = 0xe219, // 11 100 0100 0011 001 00770 SPSR_und = 0xe21a, // 11 100 0100 0011 010 00771 SPSR_fiq = 0xe21b, // 11 100 0100 0011 011 00772 FPCR = 0xda20, // 11 011 0100 0100 000 00773 FPSR = 0xda21, // 11 011 0100 0100 001 00774 DSPSR_EL0 = 0xda28, // 11 011 0100 0101 000 00775 DLR_EL0 = 0xda29, // 11 011 0100 0101 001 00776 IFSR32_EL2 = 0xe281, // 11 100 0101 0000 001 00777 AFSR0_EL1 = 0xc288, // 11 000 0101 0001 000 00778 AFSR0_EL2 = 0xe288, // 11 100 0101 0001 000 00779 AFSR0_EL3 = 0xf288, // 11 110 0101 0001 000 00780 AFSR1_EL1 = 0xc289, // 11 000 0101 0001 001 00781 AFSR1_EL2 = 0xe289, // 11 100 0101 0001 001 00782 AFSR1_EL3 = 0xf289, // 11 110 0101 0001 001 00783 ESR_EL1 = 0xc290, // 11 000 0101 0010 000 00784 ESR_EL2 = 0xe290, // 11 100 0101 0010 000 00785 ESR_EL3 = 0xf290, // 11 110 0101 0010 000 00786 FPEXC32_EL2 = 0xe298, // 11 100 0101 0011 000 00787 FAR_EL1 = 0xc300, // 11 000 0110 0000 000 00788 FAR_EL2 = 0xe300, // 11 100 0110 0000 000 00789 FAR_EL3 = 0xf300, // 11 110 0110 0000 000 00790 HPFAR_EL2 = 0xe304, // 11 100 0110 0000 100 00791 PAR_EL1 = 0xc3a0, // 11 000 0111 0100 000 00792 PMCR_EL0 = 0xdce0, // 11 011 1001 1100 000 00793 PMCNTENSET_EL0 = 0xdce1, // 11 011 1001 1100 001 00794 PMCNTENCLR_EL0 = 0xdce2, // 11 011 1001 1100 010 00795 PMOVSCLR_EL0 = 0xdce3, // 11 011 1001 1100 011 00796 PMSELR_EL0 = 0xdce5, // 11 011 1001 1100 101 00797 PMCCNTR_EL0 = 0xdce8, // 11 011 1001 1101 000 00798 PMXEVTYPER_EL0 = 0xdce9, // 11 011 1001 1101 001 00799 PMXEVCNTR_EL0 = 0xdcea, // 11 011 1001 1101 010 00800 PMUSERENR_EL0 = 0xdcf0, // 11 011 1001 1110 000 00801 PMINTENSET_EL1 = 0xc4f1, // 11 000 1001 1110 001 00802 PMINTENCLR_EL1 = 0xc4f2, // 11 000 1001 1110 010 00803 PMOVSSET_EL0 = 0xdcf3, // 11 011 1001 1110 011 00804 MAIR_EL1 = 0xc510, // 11 000 1010 0010 000 00805 MAIR_EL2 = 0xe510, // 11 100 1010 0010 000 00806 MAIR_EL3 = 0xf510, // 11 110 1010 0010 000 00807 AMAIR_EL1 = 0xc518, // 11 000 1010 0011 000 00808 AMAIR_EL2 = 0xe518, // 11 100 1010 0011 000 00809 AMAIR_EL3 = 0xf518, // 11 110 1010 0011 000 00810 VBAR_EL1 = 0xc600, // 11 000 1100 0000 000 00811 VBAR_EL2 = 0xe600, // 11 100 1100 0000 000 00812 VBAR_EL3 = 0xf600, // 11 110 1100 0000 000 00813 RMR_EL1 = 0xc602, // 11 000 1100 0000 010 00814 RMR_EL2 = 0xe602, // 11 100 1100 0000 010 00815 RMR_EL3 = 0xf602, // 11 110 1100 0000 010 00816 CONTEXTIDR_EL1 = 0xc681, // 11 000 1101 0000 001 00817 TPIDR_EL0 = 0xde82, // 11 011 1101 0000 010 00818 TPIDR_EL2 = 0xe682, // 11 100 1101 0000 010 00819 TPIDR_EL3 = 0xf682, // 11 110 1101 0000 010 00820 TPIDRRO_EL0 = 0xde83, // 11 011 1101 0000 011 00821 TPIDR_EL1 = 0xc684, // 11 000 1101 0000 100 00822 CNTFRQ_EL0 = 0xdf00, // 11 011 1110 0000 000 00823 CNTVOFF_EL2 = 0xe703, // 11 100 1110 0000 011 00824 CNTKCTL_EL1 = 0xc708, // 11 000 1110 0001 000 00825 CNTHCTL_EL2 = 0xe708, // 11 100 1110 0001 000 00826 CNTP_TVAL_EL0 = 0xdf10, // 11 011 1110 0010 000 00827 CNTHP_TVAL_EL2 = 0xe710, // 11 100 1110 0010 000 00828 CNTPS_TVAL_EL1 = 0xff10, // 11 111 1110 0010 000 00829 CNTP_CTL_EL0 = 0xdf11, // 11 011 1110 0010 001 00830 CNTHP_CTL_EL2 = 0xe711, // 11 100 1110 0010 001 00831 CNTPS_CTL_EL1 = 0xff11, // 11 111 1110 0010 001 00832 CNTP_CVAL_EL0 = 0xdf12, // 11 011 1110 0010 010 00833 CNTHP_CVAL_EL2 = 0xe712, // 11 100 1110 0010 010 00834 CNTPS_CVAL_EL1 = 0xff12, // 11 111 1110 0010 010 00835 CNTV_TVAL_EL0 = 0xdf18, // 11 011 1110 0011 000 00836 CNTV_CTL_EL0 = 0xdf19, // 11 011 1110 0011 001 00837 CNTV_CVAL_EL0 = 0xdf1a, // 11 011 1110 0011 010 00838 PMEVCNTR0_EL0 = 0xdf40, // 11 011 1110 1000 000 00839 PMEVCNTR1_EL0 = 0xdf41, // 11 011 1110 1000 001 00840 PMEVCNTR2_EL0 = 0xdf42, // 11 011 1110 1000 010 00841 PMEVCNTR3_EL0 = 0xdf43, // 11 011 1110 1000 011 00842 PMEVCNTR4_EL0 = 0xdf44, // 11 011 1110 1000 100 00843 PMEVCNTR5_EL0 = 0xdf45, // 11 011 1110 1000 101 00844 PMEVCNTR6_EL0 = 0xdf46, // 11 011 1110 1000 110 00845 PMEVCNTR7_EL0 = 0xdf47, // 11 011 1110 1000 111 00846 PMEVCNTR8_EL0 = 0xdf48, // 11 011 1110 1001 000 00847 PMEVCNTR9_EL0 = 0xdf49, // 11 011 1110 1001 001 00848 PMEVCNTR10_EL0 = 0xdf4a, // 11 011 1110 1001 010 00849 PMEVCNTR11_EL0 = 0xdf4b, // 11 011 1110 1001 011 00850 PMEVCNTR12_EL0 = 0xdf4c, // 11 011 1110 1001 100 00851 PMEVCNTR13_EL0 = 0xdf4d, // 11 011 1110 1001 101 00852 PMEVCNTR14_EL0 = 0xdf4e, // 11 011 1110 1001 110 00853 PMEVCNTR15_EL0 = 0xdf4f, // 11 011 1110 1001 111 00854 PMEVCNTR16_EL0 = 0xdf50, // 11 011 1110 1010 000 00855 PMEVCNTR17_EL0 = 0xdf51, // 11 011 1110 1010 001 00856 PMEVCNTR18_EL0 = 0xdf52, // 11 011 1110 1010 010 00857 PMEVCNTR19_EL0 = 0xdf53, // 11 011 1110 1010 011 00858 PMEVCNTR20_EL0 = 0xdf54, // 11 011 1110 1010 100 00859 PMEVCNTR21_EL0 = 0xdf55, // 11 011 1110 1010 101 00860 PMEVCNTR22_EL0 = 0xdf56, // 11 011 1110 1010 110 00861 PMEVCNTR23_EL0 = 0xdf57, // 11 011 1110 1010 111 00862 PMEVCNTR24_EL0 = 0xdf58, // 11 011 1110 1011 000 00863 PMEVCNTR25_EL0 = 0xdf59, // 11 011 1110 1011 001 00864 PMEVCNTR26_EL0 = 0xdf5a, // 11 011 1110 1011 010 00865 PMEVCNTR27_EL0 = 0xdf5b, // 11 011 1110 1011 011 00866 PMEVCNTR28_EL0 = 0xdf5c, // 11 011 1110 1011 100 00867 PMEVCNTR29_EL0 = 0xdf5d, // 11 011 1110 1011 101 00868 PMEVCNTR30_EL0 = 0xdf5e, // 11 011 1110 1011 110 00869 PMCCFILTR_EL0 = 0xdf7f, // 11 011 1110 1111 111 00870 PMEVTYPER0_EL0 = 0xdf60, // 11 011 1110 1100 000 00871 PMEVTYPER1_EL0 = 0xdf61, // 11 011 1110 1100 001 00872 PMEVTYPER2_EL0 = 0xdf62, // 11 011 1110 1100 010 00873 PMEVTYPER3_EL0 = 0xdf63, // 11 011 1110 1100 011 00874 PMEVTYPER4_EL0 = 0xdf64, // 11 011 1110 1100 100 00875 PMEVTYPER5_EL0 = 0xdf65, // 11 011 1110 1100 101 00876 PMEVTYPER6_EL0 = 0xdf66, // 11 011 1110 1100 110 00877 PMEVTYPER7_EL0 = 0xdf67, // 11 011 1110 1100 111 00878 PMEVTYPER8_EL0 = 0xdf68, // 11 011 1110 1101 000 00879 PMEVTYPER9_EL0 = 0xdf69, // 11 011 1110 1101 001 00880 PMEVTYPER10_EL0 = 0xdf6a, // 11 011 1110 1101 010 00881 PMEVTYPER11_EL0 = 0xdf6b, // 11 011 1110 1101 011 00882 PMEVTYPER12_EL0 = 0xdf6c, // 11 011 1110 1101 100 00883 PMEVTYPER13_EL0 = 0xdf6d, // 11 011 1110 1101 101 00884 PMEVTYPER14_EL0 = 0xdf6e, // 11 011 1110 1101 110 00885 PMEVTYPER15_EL0 = 0xdf6f, // 11 011 1110 1101 111 00886 PMEVTYPER16_EL0 = 0xdf70, // 11 011 1110 1110 000 00887 PMEVTYPER17_EL0 = 0xdf71, // 11 011 1110 1110 001 00888 PMEVTYPER18_EL0 = 0xdf72, // 11 011 1110 1110 010 00889 PMEVTYPER19_EL0 = 0xdf73, // 11 011 1110 1110 011 00890 PMEVTYPER20_EL0 = 0xdf74, // 11 011 1110 1110 100 00891 PMEVTYPER21_EL0 = 0xdf75, // 11 011 1110 1110 101 00892 PMEVTYPER22_EL0 = 0xdf76, // 11 011 1110 1110 110 00893 PMEVTYPER23_EL0 = 0xdf77, // 11 011 1110 1110 111 00894 PMEVTYPER24_EL0 = 0xdf78, // 11 011 1110 1111 000 00895 PMEVTYPER25_EL0 = 0xdf79, // 11 011 1110 1111 001 00896 PMEVTYPER26_EL0 = 0xdf7a, // 11 011 1110 1111 010 00897 PMEVTYPER27_EL0 = 0xdf7b, // 11 011 1110 1111 011 00898 PMEVTYPER28_EL0 = 0xdf7c, // 11 011 1110 1111 100 00899 PMEVTYPER29_EL0 = 0xdf7d, // 11 011 1110 1111 101 00900 PMEVTYPER30_EL0 = 0xdf7e, // 11 011 1110 1111 110 00901 00902 // Trace registers 00903 TRCPRGCTLR = 0x8808, // 10 001 0000 0001 000 00904 TRCPROCSELR = 0x8810, // 10 001 0000 0010 000 00905 TRCCONFIGR = 0x8820, // 10 001 0000 0100 000 00906 TRCAUXCTLR = 0x8830, // 10 001 0000 0110 000 00907 TRCEVENTCTL0R = 0x8840, // 10 001 0000 1000 000 00908 TRCEVENTCTL1R = 0x8848, // 10 001 0000 1001 000 00909 TRCSTALLCTLR = 0x8858, // 10 001 0000 1011 000 00910 TRCTSCTLR = 0x8860, // 10 001 0000 1100 000 00911 TRCSYNCPR = 0x8868, // 10 001 0000 1101 000 00912 TRCCCCTLR = 0x8870, // 10 001 0000 1110 000 00913 TRCBBCTLR = 0x8878, // 10 001 0000 1111 000 00914 TRCTRACEIDR = 0x8801, // 10 001 0000 0000 001 00915 TRCQCTLR = 0x8809, // 10 001 0000 0001 001 00916 TRCVICTLR = 0x8802, // 10 001 0000 0000 010 00917 TRCVIIECTLR = 0x880a, // 10 001 0000 0001 010 00918 TRCVISSCTLR = 0x8812, // 10 001 0000 0010 010 00919 TRCVIPCSSCTLR = 0x881a, // 10 001 0000 0011 010 00920 TRCVDCTLR = 0x8842, // 10 001 0000 1000 010 00921 TRCVDSACCTLR = 0x884a, // 10 001 0000 1001 010 00922 TRCVDARCCTLR = 0x8852, // 10 001 0000 1010 010 00923 TRCSEQEVR0 = 0x8804, // 10 001 0000 0000 100 00924 TRCSEQEVR1 = 0x880c, // 10 001 0000 0001 100 00925 TRCSEQEVR2 = 0x8814, // 10 001 0000 0010 100 00926 TRCSEQRSTEVR = 0x8834, // 10 001 0000 0110 100 00927 TRCSEQSTR = 0x883c, // 10 001 0000 0111 100 00928 TRCEXTINSELR = 0x8844, // 10 001 0000 1000 100 00929 TRCCNTRLDVR0 = 0x8805, // 10 001 0000 0000 101 00930 TRCCNTRLDVR1 = 0x880d, // 10 001 0000 0001 101 00931 TRCCNTRLDVR2 = 0x8815, // 10 001 0000 0010 101 00932 TRCCNTRLDVR3 = 0x881d, // 10 001 0000 0011 101 00933 TRCCNTCTLR0 = 0x8825, // 10 001 0000 0100 101 00934 TRCCNTCTLR1 = 0x882d, // 10 001 0000 0101 101 00935 TRCCNTCTLR2 = 0x8835, // 10 001 0000 0110 101 00936 TRCCNTCTLR3 = 0x883d, // 10 001 0000 0111 101 00937 TRCCNTVR0 = 0x8845, // 10 001 0000 1000 101 00938 TRCCNTVR1 = 0x884d, // 10 001 0000 1001 101 00939 TRCCNTVR2 = 0x8855, // 10 001 0000 1010 101 00940 TRCCNTVR3 = 0x885d, // 10 001 0000 1011 101 00941 TRCIMSPEC0 = 0x8807, // 10 001 0000 0000 111 00942 TRCIMSPEC1 = 0x880f, // 10 001 0000 0001 111 00943 TRCIMSPEC2 = 0x8817, // 10 001 0000 0010 111 00944 TRCIMSPEC3 = 0x881f, // 10 001 0000 0011 111 00945 TRCIMSPEC4 = 0x8827, // 10 001 0000 0100 111 00946 TRCIMSPEC5 = 0x882f, // 10 001 0000 0101 111 00947 TRCIMSPEC6 = 0x8837, // 10 001 0000 0110 111 00948 TRCIMSPEC7 = 0x883f, // 10 001 0000 0111 111 00949 TRCRSCTLR2 = 0x8890, // 10 001 0001 0010 000 00950 TRCRSCTLR3 = 0x8898, // 10 001 0001 0011 000 00951 TRCRSCTLR4 = 0x88a0, // 10 001 0001 0100 000 00952 TRCRSCTLR5 = 0x88a8, // 10 001 0001 0101 000 00953 TRCRSCTLR6 = 0x88b0, // 10 001 0001 0110 000 00954 TRCRSCTLR7 = 0x88b8, // 10 001 0001 0111 000 00955 TRCRSCTLR8 = 0x88c0, // 10 001 0001 1000 000 00956 TRCRSCTLR9 = 0x88c8, // 10 001 0001 1001 000 00957 TRCRSCTLR10 = 0x88d0, // 10 001 0001 1010 000 00958 TRCRSCTLR11 = 0x88d8, // 10 001 0001 1011 000 00959 TRCRSCTLR12 = 0x88e0, // 10 001 0001 1100 000 00960 TRCRSCTLR13 = 0x88e8, // 10 001 0001 1101 000 00961 TRCRSCTLR14 = 0x88f0, // 10 001 0001 1110 000 00962 TRCRSCTLR15 = 0x88f8, // 10 001 0001 1111 000 00963 TRCRSCTLR16 = 0x8881, // 10 001 0001 0000 001 00964 TRCRSCTLR17 = 0x8889, // 10 001 0001 0001 001 00965 TRCRSCTLR18 = 0x8891, // 10 001 0001 0010 001 00966 TRCRSCTLR19 = 0x8899, // 10 001 0001 0011 001 00967 TRCRSCTLR20 = 0x88a1, // 10 001 0001 0100 001 00968 TRCRSCTLR21 = 0x88a9, // 10 001 0001 0101 001 00969 TRCRSCTLR22 = 0x88b1, // 10 001 0001 0110 001 00970 TRCRSCTLR23 = 0x88b9, // 10 001 0001 0111 001 00971 TRCRSCTLR24 = 0x88c1, // 10 001 0001 1000 001 00972 TRCRSCTLR25 = 0x88c9, // 10 001 0001 1001 001 00973 TRCRSCTLR26 = 0x88d1, // 10 001 0001 1010 001 00974 TRCRSCTLR27 = 0x88d9, // 10 001 0001 1011 001 00975 TRCRSCTLR28 = 0x88e1, // 10 001 0001 1100 001 00976 TRCRSCTLR29 = 0x88e9, // 10 001 0001 1101 001 00977 TRCRSCTLR30 = 0x88f1, // 10 001 0001 1110 001 00978 TRCRSCTLR31 = 0x88f9, // 10 001 0001 1111 001 00979 TRCSSCCR0 = 0x8882, // 10 001 0001 0000 010 00980 TRCSSCCR1 = 0x888a, // 10 001 0001 0001 010 00981 TRCSSCCR2 = 0x8892, // 10 001 0001 0010 010 00982 TRCSSCCR3 = 0x889a, // 10 001 0001 0011 010 00983 TRCSSCCR4 = 0x88a2, // 10 001 0001 0100 010 00984 TRCSSCCR5 = 0x88aa, // 10 001 0001 0101 010 00985 TRCSSCCR6 = 0x88b2, // 10 001 0001 0110 010 00986 TRCSSCCR7 = 0x88ba, // 10 001 0001 0111 010 00987 TRCSSCSR0 = 0x88c2, // 10 001 0001 1000 010 00988 TRCSSCSR1 = 0x88ca, // 10 001 0001 1001 010 00989 TRCSSCSR2 = 0x88d2, // 10 001 0001 1010 010 00990 TRCSSCSR3 = 0x88da, // 10 001 0001 1011 010 00991 TRCSSCSR4 = 0x88e2, // 10 001 0001 1100 010 00992 TRCSSCSR5 = 0x88ea, // 10 001 0001 1101 010 00993 TRCSSCSR6 = 0x88f2, // 10 001 0001 1110 010 00994 TRCSSCSR7 = 0x88fa, // 10 001 0001 1111 010 00995 TRCSSPCICR0 = 0x8883, // 10 001 0001 0000 011 00996 TRCSSPCICR1 = 0x888b, // 10 001 0001 0001 011 00997 TRCSSPCICR2 = 0x8893, // 10 001 0001 0010 011 00998 TRCSSPCICR3 = 0x889b, // 10 001 0001 0011 011 00999 TRCSSPCICR4 = 0x88a3, // 10 001 0001 0100 011 01000 TRCSSPCICR5 = 0x88ab, // 10 001 0001 0101 011 01001 TRCSSPCICR6 = 0x88b3, // 10 001 0001 0110 011 01002 TRCSSPCICR7 = 0x88bb, // 10 001 0001 0111 011 01003 TRCPDCR = 0x88a4, // 10 001 0001 0100 100 01004 TRCACVR0 = 0x8900, // 10 001 0010 0000 000 01005 TRCACVR1 = 0x8910, // 10 001 0010 0010 000 01006 TRCACVR2 = 0x8920, // 10 001 0010 0100 000 01007 TRCACVR3 = 0x8930, // 10 001 0010 0110 000 01008 TRCACVR4 = 0x8940, // 10 001 0010 1000 000 01009 TRCACVR5 = 0x8950, // 10 001 0010 1010 000 01010 TRCACVR6 = 0x8960, // 10 001 0010 1100 000 01011 TRCACVR7 = 0x8970, // 10 001 0010 1110 000 01012 TRCACVR8 = 0x8901, // 10 001 0010 0000 001 01013 TRCACVR9 = 0x8911, // 10 001 0010 0010 001 01014 TRCACVR10 = 0x8921, // 10 001 0010 0100 001 01015 TRCACVR11 = 0x8931, // 10 001 0010 0110 001 01016 TRCACVR12 = 0x8941, // 10 001 0010 1000 001 01017 TRCACVR13 = 0x8951, // 10 001 0010 1010 001 01018 TRCACVR14 = 0x8961, // 10 001 0010 1100 001 01019 TRCACVR15 = 0x8971, // 10 001 0010 1110 001 01020 TRCACATR0 = 0x8902, // 10 001 0010 0000 010 01021 TRCACATR1 = 0x8912, // 10 001 0010 0010 010 01022 TRCACATR2 = 0x8922, // 10 001 0010 0100 010 01023 TRCACATR3 = 0x8932, // 10 001 0010 0110 010 01024 TRCACATR4 = 0x8942, // 10 001 0010 1000 010 01025 TRCACATR5 = 0x8952, // 10 001 0010 1010 010 01026 TRCACATR6 = 0x8962, // 10 001 0010 1100 010 01027 TRCACATR7 = 0x8972, // 10 001 0010 1110 010 01028 TRCACATR8 = 0x8903, // 10 001 0010 0000 011 01029 TRCACATR9 = 0x8913, // 10 001 0010 0010 011 01030 TRCACATR10 = 0x8923, // 10 001 0010 0100 011 01031 TRCACATR11 = 0x8933, // 10 001 0010 0110 011 01032 TRCACATR12 = 0x8943, // 10 001 0010 1000 011 01033 TRCACATR13 = 0x8953, // 10 001 0010 1010 011 01034 TRCACATR14 = 0x8963, // 10 001 0010 1100 011 01035 TRCACATR15 = 0x8973, // 10 001 0010 1110 011 01036 TRCDVCVR0 = 0x8904, // 10 001 0010 0000 100 01037 TRCDVCVR1 = 0x8924, // 10 001 0010 0100 100 01038 TRCDVCVR2 = 0x8944, // 10 001 0010 1000 100 01039 TRCDVCVR3 = 0x8964, // 10 001 0010 1100 100 01040 TRCDVCVR4 = 0x8905, // 10 001 0010 0000 101 01041 TRCDVCVR5 = 0x8925, // 10 001 0010 0100 101 01042 TRCDVCVR6 = 0x8945, // 10 001 0010 1000 101 01043 TRCDVCVR7 = 0x8965, // 10 001 0010 1100 101 01044 TRCDVCMR0 = 0x8906, // 10 001 0010 0000 110 01045 TRCDVCMR1 = 0x8926, // 10 001 0010 0100 110 01046 TRCDVCMR2 = 0x8946, // 10 001 0010 1000 110 01047 TRCDVCMR3 = 0x8966, // 10 001 0010 1100 110 01048 TRCDVCMR4 = 0x8907, // 10 001 0010 0000 111 01049 TRCDVCMR5 = 0x8927, // 10 001 0010 0100 111 01050 TRCDVCMR6 = 0x8947, // 10 001 0010 1000 111 01051 TRCDVCMR7 = 0x8967, // 10 001 0010 1100 111 01052 TRCCIDCVR0 = 0x8980, // 10 001 0011 0000 000 01053 TRCCIDCVR1 = 0x8990, // 10 001 0011 0010 000 01054 TRCCIDCVR2 = 0x89a0, // 10 001 0011 0100 000 01055 TRCCIDCVR3 = 0x89b0, // 10 001 0011 0110 000 01056 TRCCIDCVR4 = 0x89c0, // 10 001 0011 1000 000 01057 TRCCIDCVR5 = 0x89d0, // 10 001 0011 1010 000 01058 TRCCIDCVR6 = 0x89e0, // 10 001 0011 1100 000 01059 TRCCIDCVR7 = 0x89f0, // 10 001 0011 1110 000 01060 TRCVMIDCVR0 = 0x8981, // 10 001 0011 0000 001 01061 TRCVMIDCVR1 = 0x8991, // 10 001 0011 0010 001 01062 TRCVMIDCVR2 = 0x89a1, // 10 001 0011 0100 001 01063 TRCVMIDCVR3 = 0x89b1, // 10 001 0011 0110 001 01064 TRCVMIDCVR4 = 0x89c1, // 10 001 0011 1000 001 01065 TRCVMIDCVR5 = 0x89d1, // 10 001 0011 1010 001 01066 TRCVMIDCVR6 = 0x89e1, // 10 001 0011 1100 001 01067 TRCVMIDCVR7 = 0x89f1, // 10 001 0011 1110 001 01068 TRCCIDCCTLR0 = 0x8982, // 10 001 0011 0000 010 01069 TRCCIDCCTLR1 = 0x898a, // 10 001 0011 0001 010 01070 TRCVMIDCCTLR0 = 0x8992, // 10 001 0011 0010 010 01071 TRCVMIDCCTLR1 = 0x899a, // 10 001 0011 0011 010 01072 TRCITCTRL = 0x8b84, // 10 001 0111 0000 100 01073 TRCCLAIMSET = 0x8bc6, // 10 001 0111 1000 110 01074 TRCCLAIMCLR = 0x8bce, // 10 001 0111 1001 110 01075 01076 // GICv3 registers 01077 ICC_BPR1_EL1 = 0xc663, // 11 000 1100 1100 011 01078 ICC_BPR0_EL1 = 0xc643, // 11 000 1100 1000 011 01079 ICC_PMR_EL1 = 0xc230, // 11 000 0100 0110 000 01080 ICC_CTLR_EL1 = 0xc664, // 11 000 1100 1100 100 01081 ICC_CTLR_EL3 = 0xf664, // 11 110 1100 1100 100 01082 ICC_SRE_EL1 = 0xc665, // 11 000 1100 1100 101 01083 ICC_SRE_EL2 = 0xe64d, // 11 100 1100 1001 101 01084 ICC_SRE_EL3 = 0xf665, // 11 110 1100 1100 101 01085 ICC_IGRPEN0_EL1 = 0xc666, // 11 000 1100 1100 110 01086 ICC_IGRPEN1_EL1 = 0xc667, // 11 000 1100 1100 111 01087 ICC_IGRPEN1_EL3 = 0xf667, // 11 110 1100 1100 111 01088 ICC_SEIEN_EL1 = 0xc668, // 11 000 1100 1101 000 01089 ICC_AP0R0_EL1 = 0xc644, // 11 000 1100 1000 100 01090 ICC_AP0R1_EL1 = 0xc645, // 11 000 1100 1000 101 01091 ICC_AP0R2_EL1 = 0xc646, // 11 000 1100 1000 110 01092 ICC_AP0R3_EL1 = 0xc647, // 11 000 1100 1000 111 01093 ICC_AP1R0_EL1 = 0xc648, // 11 000 1100 1001 000 01094 ICC_AP1R1_EL1 = 0xc649, // 11 000 1100 1001 001 01095 ICC_AP1R2_EL1 = 0xc64a, // 11 000 1100 1001 010 01096 ICC_AP1R3_EL1 = 0xc64b, // 11 000 1100 1001 011 01097 ICH_AP0R0_EL2 = 0xe640, // 11 100 1100 1000 000 01098 ICH_AP0R1_EL2 = 0xe641, // 11 100 1100 1000 001 01099 ICH_AP0R2_EL2 = 0xe642, // 11 100 1100 1000 010 01100 ICH_AP0R3_EL2 = 0xe643, // 11 100 1100 1000 011 01101 ICH_AP1R0_EL2 = 0xe648, // 11 100 1100 1001 000 01102 ICH_AP1R1_EL2 = 0xe649, // 11 100 1100 1001 001 01103 ICH_AP1R2_EL2 = 0xe64a, // 11 100 1100 1001 010 01104 ICH_AP1R3_EL2 = 0xe64b, // 11 100 1100 1001 011 01105 ICH_HCR_EL2 = 0xe658, // 11 100 1100 1011 000 01106 ICH_MISR_EL2 = 0xe65a, // 11 100 1100 1011 010 01107 ICH_VMCR_EL2 = 0xe65f, // 11 100 1100 1011 111 01108 ICH_VSEIR_EL2 = 0xe64c, // 11 100 1100 1001 100 01109 ICH_LR0_EL2 = 0xe660, // 11 100 1100 1100 000 01110 ICH_LR1_EL2 = 0xe661, // 11 100 1100 1100 001 01111 ICH_LR2_EL2 = 0xe662, // 11 100 1100 1100 010 01112 ICH_LR3_EL2 = 0xe663, // 11 100 1100 1100 011 01113 ICH_LR4_EL2 = 0xe664, // 11 100 1100 1100 100 01114 ICH_LR5_EL2 = 0xe665, // 11 100 1100 1100 101 01115 ICH_LR6_EL2 = 0xe666, // 11 100 1100 1100 110 01116 ICH_LR7_EL2 = 0xe667, // 11 100 1100 1100 111 01117 ICH_LR8_EL2 = 0xe668, // 11 100 1100 1101 000 01118 ICH_LR9_EL2 = 0xe669, // 11 100 1100 1101 001 01119 ICH_LR10_EL2 = 0xe66a, // 11 100 1100 1101 010 01120 ICH_LR11_EL2 = 0xe66b, // 11 100 1100 1101 011 01121 ICH_LR12_EL2 = 0xe66c, // 11 100 1100 1101 100 01122 ICH_LR13_EL2 = 0xe66d, // 11 100 1100 1101 101 01123 ICH_LR14_EL2 = 0xe66e, // 11 100 1100 1101 110 01124 ICH_LR15_EL2 = 0xe66f, // 11 100 1100 1101 111 01125 }; 01126 01127 // Cyclone specific system registers 01128 enum CycloneSysRegValues { 01129 CPM_IOACC_CTL_EL3 = 0xff90 01130 }; 01131 01132 // Note that these do not inherit from AArch64NamedImmMapper. This class is 01133 // sufficiently different in its behaviour that I don't believe it's worth 01134 // burdening the common AArch64NamedImmMapper with abstractions only needed in 01135 // this one case. 01136 struct SysRegMapper { 01137 static const AArch64NamedImmMapper::Mapping SysRegPairs[]; 01138 static const AArch64NamedImmMapper::Mapping CycloneSysRegPairs[]; 01139 01140 const AArch64NamedImmMapper::Mapping *InstPairs; 01141 size_t NumInstPairs; 01142 uint64_t FeatureBits; 01143 01144 SysRegMapper(uint64_t FeatureBits) : FeatureBits(FeatureBits) { } 01145 uint32_t fromString(StringRef Name, bool &Valid) const; 01146 std::string toString(uint32_t Bits, bool &Valid) const; 01147 }; 01148 01149 struct MSRMapper : SysRegMapper { 01150 static const AArch64NamedImmMapper::Mapping MSRPairs[]; 01151 MSRMapper(uint64_t FeatureBits); 01152 }; 01153 01154 struct MRSMapper : SysRegMapper { 01155 static const AArch64NamedImmMapper::Mapping MRSPairs[]; 01156 MRSMapper(uint64_t FeatureBits); 01157 }; 01158 01159 uint32_t ParseGenericRegister(StringRef Name, bool &Valid); 01160 } 01161 01162 namespace AArch64TLBI { 01163 enum TLBIValues { 01164 Invalid = -1, // Op0 Op1 CRn CRm Op2 01165 IPAS2E1IS = 0x6401, // 01 100 1000 0000 001 01166 IPAS2LE1IS = 0x6405, // 01 100 1000 0000 101 01167 VMALLE1IS = 0x4418, // 01 000 1000 0011 000 01168 ALLE2IS = 0x6418, // 01 100 1000 0011 000 01169 ALLE3IS = 0x7418, // 01 110 1000 0011 000 01170 VAE1IS = 0x4419, // 01 000 1000 0011 001 01171 VAE2IS = 0x6419, // 01 100 1000 0011 001 01172 VAE3IS = 0x7419, // 01 110 1000 0011 001 01173 ASIDE1IS = 0x441a, // 01 000 1000 0011 010 01174 VAAE1IS = 0x441b, // 01 000 1000 0011 011 01175 ALLE1IS = 0x641c, // 01 100 1000 0011 100 01176 VALE1IS = 0x441d, // 01 000 1000 0011 101 01177 VALE2IS = 0x641d, // 01 100 1000 0011 101 01178 VALE3IS = 0x741d, // 01 110 1000 0011 101 01179 VMALLS12E1IS = 0x641e, // 01 100 1000 0011 110 01180 VAALE1IS = 0x441f, // 01 000 1000 0011 111 01181 IPAS2E1 = 0x6421, // 01 100 1000 0100 001 01182 IPAS2LE1 = 0x6425, // 01 100 1000 0100 101 01183 VMALLE1 = 0x4438, // 01 000 1000 0111 000 01184 ALLE2 = 0x6438, // 01 100 1000 0111 000 01185 ALLE3 = 0x7438, // 01 110 1000 0111 000 01186 VAE1 = 0x4439, // 01 000 1000 0111 001 01187 VAE2 = 0x6439, // 01 100 1000 0111 001 01188 VAE3 = 0x7439, // 01 110 1000 0111 001 01189 ASIDE1 = 0x443a, // 01 000 1000 0111 010 01190 VAAE1 = 0x443b, // 01 000 1000 0111 011 01191 ALLE1 = 0x643c, // 01 100 1000 0111 100 01192 VALE1 = 0x443d, // 01 000 1000 0111 101 01193 VALE2 = 0x643d, // 01 100 1000 0111 101 01194 VALE3 = 0x743d, // 01 110 1000 0111 101 01195 VMALLS12E1 = 0x643e, // 01 100 1000 0111 110 01196 VAALE1 = 0x443f // 01 000 1000 0111 111 01197 }; 01198 01199 struct TLBIMapper : AArch64NamedImmMapper { 01200 const static Mapping TLBIPairs[]; 01201 01202 TLBIMapper(); 01203 }; 01204 01205 static inline bool NeedsRegister(TLBIValues Val) { 01206 switch (Val) { 01207 case VMALLE1IS: 01208 case ALLE2IS: 01209 case ALLE3IS: 01210 case ALLE1IS: 01211 case VMALLS12E1IS: 01212 case VMALLE1: 01213 case ALLE2: 01214 case ALLE3: 01215 case ALLE1: 01216 case VMALLS12E1: 01217 return false; 01218 default: 01219 return true; 01220 } 01221 } 01222 } 01223 01224 namespace AArch64II { 01225 /// Target Operand Flag enum. 01226 enum TOF { 01227 //===------------------------------------------------------------------===// 01228 // AArch64 Specific MachineOperand flags. 01229 01230 MO_NO_FLAG, 01231 01232 MO_FRAGMENT = 0x7, 01233 01234 /// MO_PAGE - A symbol operand with this flag represents the pc-relative 01235 /// offset of the 4K page containing the symbol. This is used with the 01236 /// ADRP instruction. 01237 MO_PAGE = 1, 01238 01239 /// MO_PAGEOFF - A symbol operand with this flag represents the offset of 01240 /// that symbol within a 4K page. This offset is added to the page address 01241 /// to produce the complete address. 01242 MO_PAGEOFF = 2, 01243 01244 /// MO_G3 - A symbol operand with this flag (granule 3) represents the high 01245 /// 16-bits of a 64-bit address, used in a MOVZ or MOVK instruction 01246 MO_G3 = 3, 01247 01248 /// MO_G2 - A symbol operand with this flag (granule 2) represents the bits 01249 /// 32-47 of a 64-bit address, used in a MOVZ or MOVK instruction 01250 MO_G2 = 4, 01251 01252 /// MO_G1 - A symbol operand with this flag (granule 1) represents the bits 01253 /// 16-31 of a 64-bit address, used in a MOVZ or MOVK instruction 01254 MO_G1 = 5, 01255 01256 /// MO_G0 - A symbol operand with this flag (granule 0) represents the bits 01257 /// 0-15 of a 64-bit address, used in a MOVZ or MOVK instruction 01258 MO_G0 = 6, 01259 01260 /// MO_GOT - This flag indicates that a symbol operand represents the 01261 /// address of the GOT entry for the symbol, rather than the address of 01262 /// the symbol itself. 01263 MO_GOT = 8, 01264 01265 /// MO_NC - Indicates whether the linker is expected to check the symbol 01266 /// reference for overflow. For example in an ADRP/ADD pair of relocations 01267 /// the ADRP usually does check, but not the ADD. 01268 MO_NC = 0x10, 01269 01270 /// MO_TLS - Indicates that the operand being accessed is some kind of 01271 /// thread-local symbol. On Darwin, only one type of thread-local access 01272 /// exists (pre linker-relaxation), but on ELF the TLSModel used for the 01273 /// referee will affect interpretation. 01274 MO_TLS = 0x20, 01275 01276 /// MO_CONSTPOOL - This flag indicates that a symbol operand represents 01277 /// the address of a constant pool entry for the symbol, rather than the 01278 /// address of the symbol itself. 01279 MO_CONSTPOOL = 0x40 01280 }; 01281 } // end namespace AArch64II 01282 01283 } // end namespace llvm 01284 01285 #endif
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