LLVM API Documentation
00001 //===-- PowerPCSubtarget.cpp - PPC Subtarget Information ------------------===// 00002 // 00003 // The LLVM Compiler Infrastructure 00004 // 00005 // This file is distributed under the University of Illinois Open Source 00006 // License. See LICENSE.TXT for details. 00007 // 00008 //===----------------------------------------------------------------------===// 00009 // 00010 // This file implements the PPC specific subclass of TargetSubtargetInfo. 00011 // 00012 //===----------------------------------------------------------------------===// 00013 00014 #include "PPCSubtarget.h" 00015 #include "PPC.h" 00016 #include "PPCRegisterInfo.h" 00017 #include "llvm/CodeGen/MachineFunction.h" 00018 #include "llvm/CodeGen/MachineScheduler.h" 00019 #include "llvm/IR/Attributes.h" 00020 #include "llvm/IR/Function.h" 00021 #include "llvm/IR/GlobalValue.h" 00022 #include "llvm/Support/Host.h" 00023 #include "llvm/Support/TargetRegistry.h" 00024 #include "llvm/Target/TargetMachine.h" 00025 #include <cstdlib> 00026 00027 using namespace llvm; 00028 00029 #define DEBUG_TYPE "ppc-subtarget" 00030 00031 #define GET_SUBTARGETINFO_TARGET_DESC 00032 #define GET_SUBTARGETINFO_CTOR 00033 #include "PPCGenSubtargetInfo.inc" 00034 00035 /// Return the datalayout string of a subtarget. 00036 static std::string getDataLayoutString(const Triple &T) { 00037 bool is64Bit = T.getArch() == Triple::ppc64 || T.getArch() == Triple::ppc64le; 00038 std::string Ret; 00039 00040 // Most PPC* platforms are big endian, PPC64LE is little endian. 00041 if (T.getArch() == Triple::ppc64le) 00042 Ret = "e"; 00043 else 00044 Ret = "E"; 00045 00046 Ret += DataLayout::getManglingComponent(T); 00047 00048 // PPC32 has 32 bit pointers. The PS3 (OS Lv2) is a PPC64 machine with 32 bit 00049 // pointers. 00050 if (!is64Bit || T.getOS() == Triple::Lv2) 00051 Ret += "-p:32:32"; 00052 00053 // Note, the alignment values for f64 and i64 on ppc64 in Darwin 00054 // documentation are wrong; these are correct (i.e. "what gcc does"). 00055 if (is64Bit || !T.isOSDarwin()) 00056 Ret += "-i64:64"; 00057 else 00058 Ret += "-f64:32:64"; 00059 00060 // PPC64 has 32 and 64 bit registers, PPC32 has only 32 bit ones. 00061 if (is64Bit) 00062 Ret += "-n32:64"; 00063 else 00064 Ret += "-n32"; 00065 00066 return Ret; 00067 } 00068 00069 PPCSubtarget &PPCSubtarget::initializeSubtargetDependencies(StringRef CPU, 00070 StringRef FS) { 00071 initializeEnvironment(); 00072 initSubtargetFeatures(CPU, FS); 00073 return *this; 00074 } 00075 00076 PPCSubtarget::PPCSubtarget(const std::string &TT, const std::string &CPU, 00077 const std::string &FS, PPCTargetMachine &TM, 00078 CodeGenOpt::Level OptLevel) 00079 : PPCGenSubtargetInfo(TT, CPU, FS), TargetTriple(TT), 00080 DL(getDataLayoutString(TargetTriple)), 00081 IsPPC64(TargetTriple.getArch() == Triple::ppc64 || 00082 TargetTriple.getArch() == Triple::ppc64le), 00083 OptLevel(OptLevel), TargetABI(PPC_ABI_UNKNOWN), 00084 FrameLowering(initializeSubtargetDependencies(CPU, FS)), InstrInfo(*this), 00085 TLInfo(TM), TSInfo(&DL) {} 00086 00087 void PPCSubtarget::initializeEnvironment() { 00088 StackAlignment = 16; 00089 DarwinDirective = PPC::DIR_NONE; 00090 HasMFOCRF = false; 00091 Has64BitSupport = false; 00092 Use64BitRegs = false; 00093 UseCRBits = false; 00094 HasAltivec = false; 00095 HasSPE = false; 00096 HasQPX = false; 00097 HasVSX = false; 00098 HasFCPSGN = false; 00099 HasFSQRT = false; 00100 HasFRE = false; 00101 HasFRES = false; 00102 HasFRSQRTE = false; 00103 HasFRSQRTES = false; 00104 HasRecipPrec = false; 00105 HasSTFIWX = false; 00106 HasLFIWAX = false; 00107 HasFPRND = false; 00108 HasFPCVT = false; 00109 HasISEL = false; 00110 HasPOPCNTD = false; 00111 HasLDBRX = false; 00112 IsBookE = false; 00113 IsPPC4xx = false; 00114 IsPPC6xx = false; 00115 IsE500 = false; 00116 DeprecatedMFTB = false; 00117 DeprecatedDST = false; 00118 HasLazyResolverStubs = false; 00119 } 00120 00121 void PPCSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) { 00122 // Determine default and user specified characteristics 00123 std::string CPUName = CPU; 00124 if (CPUName.empty()) 00125 CPUName = "generic"; 00126 #if (defined(__APPLE__) || defined(__linux__)) && \ 00127 (defined(__ppc__) || defined(__powerpc__)) 00128 if (CPUName == "generic") 00129 CPUName = sys::getHostCPUName(); 00130 #endif 00131 00132 // Initialize scheduling itinerary for the specified CPU. 00133 InstrItins = getInstrItineraryForCPU(CPUName); 00134 00135 // Make sure 64-bit features are available when CPUname is generic 00136 std::string FullFS = FS; 00137 00138 // If we are generating code for ppc64, verify that options make sense. 00139 if (IsPPC64) { 00140 Has64BitSupport = true; 00141 // Silently force 64-bit register use on ppc64. 00142 Use64BitRegs = true; 00143 if (!FullFS.empty()) 00144 FullFS = "+64bit," + FullFS; 00145 else 00146 FullFS = "+64bit"; 00147 } 00148 00149 // At -O2 and above, track CR bits as individual registers. 00150 if (OptLevel >= CodeGenOpt::Default) { 00151 if (!FullFS.empty()) 00152 FullFS = "+crbits," + FullFS; 00153 else 00154 FullFS = "+crbits"; 00155 } 00156 00157 // Parse features string. 00158 ParseSubtargetFeatures(CPUName, FullFS); 00159 00160 // If the user requested use of 64-bit regs, but the cpu selected doesn't 00161 // support it, ignore. 00162 if (use64BitRegs() && !has64BitSupport()) 00163 Use64BitRegs = false; 00164 00165 // Set up darwin-specific properties. 00166 if (isDarwin()) 00167 HasLazyResolverStubs = true; 00168 00169 // QPX requires a 32-byte aligned stack. Note that we need to do this if 00170 // we're compiling for a BG/Q system regardless of whether or not QPX 00171 // is enabled because external functions will assume this alignment. 00172 if (hasQPX() || isBGQ()) 00173 StackAlignment = 32; 00174 00175 // Determine endianness. 00176 IsLittleEndian = (TargetTriple.getArch() == Triple::ppc64le); 00177 00178 // FIXME: For now, we disable VSX in little-endian mode until endian 00179 // issues in those instructions can be addressed. 00180 if (IsLittleEndian) 00181 HasVSX = false; 00182 00183 // Determine default ABI. 00184 if (TargetABI == PPC_ABI_UNKNOWN) { 00185 if (!isDarwin() && IsPPC64) { 00186 if (IsLittleEndian) 00187 TargetABI = PPC_ABI_ELFv2; 00188 else 00189 TargetABI = PPC_ABI_ELFv1; 00190 } 00191 } 00192 } 00193 00194 /// hasLazyResolverStub - Return true if accesses to the specified global have 00195 /// to go through a dyld lazy resolution stub. This means that an extra load 00196 /// is required to get the address of the global. 00197 bool PPCSubtarget::hasLazyResolverStub(const GlobalValue *GV, 00198 const TargetMachine &TM) const { 00199 // We never have stubs if HasLazyResolverStubs=false or if in static mode. 00200 if (!HasLazyResolverStubs || TM.getRelocationModel() == Reloc::Static) 00201 return false; 00202 // If symbol visibility is hidden, the extra load is not needed if 00203 // the symbol is definitely defined in the current translation unit. 00204 bool isDecl = GV->isDeclaration() && !GV->isMaterializable(); 00205 if (GV->hasHiddenVisibility() && !isDecl && !GV->hasCommonLinkage()) 00206 return false; 00207 return GV->hasWeakLinkage() || GV->hasLinkOnceLinkage() || 00208 GV->hasCommonLinkage() || isDecl; 00209 } 00210 00211 // Embedded cores need aggressive scheduling (and some others also benefit). 00212 static bool needsAggressiveScheduling(unsigned Directive) { 00213 switch (Directive) { 00214 default: return false; 00215 case PPC::DIR_440: 00216 case PPC::DIR_A2: 00217 case PPC::DIR_E500mc: 00218 case PPC::DIR_E5500: 00219 case PPC::DIR_PWR7: 00220 case PPC::DIR_PWR8: 00221 return true; 00222 } 00223 } 00224 00225 bool PPCSubtarget::enableMachineScheduler() const { 00226 // Enable MI scheduling for the embedded cores. 00227 // FIXME: Enable this for all cores (some additional modeling 00228 // may be necessary). 00229 return needsAggressiveScheduling(DarwinDirective); 00230 } 00231 00232 // This overrides the PostRAScheduler bit in the SchedModel for each CPU. 00233 bool PPCSubtarget::enablePostMachineScheduler() const { return true; } 00234 00235 PPCGenSubtargetInfo::AntiDepBreakMode PPCSubtarget::getAntiDepBreakMode() const { 00236 return TargetSubtargetInfo::ANTIDEP_ALL; 00237 } 00238 00239 void PPCSubtarget::getCriticalPathRCs(RegClassVector &CriticalPathRCs) const { 00240 CriticalPathRCs.clear(); 00241 CriticalPathRCs.push_back(isPPC64() ? 00242 &PPC::G8RCRegClass : &PPC::GPRCRegClass); 00243 } 00244 00245 void PPCSubtarget::overrideSchedPolicy(MachineSchedPolicy &Policy, 00246 MachineInstr *begin, 00247 MachineInstr *end, 00248 unsigned NumRegionInstrs) const { 00249 if (needsAggressiveScheduling(DarwinDirective)) { 00250 Policy.OnlyTopDown = false; 00251 Policy.OnlyBottomUp = false; 00252 } 00253 00254 // Spilling is generally expensive on all PPC cores, so always enable 00255 // register-pressure tracking. 00256 Policy.ShouldTrackPressure = true; 00257 } 00258 00259 bool PPCSubtarget::useAA() const { 00260 // Use AA during code generation for the embedded cores. 00261 return needsAggressiveScheduling(DarwinDirective); 00262 } 00263