llvm::TargetSubtargetInfo Class Reference

#include <TargetSubtargetInfo.h>

Inheritance diagram for llvm::TargetSubtargetInfo:

Collaboration diagram for llvm::TargetSubtargetInfo:

List of all members.

Public Types
enum	AntiDepBreakMode { ANTIDEP_NONE, ANTIDEP_CRITICAL, ANTIDEP_ALL }
typedef SmallVectorImpl< const TargetRegisterClass * >	RegClassVector
Public Member Functions
virtual	~TargetSubtargetInfo ()
virtual const TargetInstrInfo *	getInstrInfo () const
virtual const TargetFrameLowering *	getFrameLowering () const
virtual const TargetLowering *	getTargetLowering () const
virtual const TargetSelectionDAGInfo *	getSelectionDAGInfo () const
virtual const DataLayout *	getDataLayout () const
virtual const TargetRegisterInfo *	getRegisterInfo () const
virtual const InstrItineraryData *	getInstrItineraryData () const
virtual unsigned	resolveSchedClass (unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const
bool	useMachineScheduler () const
	Temporary API to test migration to MI scheduler.
virtual bool	enableMachineScheduler () const
	True if the subtarget should run MachineScheduler after aggressive coalescing.
virtual bool	enablePostMachineScheduler () const
	True if the subtarget should run PostMachineScheduler.
virtual bool	enableAtomicExpand () const
	True if the subtarget should run the atomic expansion pass.
virtual void	overrideSchedPolicy (MachineSchedPolicy &Policy, MachineInstr *begin, MachineInstr *end, unsigned NumRegionInstrs) const
	Override generic scheduling policy within a region.
virtual void	adjustSchedDependency (SUnit *def, SUnit *use, SDep &dep) const
virtual AntiDepBreakMode	getAntiDepBreakMode () const
virtual void	getCriticalPathRCs (RegClassVector &CriticalPathRCs) const
virtual CodeGenOpt::Level	getOptLevelToEnablePostRAScheduler () const
virtual bool	enableRALocalReassignment (CodeGenOpt::Level OptLevel) const
	True if the subtarget should run the local reassignment heuristic of the register allocator. This heuristic may be compile time intensive, OptLevel provides a finer grain to tune the register allocator.
virtual bool	useAA () const
	Enable use of alias analysis during code generation (during MI scheduling, DAGCombine, etc.).
virtual bool	enableEarlyIfConversion () const
	Enable the use of the early if conversion pass.
Protected Member Functions
	TargetSubtargetInfo ()

---

Detailed Description

TargetSubtargetInfo - Generic base class for all target subtargets. All Target-specific options that control code generation and printing should be exposed through a TargetSubtargetInfo-derived class.

Definition at line 43 of file TargetSubtargetInfo.h.

---

Member Typedef Documentation

typedef SmallVectorImpl<const TargetRegisterClass*> llvm::TargetSubtargetInfo::RegClassVector

Definition at line 52 of file TargetSubtargetInfo.h.

---

Member Enumeration Documentation

enum llvm::TargetSubtargetInfo::AntiDepBreakMode

Enumerator:

ANTIDEP_NONE
ANTIDEP_CRITICAL
ANTIDEP_ALL

Definition at line 51 of file TargetSubtargetInfo.h.

---

Constructor & Destructor Documentation

TargetSubtargetInfo::TargetSubtargetInfo

(

)

[protected]

Definition at line 22 of file TargetSubtargetInfo.cpp.

TargetSubtargetInfo::~TargetSubtargetInfo

(

)

[virtual]

Definition at line 24 of file TargetSubtargetInfo.cpp.

---

Member Function Documentation

virtual void llvm::TargetSubtargetInfo::adjustSchedDependency	(	SUnit *	def,
		SUnit *	use,
		SDep &	dep
	)		const [inline, virtual]

Definition at line 129 of file TargetSubtargetInfo.h.

Referenced by llvm::ScheduleDAGInstrs::addVRegUseDeps().

bool TargetSubtargetInfo::enableAtomicExpand

(

)

const [virtual]

True if the subtarget should run the atomic expansion pass.

Definition at line 42 of file TargetSubtargetInfo.cpp.

virtual bool llvm::TargetSubtargetInfo::enableEarlyIfConversion

(

)

const [inline, virtual]

Enable the use of the early if conversion pass.

Definition at line 162 of file TargetSubtargetInfo.h.

bool TargetSubtargetInfo::enableMachineScheduler

(

)

const [virtual]

True if the subtarget should run MachineScheduler after aggressive coalescing.

This currently replaces the SelectionDAG scheduler with the "source" order scheduler. It does not yet disable the postRA scheduler.

Definition at line 46 of file TargetSubtargetInfo.cpp.

Referenced by useMachineScheduler().

bool TargetSubtargetInfo::enablePostMachineScheduler

(

)

const [virtual]

True if the subtarget should run PostMachineScheduler.

This only takes effect if the target has configured the PostMachineScheduler pass to run, or if the global cl::opt flag, MISchedPostRA, is set.

Definition at line 55 of file TargetSubtargetInfo.cpp.

References llvm::MCSubtargetInfo::getSchedModel(), and llvm::MCSchedModel::PostRAScheduler.

bool TargetSubtargetInfo::enableRALocalReassignment

(

CodeGenOpt::Level

OptLevel

)

const [virtual]

True if the subtarget should run the local reassignment heuristic of the register allocator. This heuristic may be compile time intensive, OptLevel provides a finer grain to tune the register allocator.

Definition at line 50 of file TargetSubtargetInfo.cpp.

virtual AntiDepBreakMode llvm::TargetSubtargetInfo::getAntiDepBreakMode

(

)

const [inline, virtual]

Definition at line 134 of file TargetSubtargetInfo.h.

References ANTIDEP_NONE.

virtual void llvm::TargetSubtargetInfo::getCriticalPathRCs

(

RegClassVector &

CriticalPathRCs

)

const [inline, virtual]

Definition at line 141 of file TargetSubtargetInfo.h.

References llvm::SmallVectorImpl< T >::clear().

virtual const DataLayout* llvm::TargetSubtargetInfo::getDataLayout

(

)

const [inline, virtual]

Definition at line 73 of file TargetSubtargetInfo.h.

Referenced by llvm::FastISel::createMachineMemOperandFor(), llvm::AsmPrinter::doInitialization(), llvm::NVPTXAsmPrinter::doInitialization(), llvm::AsmPrinter::EmitAlignment(), llvm::AArch64FrameLowering::emitCalleeSavedFrameMoves(), llvm::AsmPrinter::EmitConstantPool(), llvm::SystemZAsmPrinter::EmitEndOfAsmFile(), llvm::ARMAsmPrinter::EmitEndOfAsmFile(), llvm::X86AsmPrinter::EmitEndOfAsmFile(), llvm::AsmPrinter::EmitGlobalConstant(), emitGlobalConstantArray(), emitGlobalConstantDataSequential(), emitGlobalConstantFP(), emitGlobalConstantImpl(), emitGlobalConstantLargeInt(), emitGlobalConstantStruct(), emitGlobalConstantVector(), llvm::AsmPrinter::EmitGlobalVariable(), llvm::ARMAsmPrinter::EmitInstruction(), llvm::AsmPrinter::EmitJumpTableInfo(), llvm::SystemZAsmPrinter::EmitMachineConstantPoolValue(), llvm::ARMAsmPrinter::EmitMachineConstantPoolValue(), llvm::TargetLoweringBase::emitPatchPoint(), llvm::TargetLoweringObjectFileELF::emitPersonalityValue(), llvm::AArch64FrameLowering::emitPrologue(), llvm::ARMAsmPrinter::EmitXXStructor(), llvm::MSP430MCInstLower::GetConstantPoolIndexSymbol(), llvm::X86AsmPrinter::GetCPISymbol(), llvm::AsmPrinter::GetCPISymbol(), llvm::AsmPrinter::getDataLayout(), llvm::MachineFunction::getJTISymbol(), llvm::AsmPrinter::GetJTSetSymbol(), llvm::MSP430MCInstLower::GetJumpTableSymbol(), llvm::TargetLoweringObjectFile::getKindForGlobal(), llvm::MachineFunction::getPICBaseSymbol(), llvm::PPCFunctionInfo::getPICOffsetSymbol(), llvm::AsmPrinter::GetSizeOfEncodedValue(), llvm::TargetInstrInfo::getStackSlotRange(), llvm::MachineBasicBlock::getSymbol(), GetSymbolFromOperand(), llvm::AsmPrinter::GetTempSymbol(), llvm::PPC::getVSPLTImmediate(), llvm::SelectionDAGBuilder::init(), llvm::TargetLoweringObjectFile::Initialize(), llvm::HexagonTargetObjectFile::IsGlobalInSmallSection(), llvm::MipsTargetObjectFile::IsGlobalInSmallSection(), llvm::XCoreTargetLowering::isLegalAddressingMode(), isRepeatedByteSequence(), llvm::PPC::isVMRGHShuffleMask(), llvm::PPC::isVMRGLShuffleMask(), llvm::PPC::isVPKUHUMShuffleMask(), llvm::PPC::isVPKUWUMShuffleMask(), llvm::PPC::isVSLDOIShuffleMask(), LLVMTargetMachineEmit(), nvptx::LowerConstant(), lowerConstant(), llvm::AMDGPUTargetLowering::LowerGlobalAddress(), llvm::MipsAsmPrinter::printOperand(), llvm::AsmPrinter::PrintSpecial(), llvm::XCoreTargetObjectFile::SelectSectionForGlobal(), llvm::TargetLoweringObjectFileELF::SelectSectionForGlobal(), and llvm::TargetLoweringObjectFileMachO::SelectSectionForGlobal().

virtual const TargetFrameLowering* llvm::TargetSubtargetInfo::getFrameLowering

(

)

const [inline, virtual]

Definition at line 66 of file TargetSubtargetInfo.h.

Referenced by llvm::ARMBaseRegisterInfo::canRealignStack(), checkNumAlignedDPRCS2Regs(), llvm::AArch64FrameLowering::eliminateCallFramePseudoInstr(), llvm::X86FrameLowering::eliminateCallFramePseudoInstr(), llvm::MSP430RegisterInfo::eliminateFrameIndex(), llvm::XCoreRegisterInfo::eliminateFrameIndex(), llvm::SystemZRegisterInfo::eliminateFrameIndex(), llvm::Thumb1RegisterInfo::eliminateFrameIndex(), llvm::HexagonRegisterInfo::eliminateFrameIndex(), llvm::AArch64RegisterInfo::eliminateFrameIndex(), llvm::ARMBaseRegisterInfo::eliminateFrameIndex(), emitDebugValueComment(), llvm::Thumb1FrameLowering::emitEpilogue(), llvm::ARMFrameLowering::emitEpilogue(), llvm::Thumb1FrameLowering::emitPrologue(), llvm::ARMFrameLowering::emitPrologue(), EnsureStackAlignment(), llvm::MachineFrameInfo::estimateStackSize(), llvm::MSP430RegisterInfo::getCalleeSavedRegs(), llvm::XCoreRegisterInfo::getCalleeSavedRegs(), llvm::MSP430RegisterInfo::getFrameRegister(), llvm::XCoreRegisterInfo::getFrameRegister(), llvm::SystemZRegisterInfo::getFrameRegister(), llvm::MipsRegisterInfo::getFrameRegister(), llvm::HexagonRegisterInfo::getFrameRegister(), llvm::AArch64RegisterInfo::getFrameRegister(), llvm::PPCRegisterInfo::getFrameRegister(), llvm::ARMBaseRegisterInfo::getFrameRegister(), llvm::AMDGPUInstrInfo::getIndirectIndexEnd(), llvm::PPCRegisterInfo::getRegPressureLimit(), llvm::MipsRegisterInfo::getRegPressureLimit(), llvm::AArch64RegisterInfo::getRegPressureLimit(), llvm::ARMBaseRegisterInfo::getRegPressureLimit(), llvm::MSP430RegisterInfo::getReservedRegs(), llvm::XCoreRegisterInfo::getReservedRegs(), llvm::SystemZRegisterInfo::getReservedRegs(), llvm::PPCRegisterInfo::getReservedRegs(), llvm::MipsRegisterInfo::getReservedRegs(), llvm::AArch64RegisterInfo::getReservedRegs(), llvm::ARMBaseRegisterInfo::getReservedRegs(), llvm::ARMBaseRegisterInfo::hasBasePointer(), llvm::AArch64RegisterInfo::isReservedReg(), llvm::PPCRegisterInfo::lowerDynamicAlloc(), llvm::SystemZTargetLowering::LowerFormalArguments(), llvm::AArch64RegisterInfo::needsFrameBaseReg(), llvm::PPCRegisterInfo::needsFrameBaseReg(), llvm::ARMBaseRegisterInfo::needsFrameBaseReg(), llvm::PPCRegisterInfo::needsStackRealignment(), llvm::ARMBaseRegisterInfo::needsStackRealignment(), llvm::MachineFrameInfo::print(), llvm::R600InstrInfo::reserveIndirectRegisters(), and llvm::PEI::runOnMachineFunction().

virtual const TargetInstrInfo* llvm::TargetSubtargetInfo::getInstrInfo

(

)

const [inline, virtual]

Definition at line 65 of file TargetSubtargetInfo.h.

Referenced by llvm::MachineBasicBlock::addLiveIn(), llvm::LLVMTargetMachine::addPassesToEmitFile(), llvm::X86FrameLowering::adjustForHiPEPrologue(), llvm::X86FrameLowering::adjustForSegmentedStacks(), llvm::ARMFrameLowering::adjustForSegmentedStacks(), llvm::SITargetLowering::AdjustInstrPostInstrSelection(), llvm::ARMTargetLowering::AdjustInstrPostInstrSelection(), llvm::VirtRegAuxInfo::calculateSpillWeightAndHint(), llvm::MachineBasicBlock::canFallThrough(), llvm::createBURRListDAGScheduler(), llvm::createHybridListDAGScheduler(), llvm::createILPListDAGScheduler(), llvm::createSourceListDAGScheduler(), llvm::AsmPrinter::doFinalization(), llvm::Mips16FrameLowering::eliminateCallFramePseudoInstr(), llvm::MipsSEFrameLowering::eliminateCallFramePseudoInstr(), llvm::AArch64FrameLowering::eliminateCallFramePseudoInstr(), llvm::MSP430FrameLowering::eliminateCallFramePseudoInstr(), llvm::XCoreFrameLowering::eliminateCallFramePseudoInstr(), llvm::Thumb1FrameLowering::eliminateCallFramePseudoInstr(), llvm::PPCFrameLowering::eliminateCallFramePseudoInstr(), llvm::X86FrameLowering::eliminateCallFramePseudoInstr(), llvm::MSP430RegisterInfo::eliminateFrameIndex(), llvm::XCoreRegisterInfo::eliminateFrameIndex(), llvm::SparcRegisterInfo::eliminateFrameIndex(), llvm::SystemZRegisterInfo::eliminateFrameIndex(), llvm::Thumb1RegisterInfo::eliminateFrameIndex(), llvm::HexagonRegisterInfo::eliminateFrameIndex(), llvm::PPCRegisterInfo::eliminateFrameIndex(), llvm::ARMBaseRegisterInfo::eliminateFrameIndex(), emitAlignedDPRCS2Restores(), emitAlignedDPRCS2Spills(), llvm::PPCTargetLowering::EmitAtomicBinary(), llvm::AArch64FrameLowering::emitCalleeSavedFrameMoves(), llvm::X86FrameLowering::emitCalleeSavedFrameMoves(), emitComments(), llvm::PPCTargetLowering::emitEHSjLjLongJmp(), llvm::PPCTargetLowering::emitEHSjLjSetJmp(), llvm::Mips16FrameLowering::emitEpilogue(), llvm::MipsSEFrameLowering::emitEpilogue(), llvm::HexagonFrameLowering::emitEpilogue(), llvm::SparcFrameLowering::emitEpilogue(), llvm::MSP430FrameLowering::emitEpilogue(), llvm::Thumb1FrameLowering::emitEpilogue(), llvm::XCoreFrameLowering::emitEpilogue(), llvm::ARMFrameLowering::emitEpilogue(), llvm::PPCFrameLowering::emitEpilogue(), llvm::AArch64FrameLowering::emitEpilogue(), llvm::X86FrameLowering::emitEpilogue(), llvm::SystemZFrameLowering::emitEpilogue(), llvm::AArch64TargetLowering::EmitF128CSEL(), llvm::AsmPrinter::EmitFunctionBody(), llvm::AMDGPUAsmPrinter::EmitInstruction(), llvm::R600TargetLowering::EmitInstrWithCustomInserter(), llvm::SITargetLowering::EmitInstrWithCustomInserter(), llvm::MSP430TargetLowering::EmitInstrWithCustomInserter(), llvm::XCoreTargetLowering::EmitInstrWithCustomInserter(), llvm::ARMTargetLowering::EmitInstrWithCustomInserter(), llvm::PPCTargetLowering::EmitInstrWithCustomInserter(), llvm::Thumb2RegisterInfo::emitLoadConstPool(), llvm::Thumb1RegisterInfo::emitLoadConstPool(), llvm::ARMBaseRegisterInfo::emitLoadConstPool(), llvm::PPCTargetLowering::EmitPartwordAtomicBinary(), llvm::Mips16FrameLowering::emitPrologue(), llvm::HexagonFrameLowering::emitPrologue(), llvm::MipsSEFrameLowering::emitPrologue(), llvm::NVPTXFrameLowering::emitPrologue(), llvm::SparcFrameLowering::emitPrologue(), llvm::MSP430FrameLowering::emitPrologue(), llvm::XCoreFrameLowering::emitPrologue(), llvm::Thumb1FrameLowering::emitPrologue(), llvm::ARMFrameLowering::emitPrologue(), llvm::PPCFrameLowering::emitPrologue(), llvm::AArch64FrameLowering::emitPrologue(), llvm::X86FrameLowering::emitPrologue(), llvm::SystemZFrameLowering::emitPrologue(), llvm::MSP430TargetLowering::EmitShiftInstr(), llvm::RegScavenger::enterBasicBlock(), llvm::SparcTargetLowering::expandAtomicRMW(), llvm::SparcTargetLowering::expandSelectCC(), FoldOperand(), llvm::AArch64InstrInfo::genAlternativeCodeSequence(), llvm::ARMHazardRecognizer::getHazardType(), llvm::MSP430InstrInfo::GetInstSizeInBytes(), llvm::SDNode::getOperationName(), llvm::ARMTargetLowering::getSchedulingPreference(), llvm::ConvergingVLIWScheduler::initialize(), llvm::GenericScheduler::initialize(), llvm::PostGenericScheduler::initialize(), INITIALIZE_PASS(), llvm::PPCRegisterInfo::lowerCRBitRestore(), llvm::PPCRegisterInfo::lowerCRBitSpilling(), llvm::PPCRegisterInfo::lowerCRRestore(), llvm::PPCRegisterInfo::lowerCRSpilling(), llvm::PPCRegisterInfo::lowerDynamicAlloc(), llvm::R600TargetLowering::LowerOperation(), llvm::PPCRegisterInfo::lowerVRSAVERestore(), llvm::PPCRegisterInfo::lowerVRSAVESpilling(), llvm::MachineSSAUpdater::MachineSSAUpdater(), llvm::PPCRegisterInfo::materializeFrameBaseRegister(), llvm::ARMBaseRegisterInfo::materializeFrameBaseRegister(), MIsNeedChainEdge(), llvm::SITargetLowering::PostISelFolding(), llvm::MachineInstr::print(), llvm::Mips16FrameLowering::processFunctionBeforeCalleeSavedScan(), llvm::ARMFrameLowering::processFunctionBeforeCalleeSavedScan(), llvm::MachineRegisterInfo::recomputeRegClass(), replaceFI(), llvm::Thumb1RegisterInfo::resolveFrameIndex(), llvm::PPCRegisterInfo::resolveFrameIndex(), llvm::ARMBaseRegisterInfo::resolveFrameIndex(), llvm::ResourcePriorityQueue::ResourcePriorityQueue(), llvm::Thumb1FrameLowering::restoreCalleeSavedRegisters(), llvm::SystemZFrameLowering::restoreCalleeSavedRegisters(), llvm::XCoreFrameLowering::restoreCalleeSavedRegisters(), llvm::HexagonFrameLowering::restoreCalleeSavedRegisters(), llvm::MSP430FrameLowering::restoreCalleeSavedRegisters(), llvm::AArch64FrameLowering::restoreCalleeSavedRegisters(), llvm::PPCFrameLowering::restoreCalleeSavedRegisters(), llvm::X86FrameLowering::restoreCalleeSavedRegisters(), restoreCRs(), llvm::SelectionDAGISel::runOnMachineFunction(), llvm::MachineTraceMetrics::runOnMachineFunction(), llvm::LiveIntervals::runOnMachineFunction(), llvm::Mips16RegisterInfo::saveScavengerRegister(), llvm::Thumb1RegisterInfo::saveScavengerRegister(), llvm::SelectionDAGISel::SelectCodeCommon(), llvm::FunctionLoweringInfo::set(), setCallTargetReg(), llvm::SITargetLowering::shouldConvertConstantLoadToIntImm(), llvm::HexagonFrameLowering::spillCalleeSavedRegisters(), llvm::SystemZFrameLowering::spillCalleeSavedRegisters(), llvm::Thumb1FrameLowering::spillCalleeSavedRegisters(), llvm::MipsSEFrameLowering::spillCalleeSavedRegisters(), llvm::XCoreFrameLowering::spillCalleeSavedRegisters(), llvm::MSP430FrameLowering::spillCalleeSavedRegisters(), llvm::AArch64FrameLowering::spillCalleeSavedRegisters(), llvm::PPCFrameLowering::spillCalleeSavedRegisters(), llvm::X86FrameLowering::spillCalleeSavedRegisters(), llvm::MachineBasicBlock::SplitCriticalEdge(), UpdateOperandRegClass(), llvm::MachineBasicBlock::updateTerminator(), llvm::VLIWPacketizerList::VLIWPacketizerList(), and llvm::VLIWResourceModel::VLIWResourceModel().

virtual const InstrItineraryData* llvm::TargetSubtargetInfo::getInstrItineraryData

(

)

const [inline, virtual]

getInstrItineraryData - Returns instruction itinerary data for the target or specific subtarget.

Definition at line 84 of file TargetSubtargetInfo.h.

Referenced by llvm::ARMTargetLowering::ARMTargetLowering(), llvm::HexagonInstrInfo::CreateTargetScheduleState(), llvm::R600InstrInfo::CreateTargetScheduleState(), and INITIALIZE_PASS().

virtual CodeGenOpt::Level llvm::TargetSubtargetInfo::getOptLevelToEnablePostRAScheduler

(

)

const [inline, virtual]

Definition at line 147 of file TargetSubtargetInfo.h.

References Default.

virtual const TargetRegisterInfo* llvm::TargetSubtargetInfo::getRegisterInfo

(

)

const [inline, virtual]

getRegisterInfo - If register information is available, return it. If not, return null. This is kept separate from RegInfo until RegInfo has details of graph coloring register allocation removed from it.

Definition at line 79 of file TargetSubtargetInfo.h.

Referenced by addLiveInRegs(), llvm::LLVMTargetMachine::addPassesToEmitFile(), llvm::LLVMTargetMachine::addPassesToEmitMC(), addPassesToGenerateCode(), llvm::DwarfUnit::addRegisterOffset(), llvm::DwarfUnit::addRegisterOpPiece(), addSavedGPR(), llvm::X86FrameLowering::adjustForHiPEPrologue(), llvm::ARMTargetLowering::ARMTargetLowering(), llvm::X86FrameLowering::assignCalleeSavedSpillSlots(), llvm::PBQPBuilder::build(), llvm::PBQPBuilderWithCoalescing::build(), llvm::VirtRegAuxInfo::calculateSpillWeightAndHint(), checkNumAlignedDPRCS2Regs(), llvm::TargetSchedModel::computeOutputLatency(), llvm::createBURRListDAGScheduler(), llvm::createHybridListDAGScheduler(), llvm::createILPListDAGScheduler(), llvm::createSourceListDAGScheduler(), llvm::PPCFrameLowering::determineFrameLayout(), llvm::Thumb1FrameLowering::eliminateCallFramePseudoInstr(), llvm::X86FrameLowering::eliminateCallFramePseudoInstr(), emitDebugValueComment(), llvm::AsmPrinter::EmitDwarfRegOp(), llvm::AsmPrinter::EmitDwarfRegOpPiece(), llvm::MipsSEFrameLowering::emitEpilogue(), llvm::Thumb1FrameLowering::emitEpilogue(), llvm::ARMFrameLowering::emitEpilogue(), llvm::PPCFrameLowering::emitEpilogue(), llvm::AArch64FrameLowering::emitEpilogue(), llvm::X86FrameLowering::emitEpilogue(), llvm::MipsAsmPrinter::emitFrameDirective(), llvm::AsmPrinter::emitImplicitDef(), llvm::AMDGPUAsmPrinter::EmitInstruction(), llvm::X86AsmPrinter::EmitInstruction(), emitKill(), llvm::MipsSEFrameLowering::emitPrologue(), llvm::HexagonFrameLowering::emitPrologue(), llvm::Thumb1FrameLowering::emitPrologue(), llvm::XCoreFrameLowering::emitPrologue(), llvm::ARMFrameLowering::emitPrologue(), llvm::PPCFrameLowering::emitPrologue(), llvm::AArch64FrameLowering::emitPrologue(), llvm::X86FrameLowering::emitPrologue(), llvm::RegScavenger::enterBasicBlock(), llvm::MipsFrameLowering::estimateStackSize(), llvm::MachineFrameInfo::estimateStackSize(), llvm::TargetLoweringBase::findRepresentativeClass(), llvm::TargetInstrInfo::foldMemoryOperand(), llvm::X86FrameLowering::getFrameIndexOffset(), llvm::X86FrameLowering::getFrameIndexReference(), llvm::TargetFrameLowering::getFrameIndexReference(), getMemcpyLoadsAndStores(), llvm::MipsTargetLowering::getOpndList(), llvm::MachineFrameInfo::getPristineRegs(), llvm::PPCTargetLowering::getRegForInlineAsmConstraint(), llvm::TargetLowering::getRegForInlineAsmConstraint(), llvm::TargetInstrInfo::getStackSlotRange(), HandleVRSaveUpdate(), llvm::ARMFrameLowering::hasFP(), llvm::AArch64FrameLowering::hasFP(), llvm::X86FrameLowering::hasFP(), llvm::Hexagon_CCState::Hexagon_CCState(), llvm::HexagonTargetLowering::HexagonTargetLowering(), llvm::RegPressureTracker::init(), initReachingDef(), llvm::TargetInstrInfo::isSchedulingBoundary(), llvm::HexagonTargetLowering::LowerCall(), llvm::SystemZTargetLowering::LowerCall(), llvm::HexagonTargetLowering::LowerDYNAMIC_STACKALLOC(), llvm::SITargetLowering::LowerFormalArguments(), llvm::HexagonTargetLowering::LowerFRAMEADDR(), llvm::SparcTargetLowering::LowerGlobalTLSAddress(), llvm::HexagonTargetLowering::LowerINLINEASM(), LowerINTRINSIC_W_CHAIN(), llvm::HexagonTargetLowering::LowerRETURNADDR(), llvm::MachineFunction::MachineFunction(), llvm::MachineOperand::print(), llvm::MachineFunction::print(), llvm::MachineBasicBlock::print(), llvm::MachineInstr::print(), llvm::ARMAsmPrinter::PrintAsmOperand(), llvm::ARMAsmPrinter::printOperand(), llvm::MipsAsmPrinter::printSavedRegsBitmask(), llvm::SystemZFrameLowering::processFunctionBeforeCalleeSavedScan(), llvm::PPCFrameLowering::processFunctionBeforeCalleeSavedScan(), llvm::X86FrameLowering::processFunctionBeforeCalleeSavedScan(), llvm::ARMFrameLowering::processFunctionBeforeCalleeSavedScan(), llvm::AArch64FrameLowering::processFunctionBeforeCalleeSavedScan(), llvm::PPCFrameLowering::processFunctionBeforeFrameFinalized(), llvm::PPCFrameLowering::replaceFPWithRealFP(), llvm::AArch64FrameLowering::resolveFrameIndexReference(), llvm::ARMFrameLowering::ResolveFrameIndexReference(), llvm::ResourcePriorityQueue::ResourcePriorityQueue(), llvm::PEI::runOnMachineFunction(), llvm::SelectionDAGISel::runOnMachineFunction(), llvm::MachineTraceMetrics::runOnMachineFunction(), llvm::RegisterClassInfo::runOnMachineFunction(), llvm::LiveStacks::runOnMachineFunction(), llvm::LiveVariables::runOnMachineFunction(), llvm::LiveIntervals::runOnMachineFunction(), llvm::StackMaps::serializeToStackMapSection(), llvm::MachineBasicBlock::SplitCriticalEdge(), and UpdateOperandRegClass().

virtual const TargetSelectionDAGInfo* llvm::TargetSubtargetInfo::getSelectionDAGInfo

(

)

const [inline, virtual]

Definition at line 70 of file TargetSubtargetInfo.h.

virtual const TargetLowering* llvm::TargetSubtargetInfo::getTargetLowering

(

)

const [inline, virtual]

Definition at line 69 of file TargetSubtargetInfo.h.

Referenced by addPassesToGenerateCode(), llvm::SelectionDAG::computeKnownBits(), llvm::SelectionDAG::ComputeNumSignBits(), llvm::SelectionDAGBuilder::CopyValueToVirtualRegister(), llvm::SelectionDAG::CreateStackTemporary(), llvm::XCoreFrameLowering::emitEpilogue(), llvm::AsmPrinter::EmitJumpTableInfo(), llvm::XCoreFrameLowering::emitPrologue(), llvm::XCoreSelectionDAGInfo::EmitTargetCodeForMemcpy(), llvm::SelectionDAG::FoldSetCC(), llvm::SelectionDAG::getConstant(), llvm::SelectionDAG::getConstantPool(), llvm::SelectionDAG::getEVTAlignment(), llvm::SelectionDAG::getGlobalAddress(), llvm::SelectionDAG::getIntPtrConstant(), llvm::SelectionDAG::getMemcpy(), llvm::SelectionDAG::getMemmove(), llvm::SelectionDAG::getMemset(), llvm::TargetMachine::getNameWithPrefix(), llvm::AsmPrinter::getObjFileLowering(), llvm::SelectionDAG::getShiftAmountOperand(), llvm::TargetMachine::getSymbol(), llvm::SelectionDAGISel::getTargetLowering(), llvm::SelectionDAGBuilder::getValue(), llvm::SelectionDAGBuilder::getValueImpl(), llvm::CCState::HandleByVal(), llvm::SelectionDAG::InferPtrAlignment(), llvm::GenericScheduler::initPolicy(), llvm::SelectionDAG::isConsecutiveLoad(), llvm::isInTailCallPosition(), llvm::TargetInstrInfo::isSchedulingBoundary(), llvm::SelectionDAGBuilder::LowerCallOperands(), llvm::SelectionDAGBuilder::LowerCallTo(), llvm::NVPTXTargetLowering::LowerFormalArguments(), llvm::MachineFunction::MachineFunction(), llvm::StackProtector::runOnFunction(), llvm::SelectionDAGISel::runOnMachineFunction(), llvm::SelectionDAG::UnrollVectorOp(), llvm::SelectionDAGBuilder::visitBitTestCase(), llvm::SelectionDAGBuilder::visitBitTestHeader(), llvm::SelectionDAGBuilder::visitJumpTable(), llvm::SelectionDAGBuilder::visitJumpTableHeader(), llvm::SelectionDAGBuilder::visitSPDescriptorFailure(), and llvm::SelectionDAGBuilder::visitSPDescriptorParent().

virtual void llvm::TargetSubtargetInfo::overrideSchedPolicy	(	MachineSchedPolicy &	Policy,
		MachineInstr *	begin,
		MachineInstr *	end,
		unsigned	NumRegionInstrs
	)		const [inline, virtual]

Override generic scheduling policy within a region.

This is a convenient way for targets that don't provide any custom scheduling heuristics (no custom MachineSchedStrategy) to make changes to the generic scheduling policy.

Definition at line 122 of file TargetSubtargetInfo.h.

Referenced by llvm::GenericScheduler::initPolicy().

virtual unsigned llvm::TargetSubtargetInfo::resolveSchedClass	(	unsigned	SchedClass,
		const MachineInstr *	MI,
		const TargetSchedModel *	SchedModel
	)		const [inline, virtual]

Resolve a SchedClass at runtime, where SchedClass identifies an MCSchedClassDesc with the isVariant property. This may return the ID of another variant SchedClass, but repeated invocation must quickly terminate in a nonvariant SchedClass.

Definition at line 92 of file TargetSubtargetInfo.h.

Referenced by llvm::TargetSchedModel::resolveSchedClass().

bool TargetSubtargetInfo::useAA

(

)

const [virtual]

Enable use of alias analysis during code generation (during MI scheduling, DAGCombine, etc.).

Definition at line 59 of file TargetSubtargetInfo.cpp.

Referenced by llvm::ScheduleDAGInstrs::buildSchedGraph().

bool TargetSubtargetInfo::useMachineScheduler

(

)

const

Temporary API to test migration to MI scheduler.

Definition at line 36 of file TargetSubtargetInfo.cpp.

References BenchMachineSched, and enableMachineScheduler().

Referenced by llvm::createDefaultScheduler(), and llvm::TargetPassConfig::TargetPassConfig().

---

The documentation for this class was generated from the following files:

• TargetSubtargetInfo.h
• TargetSubtargetInfo.cpp