Define some predicates that are used for node matching. More...

Enumerations
enum	Fixups { fixup_ppc_br24 = FirstTargetFixupKind, fixup_ppc_brcond14, fixup_ppc_br24abs, fixup_ppc_brcond14abs, fixup_ppc_half16, fixup_ppc_half16ds, fixup_ppc_nofixup, LastTargetFixupKind, NumTargetFixupKinds = LastTargetFixupKind - FirstTargetFixupKind }
enum	Predicate { PRED_LT = (0 << 5) \| 12, PRED_LE = (1 << 5) \| 4, PRED_EQ = (2 << 5) \| 12, PRED_GE = (0 << 5) \| 4, PRED_GT = (1 << 5) \| 12, PRED_NE = (2 << 5) \| 4, PRED_UN = (3 << 5) \| 12, PRED_NU = (3 << 5) \| 4, PRED_LT_MINUS = (0 << 5) \| 14, PRED_LE_MINUS = (1 << 5) \| 6, PRED_EQ_MINUS = (2 << 5) \| 14, PRED_GE_MINUS = (0 << 5) \| 6, PRED_GT_MINUS = (1 << 5) \| 14, PRED_NE_MINUS = (2 << 5) \| 6, PRED_UN_MINUS = (3 << 5) \| 14, PRED_NU_MINUS = (3 << 5) \| 6, PRED_LT_PLUS = (0 << 5) \| 15, PRED_LE_PLUS = (1 << 5) \| 7, PRED_EQ_PLUS = (2 << 5) \| 15, PRED_GE_PLUS = (0 << 5) \| 7, PRED_GT_PLUS = (1 << 5) \| 15, PRED_NE_PLUS = (2 << 5) \| 7, PRED_UN_PLUS = (3 << 5) \| 15, PRED_NU_PLUS = (3 << 5) \| 7, PRED_BIT_SET = 1024, PRED_BIT_UNSET = 1025 }
	Predicate - These are "(BI << 5) \| BO" for various predicates. More...
enum	RelocationType { reloc_vanilla, reloc_pcrel_bx, reloc_pcrel_bcx, reloc_absolute_high, reloc_absolute_low, reloc_absolute_low_ix }
enum	{ DIR_NONE, DIR_32, DIR_440, DIR_601, DIR_602, DIR_603, DIR_7400, DIR_750, DIR_970, DIR_A2, DIR_E500mc, DIR_E5500, DIR_PWR3, DIR_PWR4, DIR_PWR5, DIR_PWR5X, DIR_PWR6, DIR_PWR6X, DIR_PWR7, DIR_PWR8, DIR_64 }
Functions
Predicate	InvertPredicate (Predicate Opcode)
	Invert the specified predicate. != -> ==, < -> >=.
Predicate	getSwappedPredicate (Predicate Opcode)
int	getNonRecordFormOpcode (uint16_t)
bool	isVPKUHUMShuffleMask (ShuffleVectorSDNode *N, unsigned ShuffleKind, SelectionDAG &DAG)
bool	isVPKUWUMShuffleMask (ShuffleVectorSDNode *N, unsigned ShuffleKind, SelectionDAG &DAG)
bool	isVMRGLShuffleMask (ShuffleVectorSDNode *N, unsigned UnitSize, unsigned ShuffleKind, SelectionDAG &DAG)
bool	isVMRGHShuffleMask (ShuffleVectorSDNode *N, unsigned UnitSize, unsigned ShuffleKind, SelectionDAG &DAG)
int	isVSLDOIShuffleMask (SDNode *N, unsigned ShuffleKind, SelectionDAG &DAG)
bool	isSplatShuffleMask (ShuffleVectorSDNode *N, unsigned EltSize)
bool	isAllNegativeZeroVector (SDNode *N)
unsigned	getVSPLTImmediate (SDNode *N, unsigned EltSize, SelectionDAG &DAG)
SDValue	get_VSPLTI_elt (SDNode *N, unsigned ByteSize, SelectionDAG &DAG)
FastISel *	createFastISel (FunctionLoweringInfo &FuncInfo, const TargetLibraryInfo *LibInfo)

Detailed Description

Define some predicates that are used for node matching.

Enumeration Type Documentation

anonymous enum

Enumerator:

DIR_NONE
DIR_32
DIR_440
DIR_601
DIR_602
DIR_603
DIR_7400
DIR_750
DIR_970
DIR_A2
DIR_E500mc
DIR_E5500
DIR_PWR3
DIR_PWR4
DIR_PWR5
DIR_PWR5X
DIR_PWR6
DIR_PWR6X
DIR_PWR7
DIR_PWR8
DIR_64

Definition at line 38 of file PPCSubtarget.h.

enum llvm::PPC::Fixups

Enumerator:

fixup_ppc_br24
fixup_ppc_brcond14	fixup_ppc_brcond14 - 14-bit PC relative relocation for conditional branches.
fixup_ppc_br24abs	fixup_ppc_br24abs - 24-bit absolute relocation for direct branches like 'ba' and 'bla'.
fixup_ppc_brcond14abs	fixup_ppc_brcond14abs - 14-bit absolute relocation for conditional branches.
fixup_ppc_half16	fixup_ppc_half16 - A 16-bit fixup corresponding to lo16(_foo) or ha16(_foo) for instrs like 'li' or 'addis'.
fixup_ppc_half16ds	fixup_ppc_half16ds - A 14-bit fixup corresponding to lo16(_foo) with implied 2 zero bits for instrs like 'std'.
fixup_ppc_nofixup	fixup_ppc_nofixup - Not a true fixup, but ties a symbol to a call to __tls_get_addr for the TLS general and local dynamic models, or inserts the thread-pointer register number.
LastTargetFixupKind
NumTargetFixupKinds

Definition at line 19 of file PPCFixupKinds.h.

enum llvm::PPC::Predicate

Predicate - These are "(BI << 5) | BO" for various predicates.

Enumerator:

PRED_LT
PRED_LE
PRED_EQ
PRED_GE
PRED_GT
PRED_NE
PRED_UN
PRED_NU
PRED_LT_MINUS
PRED_LE_MINUS
PRED_EQ_MINUS
PRED_GE_MINUS
PRED_GT_MINUS
PRED_NE_MINUS
PRED_UN_MINUS
PRED_NU_MINUS
PRED_LT_PLUS
PRED_LE_PLUS
PRED_EQ_PLUS
PRED_GE_PLUS
PRED_GT_PLUS
PRED_NE_PLUS
PRED_UN_PLUS
PRED_NU_PLUS
PRED_BIT_SET
PRED_BIT_UNSET

Definition at line 27 of file PPCPredicates.h.

enum llvm::PPC::RelocationType

Enumerator:

reloc_vanilla
reloc_pcrel_bx
reloc_pcrel_bcx
reloc_absolute_high
reloc_absolute_low
reloc_absolute_low_ix

Definition at line 27 of file PPCRelocations.h.

Function Documentation

FastISel * llvm::PPC::createFastISel	(	FunctionLoweringInfo &	FuncInfo,
		const TargetLibraryInfo *	LibInfo
	)

Definition at line 2281 of file PPCFastISel.cpp.

References llvm::TargetMachine::getSubtarget(), llvm::MachineFunction::getTarget(), llvm::PPCSubtarget::isPPC64(), llvm::PPCSubtarget::isSVR4ABI(), llvm::FunctionLoweringInfo::MF, and llvm::SystemZISD::TM.

SDValue llvm::PPC::get_VSPLTI_elt	(	SDNode *	N,
		unsigned	ByteSize,
		SelectionDAG &	DAG
	)

get_VSPLTI_elt - If this is a build_vector of constants which can be formed by using a vspltis[bhw] instruction of the specified element size, return the constant being splatted. The ByteSize field indicates the number of bytes of each element [124] -> [bhw].

Definition at line 1099 of file PPCISelLowering.cpp.

References llvm::MVT::f32, llvm::FloatToBits(), llvm::SDValue::getNode(), llvm::SDNode::getNumOperands(), llvm::SDValue::getOpcode(), llvm::SDNode::getOperand(), llvm::SelectionDAG::getTargetConstant(), llvm::MVT::i32, llvm::SignExtend32(), and llvm::ISD::UNDEF.

int llvm::PPC::getNonRecordFormOpcode ( uint16_t )

Referenced by llvm::PPCInstrInfo::optimizeCompareInstr().

PPC::Predicate llvm::PPC::getSwappedPredicate ( PPC::Predicate Opcode )

Assume the condition register is set by MI(a,b), return the predicate if we modify the instructions such that condition register is set by MI(b,a).

Definition at line 53 of file PPCPredicates.cpp.

References llvm_unreachable, PRED_BIT_SET, PRED_BIT_UNSET, PRED_EQ, PRED_EQ_MINUS, PRED_EQ_PLUS, PRED_GE, PRED_GE_MINUS, PRED_GE_PLUS, PRED_GT, PRED_GT_MINUS, PRED_GT_PLUS, PRED_LE, PRED_LE_MINUS, PRED_LE_PLUS, PRED_LT, PRED_LT_MINUS, PRED_LT_PLUS, PRED_NE, PRED_NE_MINUS, PRED_NE_PLUS, PRED_NU, PRED_NU_MINUS, PRED_NU_PLUS, PRED_UN, PRED_UN_MINUS, and PRED_UN_PLUS.

Referenced by llvm::InstCombiner::FoldAndOfFCmps(), llvm::InstCombiner::FoldGEPICmp(), llvm::InstCombiner::FoldICmpDivCst(), llvm::InstCombiner::FoldOrOfFCmps(), isSameCompare(), llvm::PPCInstrInfo::optimizeCompareInstr(), SimplifyFCmpInst(), SimplifyICmpInst(), llvm::ScalarEvolution::SimplifyICmpOperands(), llvm::ICmpInst::swapOperands(), ThreadCmpOverPHI(), ThreadCmpOverSelect(), llvm::InstCombiner::visitICmpInstWithInstAndIntCst(), and llvm::InstCombiner::visitSelectInstWithICmp().

unsigned llvm::PPC::getVSPLTImmediate	(	SDNode *	N,
		unsigned	EltSize,
		SelectionDAG &	DAG
	)

getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the specified isSplatShuffleMask VECTOR_SHUFFLE mask.

Definition at line 1085 of file PPCISelLowering.cpp.

References llvm::TargetSubtargetInfo::getDataLayout(), llvm::ShuffleVectorSDNode::getMaskElt(), llvm::SelectionDAG::getSubtarget(), llvm::DataLayout::isLittleEndian(), and isSplatShuffleMask().

PPC::Predicate llvm::PPC::InvertPredicate ( PPC::Predicate Opcode )

Invert the specified predicate. != -> ==, < -> >=.

Definition at line 19 of file PPCPredicates.cpp.

References llvm_unreachable, PRED_BIT_SET, PRED_BIT_UNSET, PRED_EQ, PRED_EQ_MINUS, PRED_EQ_PLUS, PRED_GE, PRED_GE_MINUS, PRED_GE_PLUS, PRED_GT, PRED_GT_MINUS, PRED_GT_PLUS, PRED_LE, PRED_LE_MINUS, PRED_LE_PLUS, PRED_LT, PRED_LT_MINUS, PRED_LT_PLUS, PRED_NE, PRED_NE_MINUS, PRED_NE_PLUS, PRED_NU, PRED_NU_MINUS, PRED_NU_PLUS, PRED_UN, PRED_UN_MINUS, and PRED_UN_PLUS.

Referenced by llvm::PPCInstrInfo::ReverseBranchCondition().

bool llvm::PPC::isAllNegativeZeroVector ( SDNode * N )

isAllNegativeZeroVector - Returns true if all elements of build_vector are -0.0.

Definition at line 1069 of file PPCISelLowering.cpp.

References llvm::SDNode::getOperand(), and llvm::BuildVectorSDNode::isConstantSplat().

bool llvm::PPC::isSplatShuffleMask	(	ShuffleVectorSDNode *	N,
		unsigned	EltSize
	)

isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand specifies a splat of a single element that is suitable for input to VSPLTB/VSPLTH/VSPLTW.

Definition at line 1040 of file PPCISelLowering.cpp.

References llvm::ShuffleVectorSDNode::getMaskElt(), llvm::SDNode::getValueType(), and llvm::MVT::v16i8.

Referenced by getVSPLTImmediate().

bool llvm::PPC::isVMRGHShuffleMask	(	ShuffleVectorSDNode *	N,
		unsigned	UnitSize,
		unsigned	ShuffleKind,
		SelectionDAG &	DAG
	)

isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for a VRGH* instruction with the specified unit size (1,2 or 4 bytes).

isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for a VMRGH* instruction with the specified unit size (1,2 or 4 bytes). The ShuffleKind distinguishes between big-endian merges with two different inputs (0), either-endian merges with two identical inputs (1), and little-endian merges with two different inputs (2). For the latter, the input operands are swapped (see PPCInstrAltivec.td).

Definition at line 969 of file PPCISelLowering.cpp.

References llvm::TargetSubtargetInfo::getDataLayout(), llvm::SelectionDAG::getSubtarget(), llvm::DataLayout::isLittleEndian(), and isVMerge().

bool llvm::PPC::isVMRGLShuffleMask	(	ShuffleVectorSDNode *	N,
		unsigned	UnitSize,
		unsigned	ShuffleKind,
		SelectionDAG &	DAG
	)

isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for a VRGL* instruction with the specified unit size (1,2 or 4 bytes).

isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for a VMRGL* instruction with the specified unit size (1,2 or 4 bytes). The ShuffleKind distinguishes between big-endian merges with two different inputs (0), either-endian merges with two identical inputs (1), and little-endian merges with two different inputs (2). For the latter, the input operands are swapped (see PPCInstrAltivec.td).

Definition at line 944 of file PPCISelLowering.cpp.

References llvm::TargetSubtargetInfo::getDataLayout(), llvm::SelectionDAG::getSubtarget(), llvm::DataLayout::isLittleEndian(), and isVMerge().

bool llvm::PPC::isVPKUHUMShuffleMask	(	ShuffleVectorSDNode *	N,
		unsigned	ShuffleKind,
		SelectionDAG &	DAG
	)

isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a VPKUHUM instruction.

isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a VPKUHUM instruction. The ShuffleKind distinguishes between big-endian operations with two different inputs (0), either-endian operations with two identical inputs (1), and little-endian operantion with two different inputs (2). For the latter, the input operands are swapped (see PPCInstrAltivec.td).

Definition at line 858 of file PPCISelLowering.cpp.

References llvm::TargetSubtargetInfo::getDataLayout(), llvm::ShuffleVectorSDNode::getMaskElt(), llvm::SelectionDAG::getSubtarget(), isConstantOrUndef(), and llvm::DataLayout::isLittleEndian().

bool llvm::PPC::isVPKUWUMShuffleMask	(	ShuffleVectorSDNode *	N,
		unsigned	ShuffleKind,
		SelectionDAG &	DAG
	)

isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a VPKUWUM instruction.

isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a VPKUWUM instruction. The ShuffleKind distinguishes between big-endian operations with two different inputs (0), either-endian operations with two identical inputs (1), and little-endian operantion with two different inputs (2). For the latter, the input operands are swapped (see PPCInstrAltivec.td).

Definition at line 889 of file PPCISelLowering.cpp.

References llvm::TargetSubtargetInfo::getDataLayout(), llvm::ShuffleVectorSDNode::getMaskElt(), llvm::SelectionDAG::getSubtarget(), isConstantOrUndef(), and llvm::DataLayout::isLittleEndian().

int llvm::PPC::isVSLDOIShuffleMask	(	SDNode *	N,
		unsigned	ShuffleKind,
		SelectionDAG &	DAG
	)

isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift amount, otherwise return -1.

isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift amount, otherwise return -1. The ShuffleKind distinguishes between big-endian operations with two different inputs (0), either-endian operations with two identical inputs (1), and little-endian operations with two different inputs (2). For the latter, the input operands are swapped (see PPCInstrAltivec.td).

Definition at line 995 of file PPCISelLowering.cpp.

References llvm::TargetSubtargetInfo::getDataLayout(), llvm::ShuffleVectorSDNode::getMaskElt(), llvm::TargetMachine::getSubtargetImpl(), llvm::SelectionDAG::getTarget(), llvm::SDNode::getValueType(), isConstantOrUndef(), and llvm::MVT::v16i8.

Enumerations

Functions

Detailed Description

Enumeration Type Documentation

Function Documentation