LLVM API Documentation

TargetSubtargetInfo.cpp
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00001 //===-- TargetSubtargetInfo.cpp - General Target Information ---------------==//
00002 //
00003 //                     The LLVM Compiler Infrastructure
00004 //
00005 // This file is distributed under the University of Illinois Open Source
00006 // License. See LICENSE.TXT for details.
00007 //
00008 //===----------------------------------------------------------------------===//
00009 //
00010 // This file describes the general parts of a Subtarget.
00011 //
00012 //===----------------------------------------------------------------------===//
00013 
00014 #include "llvm/Support/CommandLine.h"
00015 #include "llvm/ADT/SmallVector.h"
00016 #include "llvm/Target/TargetSubtargetInfo.h"
00017 using namespace llvm;
00018 
00019 //---------------------------------------------------------------------------
00020 // TargetSubtargetInfo Class
00021 //
00022 TargetSubtargetInfo::TargetSubtargetInfo() {}
00023 
00024 TargetSubtargetInfo::~TargetSubtargetInfo() {}
00025 
00026 // Temporary option to compare overall performance change when moving from the
00027 // SD scheduler to the MachineScheduler pass pipeline. This is convenient for
00028 // benchmarking during the transition from SD to MI scheduling. Once armv7 makes
00029 // the switch, it should go away. The normal way to enable/disable the
00030 // MachineScheduling pass itself is by using -enable-misched. For targets that
00031 // already use MI sched (via MySubTarget::enableMachineScheduler())
00032 // -misched-bench=false negates the subtarget hook.
00033 static cl::opt<bool> BenchMachineSched("misched-bench", cl::Hidden,
00034     cl::desc("Migrate from the target's default SD scheduler to MI scheduler"));
00035 
00036 bool TargetSubtargetInfo::useMachineScheduler() const {
00037   if (BenchMachineSched.getNumOccurrences())
00038     return BenchMachineSched;
00039   return enableMachineScheduler();
00040 }
00041 
00042 bool TargetSubtargetInfo::enableAtomicExpand() const {
00043   return true;
00044 }
00045 
00046 bool TargetSubtargetInfo::enableMachineScheduler() const {
00047   return false;
00048 }
00049 
00050 bool TargetSubtargetInfo::enableRALocalReassignment(
00051     CodeGenOpt::Level OptLevel) const {
00052   return true;
00053 }
00054 
00055 bool TargetSubtargetInfo::enablePostMachineScheduler() const {
00056   return getSchedModel().PostRAScheduler;
00057 }
00058 
00059 bool TargetSubtargetInfo::useAA() const {
00060   return false;
00061 }