llvm::PPCInstrInfo Member List

This is the complete list of members for llvm::PPCInstrInfo, including all inherited members.

AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override	llvm::PPCInstrInfo
analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2, int &Mask, int &Value) const override	llvm::PPCInstrInfo
canInsertSelect(const MachineBasicBlock &, const SmallVectorImpl< MachineOperand > &Cond, unsigned, unsigned, int &, int &, int &) const override	llvm::PPCInstrInfo
commuteInstruction(MachineInstr *MI, bool NewMI) const override	llvm::PPCInstrInfo
copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override	llvm::PPCInstrInfo
CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, const ScheduleDAG *DAG) const override	llvm::PPCInstrInfo
CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, const ScheduleDAG *DAG) const override	llvm::PPCInstrInfo
DefinesPredicate(MachineInstr *MI, std::vector< MachineOperand > &Pred) const override	llvm::PPCInstrInfo
findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const override	llvm::PPCInstrInfo
FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI, unsigned Reg, MachineRegisterInfo *MRI) const override	llvm::PPCInstrInfo
GetInstSizeInBytes(const MachineInstr *MI) const	llvm::PPCInstrInfo
getNoopForMachoTarget(MCInst &NopInst) const override	llvm::PPCInstrInfo
getOperandLatency(const InstrItineraryData *ItinData, const MachineInstr *DefMI, unsigned DefIdx, const MachineInstr *UseMI, unsigned UseIdx) const override	llvm::PPCInstrInfo
getOperandLatency(const InstrItineraryData *ItinData, SDNode *DefNode, unsigned DefIdx, SDNode *UseNode, unsigned UseIdx) const override	llvm::PPCInstrInfo	[inline]
getRegisterInfo() const	llvm::PPCInstrInfo	[inline]
InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl< MachineOperand > &Cond, DebugLoc DL) const override	llvm::PPCInstrInfo
insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const override	llvm::PPCInstrInfo
insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, DebugLoc DL, unsigned DstReg, const SmallVectorImpl< MachineOperand > &Cond, unsigned TrueReg, unsigned FalseReg) const override	llvm::PPCInstrInfo
isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg, unsigned &SubIdx) const override	llvm::PPCInstrInfo
isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const override	llvm::PPCInstrInfo
isPredicable(MachineInstr *MI) const override	llvm::PPCInstrInfo
isPredicated(const MachineInstr *MI) const override	llvm::PPCInstrInfo
isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, const BranchProbability &Probability) const override	llvm::PPCInstrInfo	[inline]
isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, const BranchProbability &Probability) const override	llvm::PPCInstrInfo	[inline]
isProfitableToIfCvt(MachineBasicBlock &TMBB, unsigned NumT, unsigned ExtraT, MachineBasicBlock &FMBB, unsigned NumF, unsigned ExtraF, const BranchProbability &Probability) const override	llvm::PPCInstrInfo
isProfitableToUnpredicate(MachineBasicBlock &TMBB, MachineBasicBlock &FMBB) const override	llvm::PPCInstrInfo	[inline]
isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const override	llvm::PPCInstrInfo
isUnpredicatedTerminator(const MachineInstr *MI) const override	llvm::PPCInstrInfo
loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override	llvm::PPCInstrInfo
optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2, int Mask, int Value, const MachineRegisterInfo *MRI) const override	llvm::PPCInstrInfo
PPCInstrInfo(PPCSubtarget &STI)	llvm::PPCInstrInfo	[explicit]
PredicateInstruction(MachineInstr *MI, const SmallVectorImpl< MachineOperand > &Pred) const override	llvm::PPCInstrInfo
RemoveBranch(MachineBasicBlock &MBB) const override	llvm::PPCInstrInfo
ReverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override	llvm::PPCInstrInfo
storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override	llvm::PPCInstrInfo
SubsumesPredicate(const SmallVectorImpl< MachineOperand > &Pred1, const SmallVectorImpl< MachineOperand > &Pred2) const override	llvm::PPCInstrInfo