llvm::TargetInstrInfo Member List

This is the complete list of members for llvm::TargetInstrInfo, including all inherited members.

AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify=false) const	llvm::TargetInstrInfo	[inline, virtual]
analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2, int &Mask, int &Value) const	llvm::TargetInstrInfo	[inline, virtual]
analyzeSelect(const MachineInstr *MI, SmallVectorImpl< MachineOperand > &Cond, unsigned &TrueOp, unsigned &FalseOp, bool &Optimizable) const	llvm::TargetInstrInfo	[inline, virtual]
areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1, int64_t &Offset2) const	llvm::TargetInstrInfo	[inline, virtual]
areMemAccessesTriviallyDisjoint(MachineInstr *MIa, MachineInstr *MIb, AliasAnalysis *AA=nullptr) const	llvm::TargetInstrInfo	[inline, virtual]
breakPartialRegDependency(MachineBasicBlock::iterator MI, unsigned OpNum, const TargetRegisterInfo *TRI) const	llvm::TargetInstrInfo	[inline, virtual]
canFoldMemoryOperand(const MachineInstr *MI, const SmallVectorImpl< unsigned > &Ops) const	llvm::TargetInstrInfo	[virtual]
canInsertSelect(const MachineBasicBlock &MBB, const SmallVectorImpl< MachineOperand > &Cond, unsigned TrueReg, unsigned FalseReg, int &CondCycles, int &TrueCycles, int &FalseCycles) const	llvm::TargetInstrInfo	[inline, virtual]
commuteInstruction(MachineInstr *MI, bool NewMI=false) const	llvm::TargetInstrInfo	[virtual]
computeDefOperandLatency(const InstrItineraryData *ItinData, const MachineInstr *DefMI) const	llvm::TargetInstrInfo
computeOperandLatency(const InstrItineraryData *ItinData, const MachineInstr *DefMI, unsigned DefIdx, const MachineInstr *UseMI, unsigned UseIdx) const	llvm::TargetInstrInfo
convertToThreeAddress(MachineFunction::iterator &MFI, MachineBasicBlock::iterator &MBBI, LiveVariables *LV) const	llvm::TargetInstrInfo	[inline, virtual]
copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const	llvm::TargetInstrInfo	[inline, virtual]
CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, const ScheduleDAG *DAG) const	llvm::TargetInstrInfo	[virtual]
CreateTargetMIHazardRecognizer(const InstrItineraryData *, const ScheduleDAG *DAG) const	llvm::TargetInstrInfo	[virtual]
CreateTargetPostRAHazardRecognizer(const InstrItineraryData *, const ScheduleDAG *DAG) const	llvm::TargetInstrInfo	[virtual]
CreateTargetScheduleState(const TargetMachine *, const ScheduleDAG *) const	llvm::TargetInstrInfo	[inline, virtual]
defaultDefLatency(const MCSchedModel &SchedModel, const MachineInstr *DefMI) const	llvm::TargetInstrInfo
DefinesPredicate(MachineInstr *MI, std::vector< MachineOperand > &Pred) const	llvm::TargetInstrInfo	[inline, virtual]
duplicate(MachineInstr *Orig, MachineFunction &MF) const	llvm::TargetInstrInfo	[virtual]
enableClusterLoads() const	llvm::TargetInstrInfo	[inline, virtual]
expandPostRAPseudo(MachineBasicBlock::iterator MI) const	llvm::TargetInstrInfo	[inline, virtual]
findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const	llvm::TargetInstrInfo	[virtual]
FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI, unsigned Reg, MachineRegisterInfo *MRI) const	llvm::TargetInstrInfo	[inline, virtual]
foldMemoryOperand(MachineBasicBlock::iterator MI, const SmallVectorImpl< unsigned > &Ops, int FrameIndex) const	llvm::TargetInstrInfo
foldMemoryOperand(MachineBasicBlock::iterator MI, const SmallVectorImpl< unsigned > &Ops, MachineInstr *LoadMI) const	llvm::TargetInstrInfo
foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI, const SmallVectorImpl< unsigned > &Ops, int FrameIndex) const	llvm::TargetInstrInfo	[inline, protected, virtual]
foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI, const SmallVectorImpl< unsigned > &Ops, MachineInstr *LoadMI) const	llvm::TargetInstrInfo	[inline, protected, virtual]
genAlternativeCodeSequence(MachineInstr &Root, MachineCombinerPattern::MC_PATTERN P, SmallVectorImpl< MachineInstr * > &InsInstrs, SmallVectorImpl< MachineInstr * > &DelInstrs, DenseMap< unsigned, unsigned > &InstrIdxForVirtReg) const	llvm::TargetInstrInfo	[inline, virtual]
get(unsigned Opcode) const	llvm::MCInstrInfo	[inline]
getCallFrameDestroyOpcode() const	llvm::TargetInstrInfo	[inline]
getCallFrameSetupOpcode() const	llvm::TargetInstrInfo	[inline]
getExecutionDomain(const MachineInstr *MI) const	llvm::TargetInstrInfo	[inline, virtual]
getExtractSubregInputs(const MachineInstr &MI, unsigned DefIdx, RegSubRegPairAndIdx &InputReg) const	llvm::TargetInstrInfo
getExtractSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx, RegSubRegPairAndIdx &InputReg) const	llvm::TargetInstrInfo	[inline, protected, virtual]
getInlineAsmLength(const char *Str, const MCAsmInfo &MAI) const	llvm::TargetInstrInfo	[virtual]
getInsertSubregInputs(const MachineInstr &MI, unsigned DefIdx, RegSubRegPair &BaseReg, RegSubRegPairAndIdx &InsertedReg) const	llvm::TargetInstrInfo
getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx, RegSubRegPair &BaseReg, RegSubRegPairAndIdx &InsertedReg) const	llvm::TargetInstrInfo	[inline, protected, virtual]
getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr *MI, unsigned *PredCost=nullptr) const	llvm::TargetInstrInfo	[virtual]
getInstrLatency(const InstrItineraryData *ItinData, SDNode *Node) const	llvm::TargetInstrInfo	[virtual]
getLdStBaseRegImmOfs(MachineInstr *LdSt, unsigned &BaseReg, unsigned &Offset, const TargetRegisterInfo *TRI) const	llvm::TargetInstrInfo	[inline, virtual]
getName(unsigned Opcode) const	llvm::MCInstrInfo	[inline]
getNoopForMachoTarget(MCInst &NopInst) const	llvm::TargetInstrInfo	[virtual]
getNumMicroOps(const InstrItineraryData *ItinData, const MachineInstr *MI) const	llvm::TargetInstrInfo	[virtual]
getNumOpcodes() const	llvm::MCInstrInfo	[inline]
getOpcodeAfterMemoryUnfold(unsigned Opc, bool UnfoldLoad, bool UnfoldStore, unsigned *LoadRegIndex=nullptr) const	llvm::TargetInstrInfo	[inline, virtual]
getOperandLatency(const InstrItineraryData *ItinData, SDNode *DefNode, unsigned DefIdx, SDNode *UseNode, unsigned UseIdx) const	llvm::TargetInstrInfo	[virtual]
getOperandLatency(const InstrItineraryData *ItinData, const MachineInstr *DefMI, unsigned DefIdx, const MachineInstr *UseMI, unsigned UseIdx) const	llvm::TargetInstrInfo	[virtual]
getPartialRegUpdateClearance(const MachineInstr *MI, unsigned OpNum, const TargetRegisterInfo *TRI) const	llvm::TargetInstrInfo	[inline, virtual]
getPredicationCost(const MachineInstr *MI) const	llvm::TargetInstrInfo	[virtual]
getRegClass(const MCInstrDesc &TID, unsigned OpNum, const TargetRegisterInfo *TRI, const MachineFunction &MF) const	llvm::TargetInstrInfo
getRegSequenceInputs(const MachineInstr &MI, unsigned DefIdx, SmallVectorImpl< RegSubRegPairAndIdx > &InputRegs) const	llvm::TargetInstrInfo
getRegSequenceLikeInputs(const MachineInstr &MI, unsigned DefIdx, SmallVectorImpl< RegSubRegPairAndIdx > &InputRegs) const	llvm::TargetInstrInfo	[inline, protected, virtual]
getStackSlotRange(const TargetRegisterClass *RC, unsigned SubIdx, unsigned &Size, unsigned &Offset, const TargetMachine *TM) const	llvm::TargetInstrInfo	[virtual]
getTrap(MCInst &MI) const	llvm::TargetInstrInfo	[inline, virtual]
getUnconditionalBranch(MCInst &MI, const MCSymbolRefExpr *BranchTarget) const	llvm::TargetInstrInfo	[inline, virtual]
getUndefRegClearance(const MachineInstr *MI, unsigned &OpNum, const TargetRegisterInfo *TRI) const	llvm::TargetInstrInfo	[inline, virtual]
hasHighOperandLatency(const InstrItineraryData *ItinData, const MachineRegisterInfo *MRI, const MachineInstr *DefMI, unsigned DefIdx, const MachineInstr *UseMI, unsigned UseIdx) const	llvm::TargetInstrInfo	[inline, virtual]
hasLoadFromStackSlot(const MachineInstr *MI, const MachineMemOperand *&MMO, int &FrameIndex) const	llvm::TargetInstrInfo	[virtual]
hasLowDefLatency(const InstrItineraryData *ItinData, const MachineInstr *DefMI, unsigned DefIdx) const	llvm::TargetInstrInfo	[virtual]
hasPattern(MachineInstr &Root, SmallVectorImpl< MachineCombinerPattern::MC_PATTERN > &Pattern) const	llvm::TargetInstrInfo	[inline, virtual]
hasStoreToStackSlot(const MachineInstr *MI, const MachineMemOperand *&MMO, int &FrameIndex) const	llvm::TargetInstrInfo	[virtual]
InitMCInstrInfo(const MCInstrDesc *D, const unsigned *NI, const char *ND, unsigned NO)	llvm::MCInstrInfo	[inline]
InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl< MachineOperand > &Cond, DebugLoc DL) const	llvm::TargetInstrInfo	[inline, virtual]
insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const	llvm::TargetInstrInfo	[virtual]
insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DstReg, const SmallVectorImpl< MachineOperand > &Cond, unsigned TrueReg, unsigned FalseReg) const	llvm::TargetInstrInfo	[inline, virtual]
isAsCheapAsAMove(const MachineInstr *MI) const	llvm::TargetInstrInfo	[inline, virtual]
isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg, unsigned &SubIdx) const	llvm::TargetInstrInfo	[inline, virtual]
isHighLatencyDef(int opc) const	llvm::TargetInstrInfo	[inline, virtual]
isLegalToSplitMBBAt(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const	llvm::TargetInstrInfo	[inline, virtual]
isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const	llvm::TargetInstrInfo	[inline, virtual]
isLoadFromStackSlotPostFE(const MachineInstr *MI, int &FrameIndex) const	llvm::TargetInstrInfo	[inline, virtual]
isPredicable(MachineInstr *MI) const	llvm::TargetInstrInfo	[inline, virtual]
isPredicated(const MachineInstr *MI) const	llvm::TargetInstrInfo	[inline, virtual]
isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, const BranchProbability &Probability) const	llvm::TargetInstrInfo	[inline, virtual]
isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, const BranchProbability &Probability) const	llvm::TargetInstrInfo	[inline, virtual]
isProfitableToIfCvt(MachineBasicBlock &TMBB, unsigned NumTCycles, unsigned ExtraTCycles, MachineBasicBlock &FMBB, unsigned NumFCycles, unsigned ExtraFCycles, const BranchProbability &Probability) const	llvm::TargetInstrInfo	[inline, virtual]
isProfitableToUnpredicate(MachineBasicBlock &TMBB, MachineBasicBlock &FMBB) const	llvm::TargetInstrInfo	[inline, virtual]
isReallyTriviallyReMaterializable(const MachineInstr *MI, AliasAnalysis *AA) const	llvm::TargetInstrInfo	[inline, protected, virtual]
isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const	llvm::TargetInstrInfo	[inline, virtual]
isSchedulingBoundary(const MachineInstr *MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const	llvm::TargetInstrInfo	[virtual]
isStackSlotCopy(const MachineInstr *MI, int &DestFrameIndex, int &SrcFrameIndex) const	llvm::TargetInstrInfo	[inline, virtual]
isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const	llvm::TargetInstrInfo	[inline, virtual]
isStoreToStackSlotPostFE(const MachineInstr *MI, int &FrameIndex) const	llvm::TargetInstrInfo	[inline, virtual]
isTriviallyReMaterializable(const MachineInstr *MI, AliasAnalysis *AA=nullptr) const	llvm::TargetInstrInfo	[inline]
isUnpredicatedTerminator(const MachineInstr *MI) const	llvm::TargetInstrInfo	[virtual]
isZeroCost(unsigned Opcode) const	llvm::TargetInstrInfo	[inline]
loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const	llvm::TargetInstrInfo	[inline, virtual]
optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2, int Mask, int Value, const MachineRegisterInfo *MRI) const	llvm::TargetInstrInfo	[inline, virtual]
optimizeLoadInstr(MachineInstr *MI, const MachineRegisterInfo *MRI, unsigned &FoldAsLoadDefReg, MachineInstr *&DefMI) const	llvm::TargetInstrInfo	[inline, virtual]
optimizeSelect(MachineInstr *MI, bool PreferFalse=false) const	llvm::TargetInstrInfo	[inline, virtual]
PredicateInstruction(MachineInstr *MI, const SmallVectorImpl< MachineOperand > &Pred) const	llvm::TargetInstrInfo	[virtual]
produceSameValue(const MachineInstr *MI0, const MachineInstr *MI1, const MachineRegisterInfo *MRI=nullptr) const	llvm::TargetInstrInfo	[virtual]
reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, unsigned SubIdx, const MachineInstr *Orig, const TargetRegisterInfo &TRI) const	llvm::TargetInstrInfo	[virtual]
RemoveBranch(MachineBasicBlock &MBB) const	llvm::TargetInstrInfo	[inline, virtual]
ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail, MachineBasicBlock *NewDest) const	llvm::TargetInstrInfo	[virtual]
ReverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const	llvm::TargetInstrInfo	[inline, virtual]
setExecutionDomain(MachineInstr *MI, unsigned Domain) const	llvm::TargetInstrInfo	[inline, virtual]
shouldClusterLoads(MachineInstr *FirstLdSt, MachineInstr *SecondLdSt, unsigned NumLoads) const	llvm::TargetInstrInfo	[inline, virtual]
shouldScheduleAdjacent(MachineInstr *First, MachineInstr *Second) const	llvm::TargetInstrInfo	[inline, virtual]
shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, int64_t Offset1, int64_t Offset2, unsigned NumLoads) const	llvm::TargetInstrInfo	[inline, virtual]
storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const	llvm::TargetInstrInfo	[inline, virtual]
SubsumesPredicate(const SmallVectorImpl< MachineOperand > &Pred1, const SmallVectorImpl< MachineOperand > &Pred2) const	llvm::TargetInstrInfo	[inline, virtual]
TargetInstrInfo(int CFSetupOpcode=-1, int CFDestroyOpcode=-1)	llvm::TargetInstrInfo	[inline]
unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, unsigned Reg, bool UnfoldLoad, bool UnfoldStore, SmallVectorImpl< MachineInstr * > &NewMIs) const	llvm::TargetInstrInfo	[inline, virtual]
unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, SmallVectorImpl< SDNode * > &NewNodes) const	llvm::TargetInstrInfo	[inline, virtual]
useMachineCombiner() const	llvm::TargetInstrInfo	[inline, virtual]
usePreRAHazardRecognizer() const	llvm::TargetInstrInfo
verifyInstruction(const MachineInstr *MI, StringRef &ErrInfo) const	llvm::TargetInstrInfo	[inline, virtual]
~TargetInstrInfo()	llvm::TargetInstrInfo	[virtual]