#include <TargetInstrInfo.h>
Detailed Description
TargetInstrInfo - Interface to description of machine instruction set
Definition at line 52 of file TargetInstrInfo.h.
Constructor & Destructor Documentation
| llvm::TargetInstrInfo::TargetInstrInfo | ( | int | CFSetupOpcode = -1, |
| int | CFDestroyOpcode = -1 |
||
| ) | [inline] |
Definition at line 56 of file TargetInstrInfo.h.
| TargetInstrInfo::~TargetInstrInfo | ( | ) | [virtual] |
Definition at line 38 of file TargetInstrInfo.cpp.
Member Function Documentation
| virtual bool llvm::TargetInstrInfo::AnalyzeBranch | ( | MachineBasicBlock & | MBB, |
| MachineBasicBlock *& | TBB, | ||
| MachineBasicBlock *& | FBB, | ||
| SmallVectorImpl< MachineOperand > & | Cond, | ||
| bool | AllowModify = false |
||
| ) | const [inline, virtual] |
AnalyzeBranch - Analyze the branching code at the end of MBB, returning true if it cannot be understood (e.g. it's a switch dispatch or isn't implemented for a target). Upon success, this returns false and returns with the following information in various cases:
1. If this block ends with no branches (it just falls through to its succ) just return false, leaving TBB/FBB null. 2. If this block ends with only an unconditional branch, it sets TBB to be the destination block. 3. If this block ends with a conditional branch and it falls through to a successor block, it sets TBB to be the branch destination block and a list of operands that evaluate the condition. These operands can be passed to other TargetInstrInfo methods to create new branches. 4. If this block ends with a conditional branch followed by an unconditional branch, it returns the 'true' destination in TBB, the 'false' destination in FBB, and a list of operands that evaluate the condition. These operands can be passed to other TargetInstrInfo methods to create new branches.
Note that RemoveBranch and InsertBranch must be implemented to support cases where this method returns success.
If AllowModify is true, then this routine is allowed to modify the basic block (e.g. delete instructions after the unconditional branch).
Definition at line 380 of file TargetInstrInfo.h.
Referenced by llvm::MachineBasicBlock::canFallThrough(), FixTail(), llvm::BranchFolder::OptimizeFunction(), llvm::MachineBasicBlock::SplitCriticalEdge(), and llvm::MachineBasicBlock::updateTerminator().
| virtual bool llvm::TargetInstrInfo::analyzeCompare | ( | const MachineInstr * | MI, |
| unsigned & | SrcReg, | ||
| unsigned & | SrcReg2, | ||
| int & | Mask, | ||
| int & | Value | ||
| ) | const [inline, virtual] |
analyzeCompare - For a comparison instruction, return the source registers in SrcReg and SrcReg2 if having two register operands, and the value it compares against in CmpValue. Return true if the comparison instruction can be analyzed.
Definition at line 940 of file TargetInstrInfo.h.
| virtual bool llvm::TargetInstrInfo::analyzeSelect | ( | const MachineInstr * | MI, |
| SmallVectorImpl< MachineOperand > & | Cond, | ||
| unsigned & | TrueOp, | ||
| unsigned & | FalseOp, | ||
| bool & | Optimizable | ||
| ) | const [inline, virtual] |
analyzeSelect - Analyze the given select instruction, returning true if it cannot be understood. It is assumed that MI->isSelect() is true.
When successful, return the controlling condition and the operands that determine the true and false result values.
Result = SELECT Cond, TrueOp, FalseOp
Some targets can optimize select instructions, for example by predicating the instruction defining one of the operands. Such targets should set Optimizable.
- Parameters:
-
MI Select instruction to analyze. Cond Condition controlling the select. TrueOp Operand number of the value selected when Cond is true. FalseOp Operand number of the value selected when Cond is false. Optimizable Returned as true if MI is optimizable.
- Returns:
- False on success.
Definition at line 561 of file TargetInstrInfo.h.
References llvm::MachineInstr::getDesc(), and llvm::MCInstrDesc::isSelect().
| virtual bool llvm::TargetInstrInfo::areLoadsFromSameBasePtr | ( | SDNode * | Load1, |
| SDNode * | Load2, | ||
| int64_t & | Offset1, | ||
| int64_t & | Offset2 | ||
| ) | const [inline, virtual] |
areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to determine if two loads are loading from the same base address. It should only return true if the base pointers are the same and the only differences between the two addresses are the offset. It also returns the offsets by reference.
Definition at line 795 of file TargetInstrInfo.h.
| virtual bool llvm::TargetInstrInfo::areMemAccessesTriviallyDisjoint | ( | MachineInstr * | MIa, |
| MachineInstr * | MIb, | ||
| AliasAnalysis * | AA = nullptr |
||
| ) | const [inline, virtual] |
Definition at line 1198 of file TargetInstrInfo.h.
References llvm::MachineInstr::mayLoad(), and llvm::MachineInstr::mayStore().
Referenced by MIsNeedChainEdge().
| virtual void llvm::TargetInstrInfo::breakPartialRegDependency | ( | MachineBasicBlock::iterator | MI, |
| unsigned | OpNum, | ||
| const TargetRegisterInfo * | TRI | ||
| ) | const [inline, virtual] |
breakPartialRegDependency - Insert a dependency-breaking instruction before MI to eliminate an unwanted dependency on OpNum.
If it wasn't possible to avoid a def in the last N instructions before MI (see getPartialRegUpdateClearance), this hook will be called to break the unwanted dependency.
On x86, an xorps instruction can be used as a dependency breaker:
addps xmm1, xmm0 movaps xmm0, (rax) xorps xmm0, xmm0 cvtsi2ss rbx, xmm0
An <imp-kill> operand should be added to MI if an instruction was inserted. This ties the instructions together in the post-ra scheduler.
Definition at line 1184 of file TargetInstrInfo.h.
| bool TargetInstrInfo::canFoldMemoryOperand | ( | const MachineInstr * | MI, |
| const SmallVectorImpl< unsigned > & | Ops | ||
| ) | const [virtual] |
canFoldMemoryOperand - Returns true for the specified load / store if folding is possible.
Definition at line 380 of file TargetInstrInfo.cpp.
References canFoldCopy(), llvm::MachineInstr::isCopy(), and llvm::SmallVectorTemplateCommon< T, typename >::size().
| virtual bool llvm::TargetInstrInfo::canInsertSelect | ( | const MachineBasicBlock & | MBB, |
| const SmallVectorImpl< MachineOperand > & | Cond, | ||
| unsigned | TrueReg, | ||
| unsigned | FalseReg, | ||
| int & | CondCycles, | ||
| int & | TrueCycles, | ||
| int & | FalseCycles | ||
| ) | const [inline, virtual] |
canInsertSelect - Return true if it is possible to insert a select instruction that chooses between TrueReg and FalseReg based on the condition code in Cond.
When successful, also return the latency in cycles from TrueReg, FalseReg, and Cond to the destination register. In most cases, a select instruction will be 1 cycle, so CondCycles = TrueCycles = FalseCycles = 1
Some x86 implementations have 2-cycle cmov instructions.
- Parameters:
-
MBB Block where select instruction would be inserted. Cond Condition returned by AnalyzeBranch. TrueReg Virtual register to select when Cond is true. FalseReg Virtual register to select when Cond is false. CondCycles Latency from Cond+Branch to select output. TrueCycles Latency from TrueReg to select output. FalseCycles Latency from FalseReg to select output.
Definition at line 511 of file TargetInstrInfo.h.
| MachineInstr * TargetInstrInfo::commuteInstruction | ( | MachineInstr * | MI, |
| bool | NewMI = false |
||
| ) | const [virtual] |
commuteInstruction - If a target has any instructions that are commutable but require converting to different instructions or making non-trivial changes to commute them, this method can overloaded to do that. The default implementation simply swaps the commutable operands. If NewMI is false, MI is modified in place and returned; otherwise, a new machine instruction is created and returned. Do not call this method for a non-commutable instruction, but there may be some cases where this method fails and returns null.
Definition at line 121 of file TargetInstrInfo.cpp.
References llvm::MachineFunction::CloneMachineInstr(), findCommutedOpIndices(), llvm::MachineInstr::getDesc(), llvm::MCInstrDesc::getNumDefs(), llvm::MachineInstr::getOperand(), llvm::MCInstrDesc::getOperandConstraint(), llvm::MachineInstr::getParent(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getSubReg(), llvm::MachineInstr::isCommutable(), llvm::MachineOperand::isKill(), llvm::MachineOperand::isReg(), llvm::AArch64CC::MI, llvm::MachineOperand::setIsKill(), llvm::MachineOperand::setReg(), llvm::MachineOperand::setSubReg(), and llvm::MCOI::TIED_TO.
Referenced by llvm::PPCInstrInfo::commuteInstruction().
| int TargetInstrInfo::computeDefOperandLatency | ( | const InstrItineraryData * | ItinData, |
| const MachineInstr * | DefMI | ||
| ) | const |
If we can determine the operand latency from the def only, without itinerary lookup, do so. Otherwise return -1.
Definition at line 804 of file TargetInstrInfo.cpp.
References defaultDefLatency(), getInstrLatency(), llvm::InstrItineraryData::isEmpty(), and llvm::InstrItineraryData::SchedModel.
Referenced by computeOperandLatency().
| unsigned TargetInstrInfo::computeOperandLatency | ( | const InstrItineraryData * | ItinData, |
| const MachineInstr * | DefMI, | ||
| unsigned | DefIdx, | ||
| const MachineInstr * | UseMI, | ||
| unsigned | UseIdx | ||
| ) | const |
computeOperandLatency - Compute and return the latency of the given data dependent def and use when the operand indices are already known.
computeOperandLatency - Compute and return the latency of the given data dependent def and use when the operand indices are already known. UseMI may be NULL for an unknown use.
FindMin may be set to get the minimum vs. expected latency. Minimum latency is used for scheduling groups, while expected latency is for instruction cost and critical path.
Depending on the subtarget's itinerary properties, this may or may not need to call getOperandLatency(). For most subtargets, we don't need DefIdx or UseIdx to compute min latency.
Definition at line 831 of file TargetInstrInfo.cpp.
References computeDefOperandLatency(), defaultDefLatency(), llvm::MachineInstr::getDesc(), getInstrLatency(), llvm::InstrItineraryData::getOperandCycle(), getOperandLatency(), llvm::MCInstrDesc::getSchedClass(), llvm::InstrItineraryData::isEmpty(), and llvm::InstrItineraryData::SchedModel.
| virtual MachineInstr* llvm::TargetInstrInfo::convertToThreeAddress | ( | MachineFunction::iterator & | MFI, |
| MachineBasicBlock::iterator & | MBBI, | ||
| LiveVariables * | LV | ||
| ) | const [inline, virtual] |
convertToThreeAddress - This method must be implemented by targets that set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target may be able to convert a two-address instruction into one or more true three-address instructions on demand. This allows the X86 target (for example) to convert ADD and SHL instructions into LEA instructions if they would require register copies due to two-addressness.
This method returns a null pointer if the transformation cannot be performed, otherwise it returns the last new instruction.
Definition at line 245 of file TargetInstrInfo.h.
| virtual void llvm::TargetInstrInfo::copyPhysReg | ( | MachineBasicBlock & | MBB, |
| MachineBasicBlock::iterator | MI, | ||
| DebugLoc | DL, | ||
| unsigned | DestReg, | ||
| unsigned | SrcReg, | ||
| bool | KillSrc | ||
| ) | const [inline, virtual] |
copyPhysReg - Emit instructions to copy a pair of physical registers.
This function should support copies within any legal register class as well as any cross-class copies created during instruction selection.
The source and destination registers may overlap, which may require a careful implementation when multiple copy instructions are required for large registers. See for example the ARM target.
Definition at line 596 of file TargetInstrInfo.h.
References llvm_unreachable.
Referenced by llvm::AArch64FrameLowering::emitPrologue(), and llvm::Mips16RegisterInfo::saveScavengerRegister().
| ScheduleHazardRecognizer * TargetInstrInfo::CreateTargetHazardRecognizer | ( | const TargetSubtargetInfo * | STI, |
| const ScheduleDAG * | DAG | ||
| ) | const [virtual] |
CreateTargetHazardRecognizer - Allocate and return a hazard recognizer to use for this target when scheduling the machine instructions before register allocation.
Definition at line 678 of file TargetInstrInfo.cpp.
| ScheduleHazardRecognizer * TargetInstrInfo::CreateTargetMIHazardRecognizer | ( | const InstrItineraryData * | II, |
| const ScheduleDAG * | DAG | ||
| ) | const [virtual] |
CreateTargetMIHazardRecognizer - Allocate and return a hazard recognizer to use for this target when scheduling the machine instructions before register allocation.
Definition at line 686 of file TargetInstrInfo.cpp.
Referenced by llvm::ConvergingVLIWScheduler::initialize(), llvm::GenericScheduler::initialize(), and llvm::PostGenericScheduler::initialize().
| ScheduleHazardRecognizer * TargetInstrInfo::CreateTargetPostRAHazardRecognizer | ( | const InstrItineraryData * | II, |
| const ScheduleDAG * | DAG | ||
| ) | const [virtual] |
CreateTargetPostRAHazardRecognizer - Allocate and return a hazard recognizer to use for this target when scheduling the machine instructions after register allocation.
Definition at line 694 of file TargetInstrInfo.cpp.
Referenced by INITIALIZE_PASS().
| virtual DFAPacketizer* llvm::TargetInstrInfo::CreateTargetScheduleState | ( | const TargetMachine * | , |
| const ScheduleDAG * | |||
| ) | const [inline, virtual] |
Create machine specific model for scheduling.
Definition at line 1189 of file TargetInstrInfo.h.
Referenced by llvm::ResourcePriorityQueue::ResourcePriorityQueue(), llvm::VLIWPacketizerList::VLIWPacketizerList(), and llvm::VLIWResourceModel::VLIWResourceModel().
| unsigned TargetInstrInfo::defaultDefLatency | ( | const MCSchedModel & | SchedModel, |
| const MachineInstr * | DefMI | ||
| ) | const |
Return the default expected latency for a def based on it's opcode.
Definition at line 753 of file TargetInstrInfo.cpp.
References llvm::MachineInstr::getOpcode(), llvm::MCSchedModel::HighLatency, if(), isHighLatencyDef(), llvm::MachineInstr::isTransient(), llvm::MCSchedModel::LoadLatency, and llvm::MachineInstr::mayLoad().
Referenced by computeDefOperandLatency(), llvm::TargetSchedModel::computeInstrLatency(), llvm::TargetSchedModel::computeOperandLatency(), and computeOperandLatency().
| virtual bool llvm::TargetInstrInfo::DefinesPredicate | ( | MachineInstr * | MI, |
| std::vector< MachineOperand > & | Pred | ||
| ) | const [inline, virtual] |
DefinesPredicate - If the specified instruction defines any predicate or condition code register(s) used for predication, returns true as well as the definition predicate(s) by reference.
Definition at line 881 of file TargetInstrInfo.h.
| MachineInstr * TargetInstrInfo::duplicate | ( | MachineInstr * | Orig, |
| MachineFunction & | MF | ||
| ) | const [virtual] |
duplicate - Create a duplicate of the Orig instruction in MF. This is like MachineFunction::CloneMachineInstr(), but the target may update operands that are required to be unique.
The instruction must be duplicable as indicated by isNotDuplicable().
Definition at line 334 of file TargetInstrInfo.cpp.
References llvm::MachineFunction::CloneMachineInstr(), and llvm::MachineInstr::isNotDuplicable().
| virtual bool llvm::TargetInstrInfo::enableClusterLoads | ( | ) | const [inline, virtual] |
Definition at line 821 of file TargetInstrInfo.h.
Referenced by createGenericSchedLive().
| virtual bool llvm::TargetInstrInfo::expandPostRAPseudo | ( | MachineBasicBlock::iterator | MI | ) | const [inline, virtual] |
expandPostRAPseudo - This function is called for all pseudo instructions that remain after register allocation. Many pseudo instructions are created to help register allocation. This is the place to convert them into real instructions. The target can edit MI in place, or it can insert new instructions and erase MI. The function should return true if anything was changed.
Definition at line 636 of file TargetInstrInfo.h.
| bool TargetInstrInfo::findCommutedOpIndices | ( | MachineInstr * | MI, |
| unsigned & | SrcOpIdx1, | ||
| unsigned & | SrcOpIdx2 | ||
| ) | const [virtual] |
findCommutedOpIndices - If specified MI is commutable, return the two operand indices that would swap value. Return false if the instruction is not in a form which this routine understands.
findCommutedOpIndices - If specified MI is commutable, return the two operand indices that would swap value. Return true if the instruction is not in a form which this routine understands.
Definition at line 180 of file TargetInstrInfo.cpp.
References llvm::MachineInstr::getDesc(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::isBundle(), and llvm::MachineOperand::isReg().
Referenced by commuteInstruction().
| virtual bool llvm::TargetInstrInfo::FoldImmediate | ( | MachineInstr * | UseMI, |
| MachineInstr * | DefMI, | ||
| unsigned | Reg, | ||
| MachineRegisterInfo * | MRI | ||
| ) | const [inline, virtual] |
FoldImmediate - 'Reg' is known to be defined by a move immediate instruction, try to fold the immediate into the use instruction. If MRI->hasOneNonDBGUse(Reg) is true, and this function returns true, then the caller may assume that DefMI has been erased from its parent block. The caller may assume that it will not be erased by this function otherwise.
Definition at line 976 of file TargetInstrInfo.h.
| MachineInstr * TargetInstrInfo::foldMemoryOperand | ( | MachineBasicBlock::iterator | MI, |
| const SmallVectorImpl< unsigned > & | Ops, | ||
| int | FI | ||
| ) | const |
foldMemoryOperand - Attempt to fold a load or store of the specified stack slot into the specified machine instruction for the specified operand(s). If this is possible, a new instruction is returned with the specified operand folded, otherwise NULL is returned. The new instruction is inserted before MI, and the client is responsible for removing the old instruction.
foldMemoryOperand - Attempt to fold a load or store of the specified stack slot into the specified machine instruction for the specified operand(s). If this is possible, a new instruction is returned with the specified operand folded, otherwise NULL is returned. The client is responsible for removing the old instruction and adding the new one in the instruction stream.
Definition at line 451 of file TargetInstrInfo.cpp.
References llvm::MachineInstr::addMemOperand(), canFoldCopy(), foldMemoryOperandImpl(), foldPatchpoint(), llvm::MachinePointerInfo::getFixedStack(), llvm::MachineFunction::getFrameInfo(), llvm::MachineFunction::getMachineMemOperand(), llvm::MachineFrameInfo::getObjectAlignment(), llvm::MachineFrameInfo::getObjectOffset(), llvm::MachineFrameInfo::getObjectSize(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getReg(), llvm::TargetSubtargetInfo::getRegisterInfo(), llvm::MachineFunction::getSubtarget(), llvm::MachineBasicBlock::insert(), llvm::MachineOperand::isKill(), loadRegFromStackSlot(), llvm::MachineInstr::mayLoad(), llvm::MachineInstr::mayStore(), llvm::AArch64CC::MI, llvm::MachineMemOperand::MOLoad, llvm::MachineMemOperand::MOStore, llvm::TargetOpcode::PATCHPOINT, llvm::MachineInstr::setMemRefs(), llvm::SmallVectorTemplateCommon< T, typename >::size(), llvm::TargetOpcode::STACKMAP, and storeRegToStackSlot().
| MachineInstr * TargetInstrInfo::foldMemoryOperand | ( | MachineBasicBlock::iterator | MI, |
| const SmallVectorImpl< unsigned > & | Ops, | ||
| MachineInstr * | LoadMI | ||
| ) | const |
foldMemoryOperand - Same as the previous version except it allows folding of any load and store from / to any address, not just from a specific stack slot.
Definition at line 520 of file TargetInstrInfo.cpp.
References llvm::MachineInstr::addMemOperand(), llvm::MachineInstr::canFoldAsLoad(), foldMemoryOperandImpl(), foldPatchpoint(), llvm::ISD::FrameIndex, llvm::MachineBasicBlock::getParent(), I, llvm::MachineBasicBlock::insert(), isLoadFromStackSlot(), llvm::MachineInstr::memoperands_begin(), llvm::MachineInstr::memoperands_end(), llvm::TargetOpcode::PATCHPOINT, llvm::MachineInstr::setMemRefs(), llvm::SmallVectorTemplateCommon< T, typename >::size(), and llvm::TargetOpcode::STACKMAP.
| virtual MachineInstr* llvm::TargetInstrInfo::foldMemoryOperandImpl | ( | MachineFunction & | MF, |
| MachineInstr * | MI, | ||
| const SmallVectorImpl< unsigned > & | Ops, | ||
| int | FrameIndex | ||
| ) | const [inline, protected, virtual] |
foldMemoryOperandImpl - Target-dependent implementation for foldMemoryOperand. Target-independent code in foldMemoryOperand will take care of adding a MachineMemOperand to the newly created instruction.
Definition at line 697 of file TargetInstrInfo.h.
Referenced by foldMemoryOperand().
| virtual MachineInstr* llvm::TargetInstrInfo::foldMemoryOperandImpl | ( | MachineFunction & | MF, |
| MachineInstr * | MI, | ||
| const SmallVectorImpl< unsigned > & | Ops, | ||
| MachineInstr * | LoadMI | ||
| ) | const [inline, protected, virtual] |
foldMemoryOperandImpl - Target-dependent implementation for foldMemoryOperand. Target-independent code in foldMemoryOperand will take care of adding a MachineMemOperand to the newly created instruction.
Definition at line 707 of file TargetInstrInfo.h.
| virtual void llvm::TargetInstrInfo::genAlternativeCodeSequence | ( | MachineInstr & | Root, |
| MachineCombinerPattern::MC_PATTERN | P, | ||
| SmallVectorImpl< MachineInstr * > & | InsInstrs, | ||
| SmallVectorImpl< MachineInstr * > & | DelInstrs, | ||
| DenseMap< unsigned, unsigned > & | InstrIdxForVirtReg | ||
| ) | const [inline, virtual] |
genAlternativeCodeSequence - when hasPattern() finds a pattern this function generates the instructions that could replace the original code sequence. The client has to decide whether the actual replacementment is beneficial or not.
- Parameters:
-
Root - Instruction that could be combined with one of its operands P - Combination pattern for Root InsInstrs - Vector of new instructions that implement P DelInstrs - Old instructions, including Root, that could be replaced by InsInstr InstrIdxForVirtReg - map of virtual register to instruction in InsInstr that defines it
Definition at line 682 of file TargetInstrInfo.h.
| int llvm::TargetInstrInfo::getCallFrameDestroyOpcode | ( | ) | const [inline] |
Definition at line 110 of file TargetInstrInfo.h.
Referenced by llvm::X86FrameLowering::eliminateCallFramePseudoInstr(), FindCallSeqStart(), IsChainDependent(), and llvm::FastISel::selectStackmap().
| int llvm::TargetInstrInfo::getCallFrameSetupOpcode | ( | ) | const [inline] |
getCallFrameSetup/DestroyOpcode - These methods return the opcode of the frame setup/destroy instructions if they exist (-1 otherwise). Some targets use pseudo instructions in order to abstract away the difference between operating with a frame pointer and operating without, through the use of these two instructions.
Definition at line 109 of file TargetInstrInfo.h.
Referenced by llvm::X86FrameLowering::eliminateCallFramePseudoInstr(), FindCallSeqStart(), IsChainDependent(), and llvm::FastISel::selectStackmap().
| virtual std::pair<uint16_t, uint16_t> llvm::TargetInstrInfo::getExecutionDomain | ( | const MachineInstr * | MI | ) | const [inline, virtual] |
getExecutionDomain - Return the current execution domain and bit mask of possible domains for instruction.
Some micro-architectures have multiple execution domains, and multiple opcodes that perform the same operation in different domains. For example, the x86 architecture provides the por, orps, and orpd instructions that all do the same thing. There is a latency penalty if a register is written in one domain and read in another.
This function returns a pair (domain, mask) containing the execution domain of MI, and a bit mask of possible domains. The setExecutionDomain function can be used to change the opcode to one of the domains in the bit mask. Instructions whose execution domain can't be changed should return a 0 mask.
The execution domain numbers don't have any special meaning except domain 0 is used for instructions that are not associated with any interesting execution domain.
Definition at line 1088 of file TargetInstrInfo.h.
| bool TargetInstrInfo::getExtractSubregInputs | ( | const MachineInstr & | MI, |
| unsigned | DefIdx, | ||
| RegSubRegPairAndIdx & | InputReg | ||
| ) | const |
Build the equivalent inputs of a EXTRACT_SUBREG for the given MI and DefIdx. [out] InputReg of the equivalent EXTRACT_SUBREG. E.g., EXTRACT_SUBREG vreg1:sub1, sub0, sub1 would produce:
- vreg1:sub1, sub0
- Returns:
- true if it is possible to build such an input sequence with the pair
MI,DefIdx. False otherwise.
- Precondition:
- MI.isExtractSubreg() or MI.isExtractSubregLike().
- Note:
- The generic implementation does not provide any support for MI.isExtractSubregLike(). In other words, one has to override getExtractSubregLikeInputs for target specific instructions.
Definition at line 885 of file TargetInstrInfo.cpp.
References getExtractSubregLikeInputs(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getSubReg(), llvm::MachineInstr::isExtractSubreg(), llvm::MachineInstr::isExtractSubregLike(), llvm::MachineOperand::isImm(), llvm::TargetInstrInfo::RegSubRegPair::Reg, llvm::TargetInstrInfo::RegSubRegPairAndIdx::SubIdx, and llvm::TargetInstrInfo::RegSubRegPair::SubReg.
| virtual bool llvm::TargetInstrInfo::getExtractSubregLikeInputs | ( | const MachineInstr & | MI, |
| unsigned | DefIdx, | ||
| RegSubRegPairAndIdx & | InputReg | ||
| ) | const [inline, protected, virtual] |
Target-dependent implementation of getExtractSubregInputs.
- Returns:
- true if it is possible to build the equivalent EXTRACT_SUBREG inputs with the pair
MI,DefIdx. False otherwise.
- Precondition:
- MI.isExtractSubregLike().
- See also:
- TargetInstrInfo::getExtractSubregInputs.
Definition at line 736 of file TargetInstrInfo.h.
Referenced by getExtractSubregInputs().
| unsigned TargetInstrInfo::getInlineAsmLength | ( | const char * | Str, |
| const MCAsmInfo & | MAI | ||
| ) | const [virtual] |
Measure the specified inline asm to determine an approximation of its length.
Measure the specified inline asm to determine an approximation of its length. Comments (which run till the next SeparatorString or newline) do not count as an instruction. Any other non-whitespace text is considered an instruction, with multiple instructions separated by SeparatorString or newlines. Variable-length instructions are not handled here; this function may be overloaded in the target code to do that.
Definition at line 75 of file TargetInstrInfo.cpp.
References llvm::MCAsmInfo::getCommentString(), llvm::MCAsmInfo::getMaxInstLength(), llvm::MCAsmInfo::getSeparatorString(), llvm::LibFunc::strlen, and llvm::LibFunc::strncmp.
Referenced by llvm::MSP430InstrInfo::GetInstSizeInBytes().
| bool TargetInstrInfo::getInsertSubregInputs | ( | const MachineInstr & | MI, |
| unsigned | DefIdx, | ||
| RegSubRegPair & | BaseReg, | ||
| RegSubRegPairAndIdx & | InsertedReg | ||
| ) | const |
Build the equivalent inputs of a INSERT_SUBREG for the given MI and DefIdx. [out] BaseReg and [out] InsertedReg contain the equivalent inputs of INSERT_SUBREG. E.g., INSERT_SUBREG vreg0:sub0, vreg1:sub1, sub3 would produce:
- BaseReg: vreg0:sub0
- InsertedReg: vreg1:sub1, sub3
- Returns:
- true if it is possible to build such an input sequence with the pair
MI,DefIdx. False otherwise.
- Precondition:
- MI.isInsertSubreg() or MI.isInsertSubregLike().
- Note:
- The generic implementation does not provide any support for MI.isInsertSubregLike(). In other words, one has to override getInsertSubregLikeInputs for target specific instructions.
Definition at line 908 of file TargetInstrInfo.cpp.
References llvm::MachineOperand::getImm(), getInsertSubregLikeInputs(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::getSubReg(), llvm::MachineOperand::isImm(), llvm::MachineInstr::isInsertSubreg(), llvm::MachineInstr::isInsertSubregLike(), llvm::TargetInstrInfo::RegSubRegPair::Reg, llvm::TargetInstrInfo::RegSubRegPairAndIdx::SubIdx, and llvm::TargetInstrInfo::RegSubRegPair::SubReg.
| virtual bool llvm::TargetInstrInfo::getInsertSubregLikeInputs | ( | const MachineInstr & | MI, |
| unsigned | DefIdx, | ||
| RegSubRegPair & | BaseReg, | ||
| RegSubRegPairAndIdx & | InsertedReg | ||
| ) | const [inline, protected, virtual] |
Target-dependent implementation of getInsertSubregInputs.
- Returns:
- true if it is possible to build the equivalent INSERT_SUBREG inputs with the pair
MI,DefIdx. False otherwise.
- Precondition:
- MI.isInsertSubregLike().
- See also:
- TargetInstrInfo::getInsertSubregInputs.
Definition at line 751 of file TargetInstrInfo.h.
Referenced by getInsertSubregInputs().
| unsigned TargetInstrInfo::getInstrLatency | ( | const InstrItineraryData * | ItinData, |
| const MachineInstr * | MI, | ||
| unsigned * | PredCost = nullptr |
||
| ) | const [virtual] |
getInstrLatency - Compute the instruction latency of a given instruction. If the instruction has higher cost when predicated, it's returned via PredCost.
Definition at line 769 of file TargetInstrInfo.cpp.
References llvm::MachineInstr::getDesc(), llvm::MCInstrDesc::getSchedClass(), llvm::InstrItineraryData::getStageLatency(), and llvm::MachineInstr::mayLoad().
Referenced by computeDefOperandLatency(), llvm::TargetSchedModel::computeInstrLatency(), llvm::ScheduleDAGSDNodes::computeLatency(), llvm::TargetSchedModel::computeOperandLatency(), and computeOperandLatency().
| int TargetInstrInfo::getInstrLatency | ( | const InstrItineraryData * | ItinData, |
| SDNode * | Node | ||
| ) | const [virtual] |
Definition at line 721 of file TargetInstrInfo.cpp.
References llvm::SDNode::getMachineOpcode(), llvm::InstrItineraryData::getStageLatency(), llvm::InstrItineraryData::isEmpty(), and llvm::SDNode::isMachineOpcode().
| virtual bool llvm::TargetInstrInfo::getLdStBaseRegImmOfs | ( | MachineInstr * | LdSt, |
| unsigned & | BaseReg, | ||
| unsigned & | Offset, | ||
| const TargetRegisterInfo * | TRI | ||
| ) | const [inline, virtual] |
Get the base register and byte offset of a load/store instr.
Definition at line 815 of file TargetInstrInfo.h.
| void TargetInstrInfo::getNoopForMachoTarget | ( | MCInst & | NopInst | ) | const [virtual] |
Return the noop instruction to use for a noop.
Definition at line 375 of file TargetInstrInfo.cpp.
References llvm_unreachable.
Referenced by llvm::AsmPrinter::EmitFunctionBody().
| unsigned TargetInstrInfo::getNumMicroOps | ( | const InstrItineraryData * | ItinData, |
| const MachineInstr * | MI | ||
| ) | const [virtual] |
getNumMicroOps - Return the number of u-operations the given machine instruction will be decoded to on the target cpu. The itinerary's IssueWidth is the number of microops that can be dispatched each cycle. An instruction with zero microops takes no dispatch resources.
Definition at line 737 of file TargetInstrInfo.cpp.
References llvm::tgtok::Class, llvm::MachineInstr::getDesc(), llvm::MCInstrDesc::getSchedClass(), llvm::InstrItineraryData::isEmpty(), llvm::InstrItineraryData::Itineraries, and llvm::InstrItinerary::NumMicroOps.
Referenced by llvm::TargetSchedModel::getNumMicroOps().
| virtual unsigned llvm::TargetInstrInfo::getOpcodeAfterMemoryUnfold | ( | unsigned | Opc, |
| bool | UnfoldLoad, | ||
| bool | UnfoldStore, | ||
| unsigned * | LoadRegIndex = nullptr |
||
| ) | const [inline, virtual] |
getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new instruction after load / store are unfolded from an instruction of the specified opcode. It returns zero if the specified unfolding is not possible. If LoadRegIndex is non-null, it is filled in with the operand index of the operand which will hold the register holding the loaded value.
Definition at line 784 of file TargetInstrInfo.h.
| int TargetInstrInfo::getOperandLatency | ( | const InstrItineraryData * | ItinData, |
| SDNode * | DefNode, | ||
| unsigned | DefIdx, | ||
| SDNode * | UseNode, | ||
| unsigned | UseIdx | ||
| ) | const [virtual] |
Definition at line 705 of file TargetInstrInfo.cpp.
References llvm::SDNode::getMachineOpcode(), llvm::InstrItineraryData::getOperandCycle(), llvm::InstrItineraryData::getOperandLatency(), llvm::InstrItineraryData::isEmpty(), and llvm::SDNode::isMachineOpcode().
Referenced by llvm::ScheduleDAGSDNodes::computeOperandLatency(), llvm::TargetSchedModel::computeOperandLatency(), and computeOperandLatency().
| int TargetInstrInfo::getOperandLatency | ( | const InstrItineraryData * | ItinData, |
| const MachineInstr * | DefMI, | ||
| unsigned | DefIdx, | ||
| const MachineInstr * | UseMI, | ||
| unsigned | UseIdx | ||
| ) | const [virtual] |
getOperandLatency - Compute and return the use operand latency of a given pair of def and use. In most cases, the static scheduling itinerary was enough to determine the operand latency. But it may not be possible for instructions with variable number of defs / uses.
This is a raw interface to the itinerary that may be directly overriden by a target. Use computeOperandLatency to get the best estimate of latency.
Both DefMI and UseMI must be valid. By default, call directly to the itinerary. This may be overriden by the target.
Definition at line 794 of file TargetInstrInfo.cpp.
References llvm::MachineInstr::getDesc(), llvm::InstrItineraryData::getOperandLatency(), and llvm::MCInstrDesc::getSchedClass().
| virtual unsigned llvm::TargetInstrInfo::getPartialRegUpdateClearance | ( | const MachineInstr * | MI, |
| unsigned | OpNum, | ||
| const TargetRegisterInfo * | TRI | ||
| ) | const [inline, virtual] |
getPartialRegUpdateClearance - Returns the preferred minimum clearance before an instruction with an unwanted partial register update.
Some instructions only write part of a register, and implicitly need to read the other parts of the register. This may cause unwanted stalls preventing otherwise unrelated instructions from executing in parallel in an out-of-order CPU.
For example, the x86 instruction cvtsi2ss writes its result to bits [31:0] of the destination xmm register. Bits [127:32] are unaffected, so the instruction needs to wait for the old value of the register to become available:
addps xmm1, xmm0 movaps xmm0, (rax) cvtsi2ss rbx, xmm0
In the code above, the cvtsi2ss instruction needs to wait for the addps instruction before it can issue, even though the high bits of xmm0 probably aren't needed.
This hook returns the preferred clearance before MI, measured in instructions. Other defs of MI's operand OpNum are avoided in the last N instructions before MI. It should only return a positive value for unwanted dependencies. If the old bits of the defined register have useful values, or if MI is determined to otherwise read the dependency, the hook should return 0.
The unwanted dependency may be handled by:
1. Allocating the same register for an MI def and use. That makes the unwanted dependency identical to a required dependency.
2. Allocating a register for the def that has no defs in the previous N instructions.
3. Calling breakPartialRegDependency() with the same arguments. This allows the target to insert a dependency breaking instruction.
Definition at line 1140 of file TargetInstrInfo.h.
| unsigned TargetInstrInfo::getPredicationCost | ( | const MachineInstr * | MI | ) | const [virtual] |
Definition at line 764 of file TargetInstrInfo.cpp.
| const TargetRegisterClass * TargetInstrInfo::getRegClass | ( | const MCInstrDesc & | TID, |
| unsigned | OpNum, | ||
| const TargetRegisterInfo * | TRI, | ||
| const MachineFunction & | MF | ||
| ) | const |
getRegClass - Givem a machine instruction descriptor, returns the register class constraint for OpNum, or NULL.
Definition at line 42 of file TargetInstrInfo.cpp.
References llvm::MCInstrDesc::getNumOperands(), llvm::TargetRegisterInfo::getPointerRegClass(), llvm::TargetRegisterInfo::getRegClass(), llvm::MCOperandInfo::isLookupPtrRegClass(), llvm::MCInstrDesc::OpInfo, and llvm::MCOperandInfo::RegClass.
Referenced by llvm::FastISel::constrainOperandRegClass(), GetCostForDef(), llvm::MachineInstr::getRegClassConstraint(), llvm::PPCRegisterInfo::materializeFrameBaseRegister(), llvm::ARMBaseRegisterInfo::materializeFrameBaseRegister(), and llvm::PPCRegisterInfo::resolveFrameIndex().
| bool TargetInstrInfo::getRegSequenceInputs | ( | const MachineInstr & | MI, |
| unsigned | DefIdx, | ||
| SmallVectorImpl< RegSubRegPairAndIdx > & | InputRegs | ||
| ) | const |
Build the equivalent inputs of a REG_SEQUENCE for the given MI and DefIdx. [out] InputRegs of the equivalent REG_SEQUENCE. Each element of the list is modeled as <Reg:SubReg, SubIdx>. E.g., REG_SEQUENCE vreg1:sub1, sub0, vreg2, sub1 would produce two elements:
- vreg1:sub1, sub0
- vreg2<:0>, sub1
- Returns:
- true if it is possible to build such an input sequence with the pair
MI,DefIdx. False otherwise.
- Precondition:
- MI.isRegSequence() or MI.isRegSequenceLike().
- Note:
- The generic implementation does not provide any support for MI.isRegSequenceLike(). In other words, one has to override getRegSequenceLikeInputs for target specific instructions.
Definition at line 860 of file TargetInstrInfo.cpp.
References llvm::MachineOperand::getImm(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), getRegSequenceLikeInputs(), llvm::MachineOperand::getSubReg(), llvm::MachineOperand::isImm(), llvm::MachineInstr::isRegSequence(), llvm::MachineInstr::isRegSequenceLike(), and llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back().
| virtual bool llvm::TargetInstrInfo::getRegSequenceLikeInputs | ( | const MachineInstr & | MI, |
| unsigned | DefIdx, | ||
| SmallVectorImpl< RegSubRegPairAndIdx > & | InputRegs | ||
| ) | const [inline, protected, virtual] |
Target-dependent implementation of getRegSequenceInputs.
- Returns:
- true if it is possible to build the equivalent REG_SEQUENCE inputs with the pair
MI,DefIdx. False otherwise.
- Precondition:
- MI.isRegSequenceLike().
- See also:
- TargetInstrInfo::getRegSequenceInputs.
Definition at line 722 of file TargetInstrInfo.h.
Referenced by getRegSequenceInputs().
| bool TargetInstrInfo::getStackSlotRange | ( | const TargetRegisterClass * | RC, |
| unsigned | SubIdx, | ||
| unsigned & | Size, | ||
| unsigned & | Offset, | ||
| const TargetMachine * | TM | ||
| ) | const [virtual] |
Compute the size in bytes and offset within a stack slot of a spilled register or subregister.
- Parameters:
-
[out] Size in bytes of the spilled value. [out] Offset in bytes within the stack slot.
- Returns:
- true if both Size and Offset are successfully computed.
Not all subregisters have computable spill slots. For example, subregisters registers may not be byte-sized, and a pair of discontiguous subregisters has no single offset.
Targets with nontrivial bigendian implementations may need to override this, particularly to support spilled vector registers.
Definition at line 284 of file TargetInstrInfo.cpp.
References llvm::TargetSubtargetInfo::getDataLayout(), llvm::TargetSubtargetInfo::getRegisterInfo(), llvm::TargetRegisterClass::getSize(), llvm::MCRegisterInfo::getSubRegIdxOffset(), llvm::MCRegisterInfo::getSubRegIdxSize(), llvm::TargetMachine::getSubtargetImpl(), and llvm::DataLayout::isLittleEndian().
Referenced by foldPatchpoint().
| virtual void llvm::TargetInstrInfo::getTrap | ( | MCInst & | MI | ) | const [inline, virtual] |
getTrap - Get a machine trap instruction
Definition at line 427 of file TargetInstrInfo.h.
References llvm_unreachable.
Referenced by llvm::AsmPrinter::doFinalization().
| virtual void llvm::TargetInstrInfo::getUnconditionalBranch | ( | MCInst & | MI, |
| const MCSymbolRefExpr * | BranchTarget | ||
| ) | const [inline, virtual] |
getUnconditionalBranch - Get an instruction that performs an unconditional branch to the given symbol.
Definition at line 420 of file TargetInstrInfo.h.
References llvm_unreachable.
Referenced by llvm::AsmPrinter::doFinalization().
| virtual unsigned llvm::TargetInstrInfo::getUndefRegClearance | ( | const MachineInstr * | MI, |
| unsigned & | OpNum, | ||
| const TargetRegisterInfo * | TRI | ||
| ) | const [inline, virtual] |
Return the minimum clearance before an instruction that reads an unused register.
For example, AVX instructions may copy part of an register operand into the unused high bits of the destination register.
vcvtsi2sdq rax, xmm0<undef>, xmm14
In the code above, vcvtsi2sdq copies xmm0[127:64] into xmm14 creating a false dependence on any previous write to xmm0.
This hook works similarly to getPartialRegUpdateClearance, except that it does not take an operand index. Instead sets OpNum to the index of the unused register.
Definition at line 1160 of file TargetInstrInfo.h.
| virtual bool llvm::TargetInstrInfo::hasHighOperandLatency | ( | const InstrItineraryData * | ItinData, |
| const MachineRegisterInfo * | MRI, | ||
| const MachineInstr * | DefMI, | ||
| unsigned | DefIdx, | ||
| const MachineInstr * | UseMI, | ||
| unsigned | UseIdx | ||
| ) | const [inline, virtual] |
hasHighOperandLatency - Compute operand latency between a def of 'Reg' and an use in the current loop, return true if the target considered it 'high'. This is used by optimization passes such as machine LICM to determine whether it makes sense to hoist an instruction out even in high register pressure situation.
Definition at line 1049 of file TargetInstrInfo.h.
| bool TargetInstrInfo::hasLoadFromStackSlot | ( | const MachineInstr * | MI, |
| const MachineMemOperand *& | MMO, | ||
| int & | FrameIndex | ||
| ) | const [virtual] |
hasLoadFromStackSlot - If the specified machine instruction has a load from a stack slot, return true along with the FrameIndex of the loaded stack slot and the machine mem operand containing the reference. If not, return false. Unlike isLoadFromStackSlot, this returns true for any instructions that loads from the stack. This is just a hint, as some cases may be missed.
Definition at line 244 of file TargetInstrInfo.cpp.
References llvm::MachineInstr::memoperands_begin(), and llvm::MachineInstr::memoperands_end().
Referenced by emitComments().
| bool TargetInstrInfo::hasLowDefLatency | ( | const InstrItineraryData * | ItinData, |
| const MachineInstr * | DefMI, | ||
| unsigned | DefIdx | ||
| ) | const [virtual] |
hasLowDefLatency - Compute operand latency of a def of 'Reg', return true if the target considered it 'low'.
Definition at line 780 of file TargetInstrInfo.cpp.
References llvm::MachineInstr::getDesc(), llvm::InstrItineraryData::getOperandCycle(), llvm::MCInstrDesc::getSchedClass(), and llvm::InstrItineraryData::isEmpty().
| virtual bool llvm::TargetInstrInfo::hasPattern | ( | MachineInstr & | Root, |
| SmallVectorImpl< MachineCombinerPattern::MC_PATTERN > & | Pattern | ||
| ) | const [inline, virtual] |
hasPattern - return true when there is potentially a faster code sequence for an instruction chain ending in Root. All potential pattern are returned in the Pattern vector. Pattern should be sorted in priority order since the pattern evaluator stops checking as soon as it finds a faster sequence.
- Parameters:
-
Root - Instruction that could be combined with one of its operands Pattern - Vector of possible combination pattern
Definition at line 665 of file TargetInstrInfo.h.
| bool TargetInstrInfo::hasStoreToStackSlot | ( | const MachineInstr * | MI, |
| const MachineMemOperand *& | MMO, | ||
| int & | FrameIndex | ||
| ) | const [virtual] |
hasStoreToStackSlot - If the specified machine instruction has a store to a stack slot, return true along with the FrameIndex of the loaded stack slot and the machine mem operand containing the reference. If not, return false. Unlike isStoreToStackSlot, this returns true for any instructions that stores to the stack. This is just a hint, as some cases may be missed.
Definition at line 264 of file TargetInstrInfo.cpp.
References llvm::MachineInstr::memoperands_begin(), and llvm::MachineInstr::memoperands_end().
Referenced by emitComments().
| virtual unsigned llvm::TargetInstrInfo::InsertBranch | ( | MachineBasicBlock & | MBB, |
| MachineBasicBlock * | TBB, | ||
| MachineBasicBlock * | FBB, | ||
| const SmallVectorImpl< MachineOperand > & | Cond, | ||
| DebugLoc | DL | ||
| ) | const [inline, virtual] |
InsertBranch - Insert branch code into the end of the specified MachineBasicBlock. The operands to this method are the same as those returned by AnalyzeBranch. This is only invoked in cases where AnalyzeBranch returns success. It returns the number of instructions inserted.
It is also invoked by tail merging to add unconditional branches in cases where AnalyzeBranch doesn't apply because there was no original branch to analyze. At least this much must be implemented, else tail merging needs to be disabled.
Definition at line 404 of file TargetInstrInfo.h.
References llvm_unreachable.
Referenced by llvm::FastISel::fastEmitBranch(), FixTail(), InsertUncondBranch(), ReplaceTailWithBranchTo(), llvm::MachineBasicBlock::SplitCriticalEdge(), and llvm::MachineBasicBlock::updateTerminator().
| void TargetInstrInfo::insertNoop | ( | MachineBasicBlock & | MBB, |
| MachineBasicBlock::iterator | MI | ||
| ) | const [virtual] |
insertNoop - Insert a noop into the instruction stream at the specified point.
Definition at line 62 of file TargetInstrInfo.cpp.
References llvm_unreachable.
Referenced by llvm::ScheduleDAGSDNodes::EmitSchedule().
| virtual void llvm::TargetInstrInfo::insertSelect | ( | MachineBasicBlock & | MBB, |
| MachineBasicBlock::iterator | I, | ||
| DebugLoc | DL, | ||
| unsigned | DstReg, | ||
| const SmallVectorImpl< MachineOperand > & | Cond, | ||
| unsigned | TrueReg, | ||
| unsigned | FalseReg | ||
| ) | const [inline, virtual] |
insertSelect - Insert a select instruction into MBB before I that will copy TrueReg to DstReg when Cond is true, and FalseReg to DstReg when Cond is false.
This function can only be called after canInsertSelect() returned true. The condition in Cond comes from AnalyzeBranch, and it can be assumed that the same flags or registers required by Cond are available at the insertion point.
- Parameters:
-
MBB Block where select instruction should be inserted. I Insertion point. DL Source location for debugging. DstReg Virtual register to be defined by select instruction. Cond Condition as computed by AnalyzeBranch. TrueReg Virtual register to copy when Cond is true. FalseReg Virtual register to copy when Cons is false.
Definition at line 535 of file TargetInstrInfo.h.
References llvm_unreachable.
Referenced by llvm::PPCTargetLowering::EmitInstrWithCustomInserter().
| virtual bool llvm::TargetInstrInfo::isAsCheapAsAMove | ( | const MachineInstr * | MI | ) | const [inline, virtual] |
isAsCheapAsAMove - Return true if the instruction is as cheap as a move instruction.
Targets for different archs need to override this, and different micro-architectures can also be finely tuned inside.
Definition at line 211 of file TargetInstrInfo.h.
References llvm::MachineInstr::isAsCheapAsAMove().
Referenced by llvm::LiveRangeEdit::canRematerializeAt().
| virtual bool llvm::TargetInstrInfo::isCoalescableExtInstr | ( | const MachineInstr & | MI, |
| unsigned & | SrcReg, | ||
| unsigned & | DstReg, | ||
| unsigned & | SubIdx | ||
| ) | const [inline, virtual] |
isCoalescableExtInstr - Return true if the instruction is a "coalescable" extension instruction. That is, it's like a copy where it's legal for the source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns true, then it's expected the pre-extension value is available as a subreg of the result register. This also returns the sub-register index in SubIdx.
Definition at line 118 of file TargetInstrInfo.h.
| virtual bool llvm::TargetInstrInfo::isHighLatencyDef | ( | int | opc | ) | const [inline, virtual] |
isHighLatencyDef - Return true if this opcode has high latency to its result.
Definition at line 1041 of file TargetInstrInfo.h.
Referenced by llvm::ScheduleDAGSDNodes::computeLatency(), and defaultDefLatency().
| virtual bool llvm::TargetInstrInfo::isLegalToSplitMBBAt | ( | MachineBasicBlock & | MBB, |
| MachineBasicBlock::iterator | MBBI | ||
| ) | const [inline, virtual] |
isLegalToSplitMBBAt - Return true if it's legal to split the given basic block at the specified instruction (i.e. instruction would be the start of a new basic block).
Definition at line 434 of file TargetInstrInfo.h.
| virtual unsigned llvm::TargetInstrInfo::isLoadFromStackSlot | ( | const MachineInstr * | MI, |
| int & | FrameIndex | ||
| ) | const [inline, virtual] |
isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot, return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot. If not, return 0. This predicate must return 0 if the instruction has any side effects other than loading from the stack slot.
Definition at line 129 of file TargetInstrInfo.h.
Referenced by foldMemoryOperand(), and MatchingStackOffset().
| virtual unsigned llvm::TargetInstrInfo::isLoadFromStackSlotPostFE | ( | const MachineInstr * | MI, |
| int & | FrameIndex | ||
| ) | const [inline, virtual] |
isLoadFromStackSlotPostFE - Check for post-frame ptr elimination stack locations as well. This uses a heuristic so it isn't reliable for correctness.
Definition at line 137 of file TargetInstrInfo.h.
Referenced by emitComments().
| virtual bool llvm::TargetInstrInfo::isPredicable | ( | MachineInstr * | MI | ) | const [inline, virtual] |
isPredicable - Return true if the specified instruction can be predicated. By default, this returns true for every instruction with a PredicateOperand.
Definition at line 889 of file TargetInstrInfo.h.
References llvm::MachineInstr::getDesc(), and llvm::MCInstrDesc::isPredicable().
| virtual bool llvm::TargetInstrInfo::isPredicated | ( | const MachineInstr * | MI | ) | const [inline, virtual] |
isPredicated - Returns true if the instruction is already predicated.
Definition at line 856 of file TargetInstrInfo.h.
Referenced by llvm::CriticalAntiDepBreaker::BreakAntiDependencies(), llvm::MachineBasicBlock::canFallThrough(), llvm::TargetSchedModel::computeOutputLatency(), findHoistingInsertPosAndDeps(), and isUnpredicatedTerminator().
| virtual bool llvm::TargetInstrInfo::isProfitableToDupForIfCvt | ( | MachineBasicBlock & | MBB, |
| unsigned | NumCycles, | ||
| const BranchProbability & | Probability | ||
| ) | const [inline, virtual] |
isProfitableToDupForIfCvt - Return true if it's profitable for if-converter to duplicate instructions of specified accumulated instruction latencies in the specified MBB to enable if-conversion. The probability of the instructions being executed is given by Probability, and Confidence is a measure of our confidence that it will be properly predicted.
Definition at line 473 of file TargetInstrInfo.h.
| virtual bool llvm::TargetInstrInfo::isProfitableToIfCvt | ( | MachineBasicBlock & | MBB, |
| unsigned | NumCycles, | ||
| unsigned | ExtraPredCycles, | ||
| const BranchProbability & | Probability | ||
| ) | const [inline, virtual] |
isProfitableToIfCvt - Return true if it's profitable to predicate instructions with accumulated instruction latency of "NumCycles" of the specified basic block, where the probability of the instructions being executed is given by Probability, and Confidence is a measure of our confidence that it will be properly predicted.
Definition at line 445 of file TargetInstrInfo.h.
| virtual bool llvm::TargetInstrInfo::isProfitableToIfCvt | ( | MachineBasicBlock & | TMBB, |
| unsigned | NumTCycles, | ||
| unsigned | ExtraTCycles, | ||
| MachineBasicBlock & | FMBB, | ||
| unsigned | NumFCycles, | ||
| unsigned | ExtraFCycles, | ||
| const BranchProbability & | Probability | ||
| ) | const [inline, virtual] |
isProfitableToIfCvt - Second variant of isProfitableToIfCvt, this one checks for the case where two basic blocks from true and false path of a if-then-else (diamond) are predicated on mutally exclusive predicates, where the probability of the true path being taken is given by Probability, and Confidence is a measure of our confidence that it will be properly predicted.
Definition at line 458 of file TargetInstrInfo.h.
| virtual bool llvm::TargetInstrInfo::isProfitableToUnpredicate | ( | MachineBasicBlock & | TMBB, |
| MachineBasicBlock & | FMBB | ||
| ) | const [inline, virtual] |
isProfitableToUnpredicate - Return true if it's profitable to unpredicate one side of a 'diamond', i.e. two sides of if-else predicated on mutually exclusive predicates. e.g. subeq r0, r1, #1 addne r0, r1, #1 => sub r0, r1, #1 addne r0, r1, #1
This may be profitable is conditional instructions are always executed.
Definition at line 489 of file TargetInstrInfo.h.
| virtual bool llvm::TargetInstrInfo::isReallyTriviallyReMaterializable | ( | const MachineInstr * | MI, |
| AliasAnalysis * | AA | ||
| ) | const [inline, protected, virtual] |
isReallyTriviallyReMaterializable - For instructions with opcodes for which the M_REMATERIALIZABLE flag is set, this hook lets the target specify whether the instruction is actually trivially rematerializable, taking into consideration its operands. This predicate must return false if the instruction has any side effects other than producing a value, or if it requres any address registers that are not always available.
Definition at line 88 of file TargetInstrInfo.h.
Referenced by isTriviallyReMaterializable().
| virtual bool llvm::TargetInstrInfo::isSafeToMoveRegClassDefs | ( | const TargetRegisterClass * | RC | ) | const [inline, virtual] |
isSafeToMoveRegClassDefs - Return true if it's safe to move a machine instruction that defines the specified register class.
Definition at line 895 of file TargetInstrInfo.h.
| bool TargetInstrInfo::isSchedulingBoundary | ( | const MachineInstr * | MI, |
| const MachineBasicBlock * | MBB, | ||
| const MachineFunction & | MF | ||
| ) | const [virtual] |
isSchedulingBoundary - Test if the given instruction should be considered a scheduling boundary. This primarily includes labels and terminators.
Definition at line 650 of file TargetInstrInfo.cpp.
References llvm::TargetSubtargetInfo::getRegisterInfo(), llvm::TargetLoweringBase::getStackPointerRegisterToSaveRestore(), llvm::MachineFunction::getSubtarget(), llvm::TargetSubtargetInfo::getTargetLowering(), llvm::MachineInstr::isPosition(), llvm::MachineInstr::isTerminator(), and llvm::MachineInstr::modifiesRegister().
Referenced by isSchedBoundary().
| virtual bool llvm::TargetInstrInfo::isStackSlotCopy | ( | const MachineInstr * | MI, |
| int & | DestFrameIndex, | ||
| int & | SrcFrameIndex | ||
| ) | const [inline, virtual] |
isStackSlotCopy - Return true if the specified machine instruction is a copy of one stack slot to another and has no other effect. Provide the identity of the two frame indices.
Definition at line 184 of file TargetInstrInfo.h.
| virtual unsigned llvm::TargetInstrInfo::isStoreToStackSlot | ( | const MachineInstr * | MI, |
| int & | FrameIndex | ||
| ) | const [inline, virtual] |
isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot, return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot. If not, return 0. This predicate must return 0 if the instruction has any side effects other than storing to the stack slot.
Definition at line 158 of file TargetInstrInfo.h.
| virtual unsigned llvm::TargetInstrInfo::isStoreToStackSlotPostFE | ( | const MachineInstr * | MI, |
| int & | FrameIndex | ||
| ) | const [inline, virtual] |
isStoreToStackSlotPostFE - Check for post-frame ptr elimination stack locations as well. This uses a heuristic so it isn't reliable for correctness.
Definition at line 166 of file TargetInstrInfo.h.
Referenced by emitComments().
| bool llvm::TargetInstrInfo::isTriviallyReMaterializable | ( | const MachineInstr * | MI, |
| AliasAnalysis * | AA = nullptr |
||
| ) | const [inline] |
isTriviallyReMaterializable - Return true if the instruction is trivially rematerializable, meaning it has no side effects and requires no operands that aren't always available.
Definition at line 73 of file TargetInstrInfo.h.
References llvm::MachineInstr::getDesc(), llvm::MachineInstr::getOpcode(), llvm::TargetOpcode::IMPLICIT_DEF, isReallyTriviallyReMaterializable(), and llvm::MCInstrDesc::isRematerializable().
Referenced by llvm::LiveRangeEdit::checkRematerializable(), and isRematerializable().
| bool TargetInstrInfo::isUnpredicatedTerminator | ( | const MachineInstr * | MI | ) | const [virtual] |
isUnpredicatedTerminator - Returns true if the instruction is a terminator instruction that has not been predicated.
Definition at line 202 of file TargetInstrInfo.cpp.
References llvm::MachineInstr::isBarrier(), llvm::MachineInstr::isBranch(), llvm::MachineInstr::isPredicable(), isPredicated(), and llvm::MachineInstr::isTerminator().
Referenced by findHoistingInsertPosAndDeps().
| bool llvm::TargetInstrInfo::isZeroCost | ( | unsigned | Opcode | ) | const [inline] |
isZeroCost - Return true for pseudo instructions that don't consume any machine resources in their current form. These are common cases that the scheduler should consider free, rather than conservatively handling them as instructions with no itinerary.
Definition at line 992 of file TargetInstrInfo.h.
References llvm::TargetOpcode::COPY.
Referenced by llvm::ScoreboardHazardRecognizer::EmitInstruction().
| virtual void llvm::TargetInstrInfo::loadRegFromStackSlot | ( | MachineBasicBlock & | MBB, |
| MachineBasicBlock::iterator | MI, | ||
| unsigned | DestReg, | ||
| int | FrameIndex, | ||
| const TargetRegisterClass * | RC, | ||
| const TargetRegisterInfo * | TRI | ||
| ) | const [inline, virtual] |
loadRegFromStackSlot - Load the specified register of the given register class from the specified stack frame index. The load instruction is to be added to the given machine basic block before the specified machine instruction.
Definition at line 621 of file TargetInstrInfo.h.
References llvm_unreachable.
Referenced by foldMemoryOperand(), llvm::SystemZFrameLowering::restoreCalleeSavedRegisters(), llvm::XCoreFrameLowering::restoreCalleeSavedRegisters(), llvm::HexagonFrameLowering::restoreCalleeSavedRegisters(), llvm::X86FrameLowering::restoreCalleeSavedRegisters(), and llvm::RegScavenger::scavengeRegister().
| virtual bool llvm::TargetInstrInfo::optimizeCompareInstr | ( | MachineInstr * | CmpInstr, |
| unsigned | SrcReg, | ||
| unsigned | SrcReg2, | ||
| int | Mask, | ||
| int | Value, | ||
| const MachineRegisterInfo * | MRI | ||
| ) | const [inline, virtual] |
optimizeCompareInstr - See if the comparison instruction can be converted into something more efficient. E.g., on ARM most instructions can set the flags register, obviating the need for a separate CMP.
Definition at line 949 of file TargetInstrInfo.h.
| virtual MachineInstr* llvm::TargetInstrInfo::optimizeLoadInstr | ( | MachineInstr * | MI, |
| const MachineRegisterInfo * | MRI, | ||
| unsigned & | FoldAsLoadDefReg, | ||
| MachineInstr *& | DefMI | ||
| ) | const [inline, virtual] |
optimizeLoadInstr - Try to remove the load by folding it to a register operand at the use. We fold the load instructions if and only if the def and use are in the same BB. We only look at one load and see whether it can be folded into MI. FoldAsLoadDefReg is the virtual register defined by the load we are trying to fold. DefMI returns the machine instruction that defines FoldAsLoadDefReg, and the function returns the machine instruction generated due to folding.
Definition at line 963 of file TargetInstrInfo.h.
| virtual MachineInstr* llvm::TargetInstrInfo::optimizeSelect | ( | MachineInstr * | MI, |
| bool | PreferFalse = false |
||
| ) | const [inline, virtual] |
optimizeSelect - Given a select instruction that was understood by analyzeSelect and returned Optimizable = true, attempt to optimize MI by merging it with one of its operands. Returns NULL on failure.
When successful, returns the new select instruction. The client is responsible for deleting MI.
If both sides of the select can be optimized, PreferFalse is used to pick a side.
- Parameters:
-
MI Optimizable select instruction. PreferFalse Try to optimize FalseOp instead of TrueOp.
- Returns:
- Optimized instruction or NULL.
Definition at line 582 of file TargetInstrInfo.h.
References llvm_unreachable.
| bool TargetInstrInfo::PredicateInstruction | ( | MachineInstr * | MI, |
| const SmallVectorImpl< MachineOperand > & | Pred | ||
| ) | const [virtual] |
PredicateInstruction - Convert the instruction into a predicated instruction. It returns true if the operation was successful.
Definition at line 214 of file TargetInstrInfo.cpp.
References llvm::MachineInstr::getDesc(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOperand(), getReg(), llvm::MachineInstr::isBundle(), llvm::MachineOperand::isImm(), llvm::MachineOperand::isMBB(), llvm::MachineInstr::isPredicable(), llvm::MachineOperand::isReg(), llvm::MachineOperand::setImm(), llvm::MachineOperand::setMBB(), and llvm::MachineOperand::setReg().
| bool TargetInstrInfo::produceSameValue | ( | const MachineInstr * | MI0, |
| const MachineInstr * | MI1, | ||
| const MachineRegisterInfo * | MRI = nullptr |
||
| ) | const [virtual] |
produceSameValue - Return true if two machine instructions would produce identical values. By default, this is only true when the two instructions are deemed identical except for defs. If this function is called when the IR is still in SSA form, the caller can pass the MachineRegisterInfo for aggressive checks.
Definition at line 328 of file TargetInstrInfo.cpp.
References llvm::MachineInstr::IgnoreVRegDefs, and llvm::MachineInstr::isIdenticalTo().
| void TargetInstrInfo::reMaterialize | ( | MachineBasicBlock & | MBB, |
| MachineBasicBlock::iterator | MI, | ||
| unsigned | DestReg, | ||
| unsigned | SubIdx, | ||
| const MachineInstr * | Orig, | ||
| const TargetRegisterInfo & | TRI | ||
| ) | const [virtual] |
reMaterialize - Re-issue the specified 'original' instruction at the specific location targeting a new destination register. The register in Orig->getOperand(0).getReg() will be substituted by DestReg:SubIdx. Any existing subreg index is preserved or composed with SubIdx.
Definition at line 316 of file TargetInstrInfo.cpp.
References llvm::MachineFunction::CloneMachineInstr(), llvm::MachineInstr::getOperand(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getReg(), llvm::MachineBasicBlock::insert(), llvm::AArch64CC::MI, and llvm::MachineInstr::substituteRegister().
Referenced by llvm::LiveRangeEdit::rematerializeAt().
| virtual unsigned llvm::TargetInstrInfo::RemoveBranch | ( | MachineBasicBlock & | MBB | ) | const [inline, virtual] |
RemoveBranch - Remove the branching code at the end of the specific MBB. This is only invoked in cases where AnalyzeBranch returns success. It returns the number of instructions that were removed.
Definition at line 390 of file TargetInstrInfo.h.
References llvm_unreachable.
Referenced by FixTail(), and llvm::MachineBasicBlock::updateTerminator().
| void TargetInstrInfo::ReplaceTailWithBranchTo | ( | MachineBasicBlock::iterator | Tail, |
| MachineBasicBlock * | NewDest | ||
| ) | const [virtual] |
ReplaceTailWithBranchTo - Delete the instruction OldInst and everything after it, replacing it with an unconditional branch to NewDest. This is used by the tail merging pass.
ReplaceTailWithBranchTo - Delete the instruction OldInst and everything after it, replacing it with an unconditional branch to NewDest.
Definition at line 101 of file TargetInstrInfo.cpp.
References llvm::MachineBasicBlock::addSuccessor(), llvm::MachineBasicBlock::end(), llvm::MachineBasicBlock::erase(), llvm::MachineBasicBlock::getParent(), InsertBranch(), llvm::MachineBasicBlock::removeSuccessor(), llvm::MachineBasicBlock::succ_begin(), and llvm::MachineBasicBlock::succ_empty().
| virtual bool llvm::TargetInstrInfo::ReverseBranchCondition | ( | SmallVectorImpl< MachineOperand > & | Cond | ) | const [inline, virtual] |
ReverseBranchCondition - Reverses the branch condition of the specified condition list, returning false on success and true if it cannot be reversed.
Definition at line 840 of file TargetInstrInfo.h.
Referenced by FixTail(), and llvm::MachineBasicBlock::updateTerminator().
| virtual void llvm::TargetInstrInfo::setExecutionDomain | ( | MachineInstr * | MI, |
| unsigned | Domain | ||
| ) | const [inline, virtual] |
setExecutionDomain - Change the opcode of MI to execute in Domain.
The bit (1 << Domain) must be set in the mask returned from getExecutionDomain(MI).
Definition at line 1097 of file TargetInstrInfo.h.
| virtual bool llvm::TargetInstrInfo::shouldClusterLoads | ( | MachineInstr * | FirstLdSt, |
| MachineInstr * | SecondLdSt, | ||
| unsigned | NumLoads | ||
| ) | const [inline, virtual] |
Definition at line 823 of file TargetInstrInfo.h.
| virtual bool llvm::TargetInstrInfo::shouldScheduleAdjacent | ( | MachineInstr * | First, |
| MachineInstr * | Second | ||
| ) | const [inline, virtual] |
Can this target fuse the given instructions if they are scheduled adjacent.
Definition at line 831 of file TargetInstrInfo.h.
| virtual bool llvm::TargetInstrInfo::shouldScheduleLoadsNear | ( | SDNode * | Load1, |
| SDNode * | Load2, | ||
| int64_t | Offset1, | ||
| int64_t | Offset2, | ||
| unsigned | NumLoads | ||
| ) | const [inline, virtual] |
shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to determine (in conjunction with areLoadsFromSameBasePtr) if two loads should be scheduled togther. On some targets if two loads are loading from addresses in the same cache line, it's better if they are scheduled together. This function takes two integers that represent the load offsets from the common base address. It returns true if it decides it's desirable to schedule the two loads together. "NumLoads" is the number of loads that have already been scheduled after Load1.
Definition at line 808 of file TargetInstrInfo.h.
| virtual void llvm::TargetInstrInfo::storeRegToStackSlot | ( | MachineBasicBlock & | MBB, |
| MachineBasicBlock::iterator | MI, | ||
| unsigned | SrcReg, | ||
| bool | isKill, | ||
| int | FrameIndex, | ||
| const TargetRegisterClass * | RC, | ||
| const TargetRegisterInfo * | TRI | ||
| ) | const [inline, virtual] |
storeRegToStackSlot - Store the specified register of the given register class to the specified stack frame index. The store instruction is to be added to the given machine basic block before the specified machine instruction. If isKill is true, the register operand is the last use and must be marked kill.
Definition at line 608 of file TargetInstrInfo.h.
References llvm_unreachable.
Referenced by foldMemoryOperand(), llvm::RegScavenger::scavengeRegister(), llvm::HexagonFrameLowering::spillCalleeSavedRegisters(), llvm::SystemZFrameLowering::spillCalleeSavedRegisters(), llvm::MipsSEFrameLowering::spillCalleeSavedRegisters(), llvm::XCoreFrameLowering::spillCalleeSavedRegisters(), and llvm::X86FrameLowering::spillCalleeSavedRegisters().
| virtual bool llvm::TargetInstrInfo::SubsumesPredicate | ( | const SmallVectorImpl< MachineOperand > & | Pred1, |
| const SmallVectorImpl< MachineOperand > & | Pred2 | ||
| ) | const [inline, virtual] |
SubsumesPredicate - Returns true if the first specified predicate subsumes the second, e.g. GE subsumes GT.
Definition at line 873 of file TargetInstrInfo.h.
| virtual bool llvm::TargetInstrInfo::unfoldMemoryOperand | ( | MachineFunction & | MF, |
| MachineInstr * | MI, | ||
| unsigned | Reg, | ||
| bool | UnfoldLoad, | ||
| bool | UnfoldStore, | ||
| SmallVectorImpl< MachineInstr * > & | NewMIs | ||
| ) | const [inline, virtual] |
unfoldMemoryOperand - Separate a single instruction which folded a load or a store or a load and a store into two or more instruction. If this is possible, returns true as well as the new instructions by reference.
Definition at line 767 of file TargetInstrInfo.h.
| virtual bool llvm::TargetInstrInfo::unfoldMemoryOperand | ( | SelectionDAG & | DAG, |
| SDNode * | N, | ||
| SmallVectorImpl< SDNode * > & | NewNodes | ||
| ) | const [inline, virtual] |
Definition at line 773 of file TargetInstrInfo.h.
| virtual bool llvm::TargetInstrInfo::useMachineCombiner | ( | ) | const [inline, virtual] |
useMachineCombiner - return true when a target supports MachineCombiner
Definition at line 691 of file TargetInstrInfo.h.
Provide a global flag for disabling the PreRA hazard recognizer that targets may choose to honor.
Definition at line 672 of file TargetInstrInfo.cpp.
References DisableHazardRecognizer.
| virtual bool llvm::TargetInstrInfo::verifyInstruction | ( | const MachineInstr * | MI, |
| StringRef & | ErrInfo | ||
| ) | const [inline, virtual] |
verifyInstruction - Perform target specific instruction verification.
Definition at line 1064 of file TargetInstrInfo.h.
Referenced by llvm::AMDGPUAsmPrinter::EmitInstruction().
The documentation for this class was generated from the following files:
1.7.6.1