llvm::AMDGPU Namespace Reference

Enumerations
enum	TargetIndex { TI_CONSTDATA_START }
enum	Fixups {   fixup_si_sopp_br = FirstTargetFixupKind, fixup_si_rodata, fixup_si_end_of_text, LastTargetFixupKind,   NumTargetFixupKinds = LastTargetFixupKind - FirstTargetFixupKind }
Functions
int	getMCOpcode (uint16_t Opcode, unsigned Gen)
int16_t	getNamedOperandIdx (uint16_t Opcode, uint16_t NamedIndex)
int	getLDSNoRetOp (uint16_t Opcode)
int	isDS (uint16_t Opcode)
int	getVOPe64 (uint16_t Opcode)
int	getVOPe32 (uint16_t Opcode)
int	getCommuteRev (uint16_t Opcode)
int	getCommuteOrig (uint16_t Opcode)
int	getAddr64Inst (uint16_t Opcode)
int	getAtomicRetOp (uint16_t Opcode)
int	getAtomicNoRetOp (uint16_t Opcode)
Variables
const uint64_t	RSRC_DATA_FORMAT = 0xf00000000000LL
const uint64_t	RSRC_TID_ENABLE = 1LL << 55

---

Enumeration Type Documentation

enum llvm::AMDGPU::Fixups

Enumerator:

fixup_si_sopp_br	16-bit PC relative fixup for SOPP branch instructions.
fixup_si_rodata	fixup for global addresses with constant initializers
fixup_si_end_of_text	fixup for offset from instruction to end of text section
LastTargetFixupKind
NumTargetFixupKinds

Definition at line 17 of file AMDGPUFixupKinds.h.

enum llvm::AMDGPU::TargetIndex

Enumerator:

TI_CONSTDATA_START

Definition at line 68 of file AMDGPU.h.

---

Function Documentation

int llvm::AMDGPU::getAddr64Inst

(

uint16_t

Opcode

)

Referenced by llvm::SIInstrInfo::legalizeOperands().

int llvm::AMDGPU::getAtomicNoRetOp

(

uint16_t

Opcode

)

Referenced by llvm::SITargetLowering::AdjustInstrPostInstrSelection().

int llvm::AMDGPU::getAtomicRetOp

(

uint16_t

Opcode

)

int llvm::AMDGPU::getCommuteOrig

(

uint16_t

Opcode

)

Referenced by llvm::SIInstrInfo::commuteOpcode().

int llvm::AMDGPU::getCommuteRev

(

uint16_t

Opcode

)

Referenced by llvm::SIInstrInfo::commuteOpcode().

int llvm::AMDGPU::getLDSNoRetOp

(

uint16_t

Opcode

)

Referenced by llvm::R600TargetLowering::EmitInstrWithCustomInserter().

int llvm::AMDGPU::getMCOpcode	(	uint16_t	Opcode,
		unsigned	Gen
	)

Definition at line 359 of file AMDGPUInstrInfo.cpp.

int16_t llvm::AMDGPU::getNamedOperandIdx	(	uint16_t	Opcode,
		uint16_t	NamedIndex
	)

Referenced by llvm::SIInstrInfo::areLoadsFromSameBasePtr(), llvm::AMDGPUInstrInfo::expandPostRAPseudo(), llvm::SIInstrInfo::getLdStBaseRegImmOfs(), llvm::SIInstrInfo::getNamedOperand(), llvm::R600InstrInfo::getOperandIdx(), llvm::SIInstrInfo::hasModifiers(), llvm::SIInstrInfo::legalizeOperands(), nodesHaveSameOperandValue(), and llvm::SIInstrInfo::verifyInstruction().

int llvm::AMDGPU::getVOPe32

(

uint16_t

Opcode

)

Referenced by llvm::SIInstrInfo::hasVALU32BitEncoding().

int llvm::AMDGPU::getVOPe64

(

uint16_t

Opcode

)

int llvm::AMDGPU::isDS

(

uint16_t

Opcode

)

---

Variable Documentation

const uint64_t llvm::AMDGPU::RSRC_DATA_FORMAT = 0xf00000000000LL

Definition at line 231 of file SIInstrInfo.h.

Referenced by buildScratchRSRC(), llvm::SITargetLowering::EmitInstrWithCustomInserter(), llvm::SIInstrInfo::legalizeOperands(), and llvm::SIInstrInfo::moveSMRDToVALU().

const uint64_t llvm::AMDGPU::RSRC_TID_ENABLE = 1LL << 55

Definition at line 232 of file SIInstrInfo.h.

Referenced by buildScratchRSRC().