llvm::TargetOpcode Namespace Reference

Enumerations
enum	{   PHI = 0, INLINEASM = 1, CFI_INSTRUCTION = 2, EH_LABEL = 3,   GC_LABEL = 4, KILL = 5, EXTRACT_SUBREG = 6, INSERT_SUBREG = 7,   IMPLICIT_DEF = 8, SUBREG_TO_REG = 9, COPY_TO_REGCLASS = 10, DBG_VALUE = 11,   REG_SEQUENCE = 12, COPY = 13, BUNDLE = 14, LIFETIME_START = 15,   LIFETIME_END = 16, STACKMAP = 17, PATCHPOINT = 18, LOAD_STACK_GUARD = 19 }

---

Detailed Description

Invariant opcodes: All instruction sets have these as their low opcodes.

Every instruction defined here must also appear in Target.td and the order must be the same as in CodeGenTarget.cpp.

---

Enumeration Type Documentation

anonymous enum

Enumerator:

PHI
INLINEASM
CFI_INSTRUCTION
EH_LABEL
GC_LABEL
KILL	KILL - This instruction is a noop that is used only to adjust the liveness of registers. This can be useful when dealing with sub-registers.
EXTRACT_SUBREG	EXTRACT_SUBREG - This instruction takes two operands: a register that has subregisters, and a subregister index. It returns the extracted subregister value. This is commonly used to implement truncation operations on target architectures which support it.
INSERT_SUBREG	INSERT_SUBREG - This instruction takes three operands: a register that has subregisters, a register providing an insert value, and a subregister index. It returns the value of the first register with the value of the second register inserted. The first register is often defined by an IMPLICIT_DEF, because it is commonly used to implement anyext operations on target architectures which support it.
IMPLICIT_DEF	IMPLICIT_DEF - This is the MachineInstr-level equivalent of undef.
SUBREG_TO_REG	SUBREG_TO_REG - This instruction is similar to INSERT_SUBREG except that the first operand is an immediate integer constant. This constant is often zero, because it is commonly used to assert that the instruction defining the register implicitly clears the high bits.
COPY_TO_REGCLASS	COPY_TO_REGCLASS - This instruction is a placeholder for a plain register-to-register copy into a specific register class. This is only used between instruction selection and MachineInstr creation, before virtual registers have been created for all the instructions, and it's only needed in cases where the register classes implied by the instructions are insufficient. It is emitted as a COPY MachineInstr.
DBG_VALUE	DBG_VALUE - a mapping of the llvm.dbg.value intrinsic.
REG_SEQUENCE	REG_SEQUENCE - This variadic instruction is used to form a register that represents a consecutive sequence of sub-registers. It's used as a register coalescing / allocation aid and must be eliminated before code emission. e.g. v1027 = REG_SEQUENCE v1024, 3, v1025, 4, v1026, 5 After register coalescing references of v1024 should be replace with v1027:3, v1025 with v1027:4, etc.
COPY	COPY - Target-independent register copy. This instruction can also be used to copy between subregisters of virtual registers.
BUNDLE	BUNDLE - This instruction represents an instruction bundle. Instructions which immediately follow a BUNDLE instruction which are marked with 'InsideBundle' flag are inside the bundle.
LIFETIME_START	Lifetime markers.
LIFETIME_END
STACKMAP	A Stackmap instruction captures the location of live variables at its position in the instruction stream. It is followed by a shadow of bytes that must lie within the function and not contain another stackmap.
PATCHPOINT	Patchable call instruction - this instruction represents a call to a constant address, followed by a series of NOPs. It is intended to support optimizations for dynamic languages (such as javascript) that rewrite calls to runtimes with more efficient code sequences. This also implies a stack map.
LOAD_STACK_GUARD	This pseudo-instruction loads the stack guard value. Targets which need to prevent the stack guard value or address from being spilled to the stack should override TargetLowering::emitLoadStackGuardNode and additionally expand this pseudo after register allocation.

Definition at line 25 of file TargetOpcodes.h.