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ad9832.c
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1 /*
2  * AD9832 SPI DDS driver
3  *
4  * Copyright 2011 Analog Devices Inc.
5  *
6  * Licensed under the GPL-2.
7  */
8 
9 #include <linux/device.h>
10 #include <linux/kernel.h>
11 #include <linux/slab.h>
12 #include <linux/sysfs.h>
13 #include <linux/spi/spi.h>
14 #include <linux/regulator/consumer.h>
15 #include <linux/err.h>
16 #include <linux/module.h>
17 #include <asm/div64.h>
18 
19 #include <linux/iio/iio.h>
20 #include <linux/iio/sysfs.h>
21 #include "dds.h"
22 
23 #include "ad9832.h"
24 
25 static unsigned long ad9832_calc_freqreg(unsigned long mclk, unsigned long fout)
26 {
27  unsigned long long freqreg = (u64) fout *
28  (u64) ((u64) 1L << AD9832_FREQ_BITS);
29  do_div(freqreg, mclk);
30  return freqreg;
31 }
32 
33 static int ad9832_write_frequency(struct ad9832_state *st,
34  unsigned addr, unsigned long fout)
35 {
36  unsigned long regval;
37 
38  if (fout > (st->mclk / 2))
39  return -EINVAL;
40 
41  regval = ad9832_calc_freqreg(st->mclk, fout);
42 
43  st->freq_data[0] = cpu_to_be16((AD9832_CMD_FRE8BITSW << CMD_SHIFT) |
44  (addr << ADD_SHIFT) |
45  ((regval >> 24) & 0xFF));
46  st->freq_data[1] = cpu_to_be16((AD9832_CMD_FRE16BITSW << CMD_SHIFT) |
47  ((addr - 1) << ADD_SHIFT) |
48  ((regval >> 16) & 0xFF));
49  st->freq_data[2] = cpu_to_be16((AD9832_CMD_FRE8BITSW << CMD_SHIFT) |
50  ((addr - 2) << ADD_SHIFT) |
51  ((regval >> 8) & 0xFF));
52  st->freq_data[3] = cpu_to_be16((AD9832_CMD_FRE16BITSW << CMD_SHIFT) |
53  ((addr - 3) << ADD_SHIFT) |
54  ((regval >> 0) & 0xFF));
55 
56  return spi_sync(st->spi, &st->freq_msg);
57 }
58 
59 static int ad9832_write_phase(struct ad9832_state *st,
60  unsigned long addr, unsigned long phase)
61 {
62  if (phase > (1 << AD9832_PHASE_BITS))
63  return -EINVAL;
64 
65  st->phase_data[0] = cpu_to_be16((AD9832_CMD_PHA8BITSW << CMD_SHIFT) |
66  (addr << ADD_SHIFT) |
67  ((phase >> 8) & 0xFF));
68  st->phase_data[1] = cpu_to_be16((AD9832_CMD_PHA16BITSW << CMD_SHIFT) |
69  ((addr - 1) << ADD_SHIFT) |
70  (phase & 0xFF));
71 
72  return spi_sync(st->spi, &st->phase_msg);
73 }
74 
75 static ssize_t ad9832_write(struct device *dev,
76  struct device_attribute *attr,
77  const char *buf,
78  size_t len)
79 {
80  struct iio_dev *indio_dev = dev_to_iio_dev(dev);
81  struct ad9832_state *st = iio_priv(indio_dev);
82  struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
83  int ret;
84  long val;
85 
86  ret = strict_strtoul(buf, 10, &val);
87  if (ret)
88  goto error_ret;
89 
90  mutex_lock(&indio_dev->mlock);
91  switch ((u32) this_attr->address) {
92  case AD9832_FREQ0HM:
93  case AD9832_FREQ1HM:
94  ret = ad9832_write_frequency(st, this_attr->address, val);
95  break;
96  case AD9832_PHASE0H:
97  case AD9832_PHASE1H:
98  case AD9832_PHASE2H:
99  case AD9832_PHASE3H:
100  ret = ad9832_write_phase(st, this_attr->address, val);
101  break;
102  case AD9832_PINCTRL_EN:
103  if (val)
104  st->ctrl_ss &= ~AD9832_SELSRC;
105  else
106  st->ctrl_ss |= AD9832_SELSRC;
107  st->data = cpu_to_be16((AD9832_CMD_SYNCSELSRC << CMD_SHIFT) |
108  st->ctrl_ss);
109  ret = spi_sync(st->spi, &st->msg);
110  break;
111  case AD9832_FREQ_SYM:
112  if (val == 1)
113  st->ctrl_fp |= AD9832_FREQ;
114  else if (val == 0)
115  st->ctrl_fp &= ~AD9832_FREQ;
116  else {
117  ret = -EINVAL;
118  break;
119  }
120  st->data = cpu_to_be16((AD9832_CMD_FPSELECT << CMD_SHIFT) |
121  st->ctrl_fp);
122  ret = spi_sync(st->spi, &st->msg);
123  break;
124  case AD9832_PHASE_SYM:
125  if (val < 0 || val > 3) {
126  ret = -EINVAL;
127  break;
128  }
129 
130  st->ctrl_fp &= ~AD9832_PHASE(3);
131  st->ctrl_fp |= AD9832_PHASE(val);
132 
133  st->data = cpu_to_be16((AD9832_CMD_FPSELECT << CMD_SHIFT) |
134  st->ctrl_fp);
135  ret = spi_sync(st->spi, &st->msg);
136  break;
137  case AD9832_OUTPUT_EN:
138  if (val)
139  st->ctrl_src &= ~(AD9832_RESET | AD9832_SLEEP |
140  AD9832_CLR);
141  else
142  st->ctrl_src |= AD9832_RESET;
143 
144  st->data = cpu_to_be16((AD9832_CMD_SLEEPRESCLR << CMD_SHIFT) |
145  st->ctrl_src);
146  ret = spi_sync(st->spi, &st->msg);
147  break;
148  default:
149  ret = -ENODEV;
150  }
151  mutex_unlock(&indio_dev->mlock);
152 
153 error_ret:
154  return ret ? ret : len;
155 }
156 
161 static IIO_DEV_ATTR_FREQ(0, 0, S_IWUSR, NULL, ad9832_write, AD9832_FREQ0HM);
162 static IIO_DEV_ATTR_FREQ(0, 1, S_IWUSR, NULL, ad9832_write, AD9832_FREQ1HM);
163 static IIO_DEV_ATTR_FREQSYMBOL(0, S_IWUSR, NULL, ad9832_write, AD9832_FREQ_SYM);
164 static IIO_CONST_ATTR_FREQ_SCALE(0, "1"); /* 1Hz */
165 
166 static IIO_DEV_ATTR_PHASE(0, 0, S_IWUSR, NULL, ad9832_write, AD9832_PHASE0H);
167 static IIO_DEV_ATTR_PHASE(0, 1, S_IWUSR, NULL, ad9832_write, AD9832_PHASE1H);
168 static IIO_DEV_ATTR_PHASE(0, 2, S_IWUSR, NULL, ad9832_write, AD9832_PHASE2H);
169 static IIO_DEV_ATTR_PHASE(0, 3, S_IWUSR, NULL, ad9832_write, AD9832_PHASE3H);
170 static IIO_DEV_ATTR_PHASESYMBOL(0, S_IWUSR, NULL,
171  ad9832_write, AD9832_PHASE_SYM);
172 static IIO_CONST_ATTR_PHASE_SCALE(0, "0.0015339808"); /* 2PI/2^12 rad*/
173 
174 static IIO_DEV_ATTR_PINCONTROL_EN(0, S_IWUSR, NULL,
175  ad9832_write, AD9832_PINCTRL_EN);
176 static IIO_DEV_ATTR_OUT_ENABLE(0, S_IWUSR, NULL,
177  ad9832_write, AD9832_OUTPUT_EN);
178 
179 static struct attribute *ad9832_attributes[] = {
180  &iio_dev_attr_out_altvoltage0_frequency0.dev_attr.attr,
181  &iio_dev_attr_out_altvoltage0_frequency1.dev_attr.attr,
182  &iio_const_attr_out_altvoltage0_frequency_scale.dev_attr.attr,
183  &iio_dev_attr_out_altvoltage0_phase0.dev_attr.attr,
184  &iio_dev_attr_out_altvoltage0_phase1.dev_attr.attr,
185  &iio_dev_attr_out_altvoltage0_phase2.dev_attr.attr,
186  &iio_dev_attr_out_altvoltage0_phase3.dev_attr.attr,
187  &iio_const_attr_out_altvoltage0_phase_scale.dev_attr.attr,
188  &iio_dev_attr_out_altvoltage0_pincontrol_en.dev_attr.attr,
189  &iio_dev_attr_out_altvoltage0_frequencysymbol.dev_attr.attr,
190  &iio_dev_attr_out_altvoltage0_phasesymbol.dev_attr.attr,
191  &iio_dev_attr_out_altvoltage0_out_enable.dev_attr.attr,
192  NULL,
193 };
194 
195 static const struct attribute_group ad9832_attribute_group = {
196  .attrs = ad9832_attributes,
197 };
198 
199 static const struct iio_info ad9832_info = {
200  .attrs = &ad9832_attribute_group,
201  .driver_module = THIS_MODULE,
202 };
203 
204 static int __devinit ad9832_probe(struct spi_device *spi)
205 {
206  struct ad9832_platform_data *pdata = spi->dev.platform_data;
207  struct iio_dev *indio_dev;
208  struct ad9832_state *st;
209  struct regulator *reg;
210  int ret;
211 
212  if (!pdata) {
213  dev_dbg(&spi->dev, "no platform data?\n");
214  return -ENODEV;
215  }
216 
217  reg = regulator_get(&spi->dev, "vcc");
218  if (!IS_ERR(reg)) {
219  ret = regulator_enable(reg);
220  if (ret)
221  goto error_put_reg;
222  }
223 
224  indio_dev = iio_device_alloc(sizeof(*st));
225  if (indio_dev == NULL) {
226  ret = -ENOMEM;
227  goto error_disable_reg;
228  }
229  spi_set_drvdata(spi, indio_dev);
230  st = iio_priv(indio_dev);
231  st->reg = reg;
232  st->mclk = pdata->mclk;
233  st->spi = spi;
234 
235  indio_dev->dev.parent = &spi->dev;
236  indio_dev->name = spi_get_device_id(spi)->name;
237  indio_dev->info = &ad9832_info;
238  indio_dev->modes = INDIO_DIRECT_MODE;
239 
240  /* Setup default messages */
241 
242  st->xfer.tx_buf = &st->data;
243  st->xfer.len = 2;
244 
245  spi_message_init(&st->msg);
246  spi_message_add_tail(&st->xfer, &st->msg);
247 
248  st->freq_xfer[0].tx_buf = &st->freq_data[0];
249  st->freq_xfer[0].len = 2;
250  st->freq_xfer[0].cs_change = 1;
251  st->freq_xfer[1].tx_buf = &st->freq_data[1];
252  st->freq_xfer[1].len = 2;
253  st->freq_xfer[1].cs_change = 1;
254  st->freq_xfer[2].tx_buf = &st->freq_data[2];
255  st->freq_xfer[2].len = 2;
256  st->freq_xfer[2].cs_change = 1;
257  st->freq_xfer[3].tx_buf = &st->freq_data[3];
258  st->freq_xfer[3].len = 2;
259 
260  spi_message_init(&st->freq_msg);
261  spi_message_add_tail(&st->freq_xfer[0], &st->freq_msg);
262  spi_message_add_tail(&st->freq_xfer[1], &st->freq_msg);
263  spi_message_add_tail(&st->freq_xfer[2], &st->freq_msg);
264  spi_message_add_tail(&st->freq_xfer[3], &st->freq_msg);
265 
266  st->phase_xfer[0].tx_buf = &st->phase_data[0];
267  st->phase_xfer[0].len = 2;
268  st->phase_xfer[0].cs_change = 1;
269  st->phase_xfer[1].tx_buf = &st->phase_data[1];
270  st->phase_xfer[1].len = 2;
271 
272  spi_message_init(&st->phase_msg);
273  spi_message_add_tail(&st->phase_xfer[0], &st->phase_msg);
274  spi_message_add_tail(&st->phase_xfer[1], &st->phase_msg);
275 
276  st->ctrl_src = AD9832_SLEEP | AD9832_RESET | AD9832_CLR;
277  st->data = cpu_to_be16((AD9832_CMD_SLEEPRESCLR << CMD_SHIFT) |
278  st->ctrl_src);
279  ret = spi_sync(st->spi, &st->msg);
280  if (ret) {
281  dev_err(&spi->dev, "device init failed\n");
282  goto error_free_device;
283  }
284 
285  ret = ad9832_write_frequency(st, AD9832_FREQ0HM, pdata->freq0);
286  if (ret)
287  goto error_free_device;
288 
289  ret = ad9832_write_frequency(st, AD9832_FREQ1HM, pdata->freq1);
290  if (ret)
291  goto error_free_device;
292 
293  ret = ad9832_write_phase(st, AD9832_PHASE0H, pdata->phase0);
294  if (ret)
295  goto error_free_device;
296 
297  ret = ad9832_write_phase(st, AD9832_PHASE1H, pdata->phase1);
298  if (ret)
299  goto error_free_device;
300 
301  ret = ad9832_write_phase(st, AD9832_PHASE2H, pdata->phase2);
302  if (ret)
303  goto error_free_device;
304 
305  ret = ad9832_write_phase(st, AD9832_PHASE3H, pdata->phase3);
306  if (ret)
307  goto error_free_device;
308 
309  ret = iio_device_register(indio_dev);
310  if (ret)
311  goto error_free_device;
312 
313  return 0;
314 
315 error_free_device:
316  iio_device_free(indio_dev);
317 error_disable_reg:
318  if (!IS_ERR(reg))
319  regulator_disable(reg);
320 error_put_reg:
321  if (!IS_ERR(reg))
322  regulator_put(reg);
323 
324  return ret;
325 }
326 
327 static int __devexit ad9832_remove(struct spi_device *spi)
328 {
329  struct iio_dev *indio_dev = spi_get_drvdata(spi);
330  struct ad9832_state *st = iio_priv(indio_dev);
331 
332  iio_device_unregister(indio_dev);
333  if (!IS_ERR(st->reg)) {
334  regulator_disable(st->reg);
335  regulator_put(st->reg);
336  }
337  iio_device_free(indio_dev);
338 
339  return 0;
340 }
341 
342 static const struct spi_device_id ad9832_id[] = {
343  {"ad9832", 0},
344  {"ad9835", 0},
345  {}
346 };
347 MODULE_DEVICE_TABLE(spi, ad9832_id);
348 
349 static struct spi_driver ad9832_driver = {
350  .driver = {
351  .name = "ad9832",
352  .owner = THIS_MODULE,
353  },
354  .probe = ad9832_probe,
355  .remove = __devexit_p(ad9832_remove),
356  .id_table = ad9832_id,
357 };
358 module_spi_driver(ad9832_driver);
359 
360 MODULE_AUTHOR("Michael Hennerich <[email protected]>");
361 MODULE_DESCRIPTION("Analog Devices AD9832/AD9835 DDS");
362 MODULE_LICENSE("GPL v2");
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