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ambassador.h
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1 /*
2  Madge Ambassador ATM Adapter driver.
3  Copyright (C) 1995-1999 Madge Networks Ltd.
4 
5  This program is free software; you can redistribute it and/or modify
6  it under the terms of the GNU General Public License as published by
7  the Free Software Foundation; either version 2 of the License, or
8  (at your option) any later version.
9 
10  This program is distributed in the hope that it will be useful,
11  but WITHOUT ANY WARRANTY; without even the implied warranty of
12  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13  GNU General Public License for more details.
14 
15  You should have received a copy of the GNU General Public License
16  along with this program; if not, write to the Free Software
17  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 
19  The GNU GPL is contained in /usr/doc/copyright/GPL on a Debian
20  system and in the file COPYING in the Linux kernel source.
21 */
22 
23 #ifndef AMBASSADOR_H
24 #define AMBASSADOR_H
25 
26 
27 #ifdef CONFIG_ATM_AMBASSADOR_DEBUG
28 #define DEBUG_AMBASSADOR
29 #endif
30 
31 #define DEV_LABEL "amb"
32 
33 #ifndef PCI_VENDOR_ID_MADGE
34 #define PCI_VENDOR_ID_MADGE 0x10B6
35 #endif
36 #ifndef PCI_VENDOR_ID_MADGE_AMBASSADOR
37 #define PCI_DEVICE_ID_MADGE_AMBASSADOR 0x1001
38 #endif
39 #ifndef PCI_VENDOR_ID_MADGE_AMBASSADOR_BAD
40 #define PCI_DEVICE_ID_MADGE_AMBASSADOR_BAD 0x1002
41 #endif
42 
43 // diagnostic output
44 
45 #define PRINTK(severity,format,args...) \
46  printk(severity DEV_LABEL ": " format "\n" , ## args)
47 
48 #ifdef DEBUG_AMBASSADOR
49 
50 #define DBG_ERR 0x0001
51 #define DBG_WARN 0x0002
52 #define DBG_INFO 0x0004
53 #define DBG_INIT 0x0008
54 #define DBG_LOAD 0x0010
55 #define DBG_VCC 0x0020
56 #define DBG_QOS 0x0040
57 #define DBG_CMD 0x0080
58 #define DBG_TX 0x0100
59 #define DBG_RX 0x0200
60 #define DBG_SKB 0x0400
61 #define DBG_POOL 0x0800
62 #define DBG_IRQ 0x1000
63 #define DBG_FLOW 0x2000
64 #define DBG_REGS 0x4000
65 #define DBG_DATA 0x8000
66 #define DBG_MASK 0xffff
67 
68 /* the ## prevents the annoying double expansion of the macro arguments */
69 /* KERN_INFO is used since KERN_DEBUG often does not make it to the console */
70 #define PRINTDB(bits,format,args...) \
71  ( (debug & (bits)) ? printk (KERN_INFO DEV_LABEL ": " format , ## args) : 1 )
72 #define PRINTDM(bits,format,args...) \
73  ( (debug & (bits)) ? printk (format , ## args) : 1 )
74 #define PRINTDE(bits,format,args...) \
75  ( (debug & (bits)) ? printk (format "\n" , ## args) : 1 )
76 #define PRINTD(bits,format,args...) \
77  ( (debug & (bits)) ? printk (KERN_INFO DEV_LABEL ": " format "\n" , ## args) : 1 )
78 
79 #else
80 
81 #define PRINTD(bits,format,args...)
82 #define PRINTDB(bits,format,args...)
83 #define PRINTDM(bits,format,args...)
84 #define PRINTDE(bits,format,args...)
85 
86 #endif
87 
88 #define PRINTDD(bits,format,args...)
89 #define PRINTDDB(sec,fmt,args...)
90 #define PRINTDDM(sec,fmt,args...)
91 #define PRINTDDE(sec,fmt,args...)
92 
93 // tunable values (?)
94 
95 /* MUST be powers of two -- why ? */
96 #define COM_Q_ENTRIES 8
97 #define TX_Q_ENTRIES 32
98 #define RX_Q_ENTRIES 64
99 
100 // fixed values
101 
102 // guessing
103 #define AMB_EXTENT 0x80
104 
105 // Minimum allowed size for an Ambassador queue
106 #define MIN_QUEUE_SIZE 2
107 
108 // Ambassador microcode allows 1 to 4 pools, we use 4 (simpler)
109 #define NUM_RX_POOLS 4
110 
111 // minimum RX buffers required to cope with replenishing delay
112 #define MIN_RX_BUFFERS 1
113 
114 // minimum PCI latency we will tolerate (32 IS TOO SMALL)
115 #define MIN_PCI_LATENCY 64 // 255
116 
117 // VCs supported by card (VPI always 0)
118 #define NUM_VPI_BITS 0
119 #define NUM_VCI_BITS 10
120 #define NUM_VCS 1024
121 
122 /* The status field bits defined so far. */
123 #define RX_ERR 0x8000 // always present if there is an error (hmm)
124 #define CRC_ERR 0x4000 // AAL5 CRC error
125 #define LEN_ERR 0x2000 // overlength frame
126 #define ABORT_ERR 0x1000 // zero length field in received frame
127 #define UNUSED_ERR 0x0800 // buffer returned unused
128 
129 // Adaptor commands
130 
131 #define SRB_OPEN_VC 0
132 /* par_0: dwordswap(VC_number) */
133 /* par_1: dwordswap(flags<<16) or wordswap(flags)*/
134 /* flags: */
135 
136 /* LANE: 0x0004 */
137 /* NOT_UBR: 0x0008 */
138 /* ABR: 0x0010 */
139 
140 /* RxPool0: 0x0000 */
141 /* RxPool1: 0x0020 */
142 /* RxPool2: 0x0040 */
143 /* RxPool3: 0x0060 */
144 
145 /* par_2: dwordswap(fp_rate<<16) or wordswap(fp_rate) */
146 
147 #define SRB_CLOSE_VC 1
148 /* par_0: dwordswap(VC_number) */
149 
150 #define SRB_GET_BIA 2
151 /* returns */
152 /* par_0: dwordswap(half BIA) */
153 /* par_1: dwordswap(half BIA) */
154 
155 #define SRB_GET_SUNI_STATS 3
156 /* par_0: dwordswap(physical_host_address) */
157 
158 #define SRB_SET_BITS_8 4
159 #define SRB_SET_BITS_16 5
160 #define SRB_SET_BITS_32 6
161 #define SRB_CLEAR_BITS_8 7
162 #define SRB_CLEAR_BITS_16 8
163 #define SRB_CLEAR_BITS_32 9
164 /* par_0: dwordswap(ATMizer address) */
165 /* par_1: dwordswap(mask) */
166 
167 #define SRB_SET_8 10
168 #define SRB_SET_16 11
169 #define SRB_SET_32 12
170 /* par_0: dwordswap(ATMizer address) */
171 /* par_1: dwordswap(data) */
172 
173 #define SRB_GET_32 13
174 /* par_0: dwordswap(ATMizer address) */
175 /* returns */
176 /* par_1: dwordswap(ATMizer data) */
177 
178 #define SRB_GET_VERSION 14
179 /* returns */
180 /* par_0: dwordswap(Major Version) */
181 /* par_1: dwordswap(Minor Version) */
182 
183 #define SRB_FLUSH_BUFFER_Q 15
184 /* Only flags to define which buffer pool; all others must be zero */
185 /* par_0: dwordswap(flags<<16) or wordswap(flags)*/
186 
187 #define SRB_GET_DMA_SPEEDS 16
188 /* returns */
189 /* par_0: dwordswap(Read speed (bytes/sec)) */
190 /* par_1: dwordswap(Write speed (bytes/sec)) */
191 
192 #define SRB_MODIFY_VC_RATE 17
193 /* par_0: dwordswap(VC_number) */
194 /* par_1: dwordswap(fp_rate<<16) or wordswap(fp_rate) */
195 
196 #define SRB_MODIFY_VC_FLAGS 18
197 /* par_0: dwordswap(VC_number) */
198 /* par_1: dwordswap(flags<<16) or wordswap(flags)*/
199 
200 /* flags: */
201 
202 /* LANE: 0x0004 */
203 /* NOT_UBR: 0x0008 */
204 /* ABR: 0x0010 */
205 
206 /* RxPool0: 0x0000 */
207 /* RxPool1: 0x0020 */
208 /* RxPool2: 0x0040 */
209 /* RxPool3: 0x0060 */
210 
211 #define SRB_RATE_SHIFT 16
212 #define SRB_POOL_SHIFT (SRB_FLAGS_SHIFT+5)
213 #define SRB_FLAGS_SHIFT 16
214 
215 #define SRB_STOP_TASKING 19
216 #define SRB_START_TASKING 20
217 #define SRB_SHUT_DOWN 21
218 #define MAX_SRB 21
219 
220 #define SRB_COMPLETE 0xffffffff
221 
222 #define TX_FRAME 0x80000000
223 
224 // number of types of SRB MUST be a power of two -- why?
225 #define NUM_OF_SRB 32
226 
227 // number of bits of period info for rate
228 #define MAX_RATE_BITS 6
229 
230 #define TX_UBR 0x0000
231 #define TX_UBR_CAPPED 0x0008
232 #define TX_ABR 0x0018
233 #define TX_FRAME_NOTCAP 0x0000
234 #define TX_FRAME_CAPPED 0x8000
235 
236 #define FP_155_RATE 0x24b1
237 #define FP_25_RATE 0x1f9d
238 
239 /* #define VERSION_NUMBER 0x01000000 // initial release */
240 /* #define VERSION_NUMBER 0x01010000 // fixed startup probs PLX MB0 not cleared */
241 /* #define VERSION_NUMBER 0x01020000 // changed SUNI reset timings; allowed r/w onchip */
242 
243 /* #define VERSION_NUMBER 0x01030000 // clear local doorbell int reg on reset */
244 /* #define VERSION_NUMBER 0x01040000 // PLX bug work around version PLUS */
245 /* remove race conditions on basic interface */
246 /* indicate to the host that diagnostics */
247 /* have finished; if failed, how and what */
248 /* failed */
249 /* fix host memory test to fix PLX bug */
250 /* allow flash upgrade and BIA upgrade directly */
251 /* */
252 #define VERSION_NUMBER 0x01050025 /* Jason's first hacked version. */
253 /* Change in download algorithm */
254 
255 #define DMA_VALID 0xb728e149 /* completely random */
256 
257 #define FLASH_BASE 0xa0c00000
258 #define FLASH_SIZE 0x00020000 /* 128K */
259 #define BIA_BASE (FLASH_BASE+0x0001c000) /* Flash Sector 7 */
260 #define BIA_ADDRESS ((void *)0xa0c1c000)
261 #define PLX_BASE 0xe0000000
262 
263 typedef enum {
276 
277 #define BAD_COMMAND (-1)
278 #define COMMAND_IN_PROGRESS 1
279 #define COMMAND_PASSED_TEST 2
280 #define COMMAND_FAILED_TEST 3
281 #define COMMAND_READ_DATA_OK 4
282 #define COMMAND_READ_BAD_ADDRESS 5
283 #define COMMAND_WRITE_DATA_OK 6
284 #define COMMAND_WRITE_BAD_ADDRESS 7
285 #define COMMAND_WRITE_FLASH_FAILURE 8
286 #define COMMAND_COMPLETE 9
287 #define COMMAND_FLASH_ERASE_FAILURE 10
288 #define COMMAND_WRITE_BAD_DATA 11
289 
290 /* bit fields for mailbox[0] return values */
291 
292 #define GPINT_TST_FAILURE 0x00000001
293 #define SUNI_DATA_PATTERN_FAILURE 0x00000002
294 #define SUNI_DATA_BITS_FAILURE 0x00000004
295 #define SUNI_UTOPIA_FAILURE 0x00000008
296 #define SUNI_FIFO_FAILURE 0x00000010
297 #define SRAM_FAILURE 0x00000020
298 #define SELF_TEST_FAILURE 0x0000003f
299 
300 /* mailbox[1] = 0 in progress, -1 on completion */
301 /* mailbox[2] = current test 00 00 test(8 bit) phase(8 bit) */
302 /* mailbox[3] = last failure, 00 00 test(8 bit) phase(8 bit) */
303 /* mailbox[4],mailbox[5],mailbox[6] random failure values */
304 
305 /* PLX/etc. memory map including command structure */
306 
307 /* These registers may also be memory mapped in PCI memory */
308 
309 #define UNUSED_LOADER_MAILBOXES 6
310 
311 typedef struct {
312  u32 stuff[16];
313  union {
314  struct {
318  } loader;
319  struct {
322  u32 rx_address[NUM_RX_POOLS];
325  } adapter;
326  } mb;
331 } amb_mem;
332 
333 /* RESET bit, IRQ (card to host) and doorbell (host to card) enable bits */
334 #define AMB_RESET_BITS 0x40000000
335 #define AMB_INTERRUPT_BITS 0x00000300
336 #define AMB_DOORBELL_BITS 0x00030000
337 
338 /* loader commands */
339 
340 #define MAX_COMMAND_DATA 13
341 #define MAX_TRANSFER_DATA 11
342 
343 typedef struct {
348 
349 typedef struct {
352  union {
357  } payload;
359 } loader_block;
360 
361 /* command queue */
362 
363 /* Again all data are BIG ENDIAN */
364 
365 typedef struct {
366  union {
367  struct {
371  } open;
372  struct {
373  __be32 vc;
374  __be32 rate;
375  } modify_rate;
376  struct {
377  __be32 vc;
378  __be32 flags;
379  } modify_flags;
380  struct {
381  __be32 vc;
382  } close;
383  struct {
386  } bia;
387  struct {
389  } suni;
390  struct {
393  } version;
394  struct {
397  } speed;
398  struct {
399  __be32 flags;
400  } flush;
401  struct {
402  __be32 address;
404  } memory;
405  __be32 par[3];
406  } args;
408 } command;
409 
410 /* transmit queues and associated structures */
411 
412 /* The hosts transmit structure. All BIG ENDIAN; host address
413  restricted to first 1GByte, but address passed to the card must
414  have the top MS bit or'ed in. -- check this */
415 
416 /* TX is described by 1+ tx_frags followed by a tx_frag_end */
417 
418 typedef struct {
421 } tx_frag;
422 
423 /* apart from handle the fields here are for the adapter to play with
424  and should be set to zero */
425 
426 typedef struct {
431 #ifdef AMB_NEW_MICROCODE
432  u8 cpcs_uu;
433  u8 cpi;
434  u16 pad;
435 #endif
436 } tx_frag_end;
437 
438 typedef struct {
441  struct sk_buff * skb;
442 } tx_simple;
443 
444 #if 0
445 typedef union {
446  tx_frag fragment;
447  tx_frag_end end_of_list;
448 } tx_descr;
449 #endif
450 
451 /* this "points" to the sequence of fragments and trailer */
452 
453 typedef struct {
457 } tx_in;
458 
459 /* handle is the handle from tx_in */
460 
461 typedef struct {
463 } tx_out;
464 
465 /* receive frame structure */
466 
467 /* All BIG ENDIAN; handle is as passed from host; length is zero for
468  aborted frames, and frames with errors. Header is actually VC
469  number, lec-id is NOT yet supported. */
470 
471 typedef struct {
474  __be16 lec_id; // unused
477 } rx_out;
478 
479 /* buffer supply structure */
480 
481 typedef struct {
484 } rx_in;
485 
486 /* This first structure is the area in host memory where the adapter
487  writes its pointer values. These pointer values are BIG ENDIAN and
488  reside in the same 4MB 'page' as this structure. The host gives the
489  adapter the address of this block by sending a doorbell interrupt
490  to the adapter after downloading the code and setting it going. The
491  addresses have the top 10 bits set to 1010000010b -- really?
492 
493  The host must initialise these before handing the block to the
494  adapter. */
495 
496 typedef struct {
497  __be32 command_start; /* SRB commands completions */
498  __be32 command_end; /* SRB commands completions */
501  __be32 txcom_start; /* tx completions */
502  __be32 txcom_end; /* tx completions */
503  struct {
509  __be32 rx_start; /* rx completions */
512  __be32 buffer_size; /* size of host buffer */
513  } rec_struct[NUM_RX_POOLS];
514 #ifdef AMB_NEW_MICROCODE
515  u16 init_flags;
516  u16 talk_block_spare;
517 #endif
519 
520 /* This structure must be kept in line with the vcr image in sarmain.h
521 
522  This is the structure in the host filled in by the adapter by
523  GET_SUNI_STATS */
524 
525 typedef struct {
534 } suni_stats;
535 
536 typedef enum {
538 } amb_flags;
539 
540 #define NEXTQ(current,start,limit) \
541  ( (current)+1 < (limit) ? (current)+1 : (start) )
542 
543 typedef struct {
548 } amb_cq_ptrs;
549 
550 typedef struct {
552  unsigned int pending;
553  unsigned int high;
554  unsigned int filled;
555  unsigned int maximum; // size - 1 (q implementation)
557 } amb_cq;
558 
559 typedef struct {
561  unsigned int pending;
562  unsigned int high;
563  unsigned int filled;
564  unsigned int maximum; // size - 1 (q implementation)
565  struct {
569  } in;
570  struct {
574  } out;
575 } amb_txq;
576 
577 typedef struct {
579  unsigned int pending;
580  unsigned int low;
581  unsigned int emptied;
582  unsigned int maximum; // size - 1 (q implementation)
583  struct {
587  } in;
588  struct {
592  } out;
593  unsigned int buffers_wanted;
594  unsigned int buffer_size;
595 } amb_rxq;
596 
597 typedef struct {
598  unsigned long tx_ok;
599  struct {
600  unsigned long ok;
601  unsigned long error;
602  unsigned long badcrc;
603  unsigned long toolong;
604  unsigned long aborted;
605  unsigned long unused;
606  } rx;
607 } amb_stats;
608 
609 // a single struct pointed to by atm_vcc->dev_data
610 
611 typedef struct {
612  u8 tx_vc_bits:7;
613  u8 tx_present:1;
614 } amb_tx_info;
615 
616 typedef struct {
617  unsigned char pool;
618 } amb_rx_info;
619 
620 typedef struct {
623  unsigned int tx_rate;
624  unsigned int rx_rate;
625 } amb_vcc;
626 
627 struct amb_dev {
629  unsigned long flags;
632 
636 
637  struct mutex vcc_sf;
639  struct atm_vcc * rxer[NUM_VCS];
640  unsigned int tx_avail;
641  unsigned int rx_avail;
642 
644 
645  struct atm_dev * atm_dev;
646  struct pci_dev * pci_dev;
648 };
649 
650 typedef struct amb_dev amb_dev;
651 
652 #define AMB_DEV(atm_dev) ((amb_dev *) (atm_dev)->dev_data)
653 #define AMB_VCC(atm_vcc) ((amb_vcc *) (atm_vcc)->dev_data)
654 
655 /* rate rounding */
656 
657 typedef enum {
661 } rounding;
662 
663 #endif