#include <linux/module.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/pci_ids.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include <linux/dmi.h>
#include <linux/edac.h>
#include <linux/mmzone.h>
#include <linux/smp.h>
#include <asm/mce.h>
#include <asm/processor.h>
#include <asm/div64.h>
#include "edac_core.h"

Data Structures
struct	i7core_info

struct	i7core_inject

struct	i7core_channel

struct	pci_id_descr

struct	pci_id_table

struct	i7core_dev

struct	i7core_pvt

struct	memdev_dmi_entry

Macros
#define	MAX_SOCKET_BUSES 2

#define	I7CORE_REVISION " Ver: 1.0.0"

#define	EDAC_MOD_STR "i7core_edac"

#define	i7core_printk(level, fmt, arg...) edac_printk(level, "i7core", fmt, ##arg)

#define	i7core_mc_printk(mci, level, fmt, arg...) edac_mc_chipset_printk(mci, level, "i7core", fmt, ##arg)

#define	MC_CFG_CONTROL 0x90

#define	MC_CFG_UNLOCK 0x02

#define	MC_CFG_LOCK 0x00

#define	MC_CONTROL 0x48

#define	MC_STATUS 0x4c

#define	MC_MAX_DOD 0x64

#define	MC_TEST_ERR_RCV1 0x60

#define	DIMM2_COR_ERR(r) ((r) & 0x7fff)

#define	MC_TEST_ERR_RCV0 0x64

#define	DIMM1_COR_ERR(r) (((r) >> 16) & 0x7fff)

#define	DIMM0_COR_ERR(r) ((r) & 0x7fff)

#define	MC_SSRCONTROL 0x48

#define	SSR_MODE_DISABLE 0x00

#define	SSR_MODE_ENABLE 0x01

#define	SSR_MODE_MASK 0x03

#define	MC_SCRUB_CONTROL 0x4c

#define	STARTSCRUB (1 << 24)

#define	SCRUBINTERVAL_MASK 0xffffff

#define	MC_COR_ECC_CNT_0 0x80

#define	MC_COR_ECC_CNT_1 0x84

#define	MC_COR_ECC_CNT_2 0x88

#define	MC_COR_ECC_CNT_3 0x8c

#define	MC_COR_ECC_CNT_4 0x90

#define	MC_COR_ECC_CNT_5 0x94

#define	DIMM_TOP_COR_ERR(r) (((r) >> 16) & 0x7fff)

#define	DIMM_BOT_COR_ERR(r) ((r) & 0x7fff)

#define	MC_CHANNEL_DIMM_INIT_PARAMS 0x58

#define	THREE_DIMMS_PRESENT (1 << 24)

#define	SINGLE_QUAD_RANK_PRESENT (1 << 23)

#define	QUAD_RANK_PRESENT (1 << 22)

#define	REGISTERED_DIMM (1 << 15)

#define	MC_CHANNEL_MAPPER 0x60

#define	RDLCH(r, ch) ((((r) >> (3 + (ch * 6))) & 0x07) - 1)

#define	WRLCH(r, ch) ((((r) >> (ch * 6)) & 0x07) - 1)

#define	MC_CHANNEL_RANK_PRESENT 0x7c

#define	RANK_PRESENT_MASK 0xffff

#define	MC_CHANNEL_ADDR_MATCH 0xf0

#define	MC_CHANNEL_ERROR_MASK 0xf8

#define	MC_CHANNEL_ERROR_INJECT 0xfc

#define	INJECT_ADDR_PARITY 0x10

#define	INJECT_ECC 0x08

#define	MASK_CACHELINE 0x06

#define	MASK_FULL_CACHELINE 0x06

#define	MASK_MSB32_CACHELINE 0x04

#define	MASK_LSB32_CACHELINE 0x02

#define	NO_MASK_CACHELINE 0x00

#define	REPEAT_EN 0x01

#define	MC_DOD_CH_DIMM0 0x48

#define	MC_DOD_CH_DIMM1 0x4c

#define	MC_DOD_CH_DIMM2 0x50

#define	RANKOFFSET_MASK ((1 << 12) \| (1 << 11) \| (1 << 10))

#define	RANKOFFSET(x) ((x & RANKOFFSET_MASK) >> 10)

#define	DIMM_PRESENT_MASK (1 << 9)

#define	DIMM_PRESENT(x) (((x) & DIMM_PRESENT_MASK) >> 9)

#define	MC_DOD_NUMBANK_MASK ((1 << 8) \| (1 << 7))

#define	MC_DOD_NUMBANK(x) (((x) & MC_DOD_NUMBANK_MASK) >> 7)

#define	MC_DOD_NUMRANK_MASK ((1 << 6) \| (1 << 5))

#define	MC_DOD_NUMRANK(x) (((x) & MC_DOD_NUMRANK_MASK) >> 5)

#define	MC_DOD_NUMROW_MASK ((1 << 4) \| (1 << 3) \| (1 << 2))

#define	MC_DOD_NUMROW(x) (((x) & MC_DOD_NUMROW_MASK) >> 2)

#define	MC_DOD_NUMCOL_MASK 3

#define	MC_DOD_NUMCOL(x) ((x) & MC_DOD_NUMCOL_MASK)

#define	MC_RANK_PRESENT 0x7c

#define	MC_SAG_CH_0 0x80

#define	MC_SAG_CH_1 0x84

#define	MC_SAG_CH_2 0x88

#define	MC_SAG_CH_3 0x8c

#define	MC_SAG_CH_4 0x90

#define	MC_SAG_CH_5 0x94

#define	MC_SAG_CH_6 0x98

#define	MC_SAG_CH_7 0x9c

#define	MC_RIR_LIMIT_CH_0 0x40

#define	MC_RIR_LIMIT_CH_1 0x44

#define	MC_RIR_LIMIT_CH_2 0x48

#define	MC_RIR_LIMIT_CH_3 0x4C

#define	MC_RIR_LIMIT_CH_4 0x50

#define	MC_RIR_LIMIT_CH_5 0x54

#define	MC_RIR_LIMIT_CH_6 0x58

#define	MC_RIR_LIMIT_CH_7 0x5C

#define	MC_RIR_LIMIT_MASK ((1 << 10) - 1)

#define	MC_RIR_WAY_CH 0x80

#define	MC_RIR_WAY_OFFSET_MASK (((1 << 14) - 1) & ~0x7)

#define	MC_RIR_WAY_RANK_MASK 0x7

#define	NUM_CHANS 3

#define	MAX_DIMMS 3 /* Max DIMMS per channel */

#define	MAX_MCR_FUNC 4

#define	MAX_CHAN_FUNC 3

#define	PCI_DESCR(device, function, device_id)

#define	PCI_ID_TABLE_ENTRY(A) { .descr=A, .n_devs = ARRAY_SIZE(A) }

#define	CH_ACTIVE(pvt, ch) ((pvt)->info.mc_control & (1 << (8 + ch)))

#define	ECCx8(pvt) ((pvt)->info.mc_control & (1 << 1))

#define	ECC_ENABLED(pvt) ((pvt)->info.mc_status & (1 << 4))

#define	CH_DISABLED(pvt, ch) ((pvt)->info.mc_status & (1 << ch))

#define	to_mci(k) container_of(k, struct mem_ctl_info, dev)

#define	DECLARE_ADDR_MATCH(param, limit)

#define	ATTR_ADDR_MATCH(param)

#define	DECLARE_COUNTER(param)

#define	ATTR_COUNTER(param)

#define	DEFAULT_DCLK_FREQ 800

Functions
	module_param (use_pci_fixup, int, 0444)

	MODULE_PARM_DESC (use_pci_fixup,"Enable PCI fixup to seek for hidden devices")

	DECLARE_ADDR_MATCH (channel, 3)

	DECLARE_ADDR_MATCH (dimm, 3)

	DECLARE_ADDR_MATCH (rank, 4)

	DECLARE_ADDR_MATCH (bank, 32)

	DECLARE_ADDR_MATCH (page, 0x10000)

	DECLARE_ADDR_MATCH (col, 0x4000)

	ATTR_ADDR_MATCH (channel)

	ATTR_ADDR_MATCH (dimm)

	ATTR_ADDR_MATCH (rank)

	ATTR_ADDR_MATCH (bank)

	ATTR_ADDR_MATCH (page)

	ATTR_ADDR_MATCH (col)

	DECLARE_COUNTER (0)

	DECLARE_COUNTER (1)

	DECLARE_COUNTER (2)

	ATTR_COUNTER (0)

	ATTR_COUNTER (1)

	ATTR_COUNTER (2)

struct memdev_dmi_entry	__attribute__ ((__packed__))

	MODULE_DEVICE_TABLE (pci, i7core_pci_tbl)

	module_init (i7core_init)

	module_exit (i7core_exit)

	MODULE_LICENSE ("GPL")

	MODULE_AUTHOR ("Mauro Carvalho Chehab <[email protected]>")

	MODULE_AUTHOR ("Red Hat Inc. (http://www.redhat.com)")

	MODULE_DESCRIPTION ("MC Driver for Intel i7 Core memory controllers - "I7CORE_REVISION)

	module_param (edac_op_state, int, 0444)

	MODULE_PARM_DESC (edac_op_state,"EDAC Error Reporting state: 0=Poll,1=NMI")

Variables
u8	type

u8	length

u16	handle

u16	phys_mem_array_handle

u16	mem_err_info_handle

u16	total_width

u16	data_width

u16	size

u8	form

u8	device_set

u8	device_locator

u8	bank_locator

u8	memory_type

u16	type_detail

u16	speed

u8	manufacturer

u8	serial_number

u8	asset_tag

u8	part_number

u8	attributes

u32	extended_size

u16	conf_mem_clk_speed

Macro Definition Documentation

#define ATTR_ADDR_MATCH ( param )

Value:

static DEVICE_ATTR(param, S_IRUGO | S_IWUSR,        \
            i7core_inject_show_##param,         \
            i7core_inject_store_##param)

Definition at line 859 of file i7core_edac.c.

#define ATTR_COUNTER ( param )

Value:

static DEVICE_ATTR(udimm##param, S_IRUGO | S_IWUSR, \
            i7core_show_counter_##param,        \
            NULL)

Definition at line 1065 of file i7core_edac.c.

#define CH_ACTIVE	(	pvt,
		ch
	)	((pvt)->info.mc_control & (1 << (8 + ch)))

Definition at line 408 of file i7core_edac.c.

#define CH_DISABLED	(	pvt,
		ch
	)	((pvt)->info.mc_status & (1 << ch))

Definition at line 413 of file i7core_edac.c.

#define DECLARE_ADDR_MATCH	(	param,
		limit
	)

Definition at line 813 of file i7core_edac.c.

#define DECLARE_COUNTER ( param )

Value:

static ssize_t i7core_show_counter_##param(         \
    struct device *dev,                 \
    struct device_attribute *mattr,             \
    char *data)                     \
{                               \
	struct mem_ctl_info *mci = dev_get_drvdata(dev);   \
	struct i7core_pvt *pvt = mci->pvt_info;            \
								\
	edac_dbg(1, "\n");                 \
    if (!pvt->ce_count_available || (pvt->is_registered))   \
        return sprintf(data, "data unavailable\n"); \
    return sprintf(data, "%lu\n",               \
            pvt->udimm_ce_count[param]);        \
}

Definition at line 1049 of file i7core_edac.c.

#define DEFAULT_DCLK_FREQ 800

Definition at line 2008 of file i7core_edac.c.

#define DIMM0_COR_ERR ( r ) ((r) & 0x7fff)

Definition at line 102 of file i7core_edac.c.

#define DIMM1_COR_ERR ( r ) (((r) >> 16) & 0x7fff)

Definition at line 101 of file i7core_edac.c.

#define DIMM2_COR_ERR ( r ) ((r) & 0x7fff)

Definition at line 98 of file i7core_edac.c.

#define DIMM_BOT_COR_ERR ( r ) ((r) & 0x7fff)

Definition at line 122 of file i7core_edac.c.

#define DIMM_PRESENT ( x ) (((x) & DIMM_PRESENT_MASK) >> 9)

Definition at line 160 of file i7core_edac.c.

#define DIMM_PRESENT_MASK (1 << 9)

Definition at line 159 of file i7core_edac.c.

#define DIMM_TOP_COR_ERR ( r ) (((r) >> 16) & 0x7fff)

Definition at line 121 of file i7core_edac.c.

#define ECC_ENABLED ( pvt ) ((pvt)->info.mc_status & (1 << 4))

Definition at line 412 of file i7core_edac.c.

#define ECCx8 ( pvt ) ((pvt)->info.mc_control & (1 << 1))

Definition at line 409 of file i7core_edac.c.

#define EDAC_MOD_STR "i7core_edac"

Definition at line 65 of file i7core_edac.c.

#define i7core_mc_printk	(	mci,
		level,
		fmt,
		arg...
	)	edac_mc_chipset_printk(mci, level, "i7core", fmt, ##arg)

Definition at line 73 of file i7core_edac.c.

#define i7core_printk	(	level,
		fmt,
		arg...
	)	edac_printk(level, "i7core", fmt, ##arg)

Definition at line 70 of file i7core_edac.c.

#define I7CORE_REVISION " Ver: 1.0.0"

Definition at line 64 of file i7core_edac.c.

#define INJECT_ADDR_PARITY 0x10

Definition at line 143 of file i7core_edac.c.

#define INJECT_ECC 0x08

Definition at line 144 of file i7core_edac.c.

#define MASK_CACHELINE 0x06

Definition at line 145 of file i7core_edac.c.

#define MASK_FULL_CACHELINE 0x06

Definition at line 146 of file i7core_edac.c.

#define MASK_LSB32_CACHELINE 0x02

Definition at line 148 of file i7core_edac.c.

#define MASK_MSB32_CACHELINE 0x04

Definition at line 147 of file i7core_edac.c.

#define MAX_CHAN_FUNC 3

Definition at line 202 of file i7core_edac.c.

#define MAX_DIMMS 3 /* Max DIMMS per channel */

Definition at line 200 of file i7core_edac.c.

#define MAX_MCR_FUNC 4

Definition at line 201 of file i7core_edac.c.

#define MAX_SOCKET_BUSES 2

Definition at line 58 of file i7core_edac.c.

#define MC_CFG_CONTROL 0x90

Definition at line 82 of file i7core_edac.c.

#define MC_CFG_LOCK 0x00

Definition at line 84 of file i7core_edac.c.

#define MC_CFG_UNLOCK 0x02

Definition at line 83 of file i7core_edac.c.

#define MC_CHANNEL_ADDR_MATCH 0xf0

Definition at line 140 of file i7core_edac.c.

#define MC_CHANNEL_DIMM_INIT_PARAMS 0x58

Definition at line 127 of file i7core_edac.c.

#define MC_CHANNEL_ERROR_INJECT 0xfc

Definition at line 142 of file i7core_edac.c.

#define MC_CHANNEL_ERROR_MASK 0xf8

Definition at line 141 of file i7core_edac.c.

#define MC_CHANNEL_MAPPER 0x60

Definition at line 133 of file i7core_edac.c.

#define MC_CHANNEL_RANK_PRESENT 0x7c

Definition at line 137 of file i7core_edac.c.

#define MC_CONTROL 0x48

Definition at line 88 of file i7core_edac.c.

#define MC_COR_ECC_CNT_0 0x80

Definition at line 114 of file i7core_edac.c.

#define MC_COR_ECC_CNT_1 0x84

Definition at line 115 of file i7core_edac.c.

#define MC_COR_ECC_CNT_2 0x88

Definition at line 116 of file i7core_edac.c.

#define MC_COR_ECC_CNT_3 0x8c

Definition at line 117 of file i7core_edac.c.

#define MC_COR_ECC_CNT_4 0x90

Definition at line 118 of file i7core_edac.c.

#define MC_COR_ECC_CNT_5 0x94

Definition at line 119 of file i7core_edac.c.

#define MC_DOD_CH_DIMM0 0x48

Definition at line 154 of file i7core_edac.c.

#define MC_DOD_CH_DIMM1 0x4c

Definition at line 155 of file i7core_edac.c.

#define MC_DOD_CH_DIMM2 0x50

Definition at line 156 of file i7core_edac.c.

#define MC_DOD_NUMBANK ( x ) (((x) & MC_DOD_NUMBANK_MASK) >> 7)

Definition at line 162 of file i7core_edac.c.

#define MC_DOD_NUMBANK_MASK ((1 << 8) | (1 << 7))

Definition at line 161 of file i7core_edac.c.

#define MC_DOD_NUMCOL ( x ) ((x) & MC_DOD_NUMCOL_MASK)

Definition at line 168 of file i7core_edac.c.

#define MC_DOD_NUMCOL_MASK 3

Definition at line 167 of file i7core_edac.c.

#define MC_DOD_NUMRANK ( x ) (((x) & MC_DOD_NUMRANK_MASK) >> 5)

Definition at line 164 of file i7core_edac.c.

#define MC_DOD_NUMRANK_MASK ((1 << 6) | (1 << 5))

Definition at line 163 of file i7core_edac.c.

#define MC_DOD_NUMROW ( x ) (((x) & MC_DOD_NUMROW_MASK) >> 2)

Definition at line 166 of file i7core_edac.c.

#define MC_DOD_NUMROW_MASK ((1 << 4) | (1 << 3) | (1 << 2))

Definition at line 165 of file i7core_edac.c.

#define MC_MAX_DOD 0x64

Definition at line 90 of file i7core_edac.c.

#define MC_RANK_PRESENT 0x7c

Definition at line 170 of file i7core_edac.c.

#define MC_RIR_LIMIT_CH_0 0x40

Definition at line 181 of file i7core_edac.c.

#define MC_RIR_LIMIT_CH_1 0x44

Definition at line 182 of file i7core_edac.c.

#define MC_RIR_LIMIT_CH_2 0x48

Definition at line 183 of file i7core_edac.c.

#define MC_RIR_LIMIT_CH_3 0x4C

Definition at line 184 of file i7core_edac.c.

#define MC_RIR_LIMIT_CH_4 0x50

Definition at line 185 of file i7core_edac.c.

#define MC_RIR_LIMIT_CH_5 0x54

Definition at line 186 of file i7core_edac.c.

#define MC_RIR_LIMIT_CH_6 0x58

Definition at line 187 of file i7core_edac.c.

#define MC_RIR_LIMIT_CH_7 0x5C

Definition at line 188 of file i7core_edac.c.

#define MC_RIR_LIMIT_MASK ((1 << 10) - 1)

Definition at line 189 of file i7core_edac.c.

#define MC_RIR_WAY_CH 0x80

Definition at line 191 of file i7core_edac.c.

#define MC_RIR_WAY_OFFSET_MASK (((1 << 14) - 1) & ~0x7)

Definition at line 192 of file i7core_edac.c.

#define MC_RIR_WAY_RANK_MASK 0x7

Definition at line 193 of file i7core_edac.c.

#define MC_SAG_CH_0 0x80

Definition at line 172 of file i7core_edac.c.

#define MC_SAG_CH_1 0x84

Definition at line 173 of file i7core_edac.c.

#define MC_SAG_CH_2 0x88

Definition at line 174 of file i7core_edac.c.

#define MC_SAG_CH_3 0x8c

Definition at line 175 of file i7core_edac.c.

#define MC_SAG_CH_4 0x90

Definition at line 176 of file i7core_edac.c.

#define MC_SAG_CH_5 0x94

Definition at line 177 of file i7core_edac.c.

#define MC_SAG_CH_6 0x98

Definition at line 178 of file i7core_edac.c.

#define MC_SAG_CH_7 0x9c

Definition at line 179 of file i7core_edac.c.

#define MC_SCRUB_CONTROL 0x4c

Definition at line 110 of file i7core_edac.c.

#define MC_SSRCONTROL 0x48

Definition at line 105 of file i7core_edac.c.

#define MC_STATUS 0x4c

Definition at line 89 of file i7core_edac.c.

#define MC_TEST_ERR_RCV0 0x64

Definition at line 100 of file i7core_edac.c.

#define MC_TEST_ERR_RCV1 0x60

Definition at line 97 of file i7core_edac.c.

#define NO_MASK_CACHELINE 0x00

Definition at line 149 of file i7core_edac.c.

#define NUM_CHANS 3

Definition at line 199 of file i7core_edac.c.

#define PCI_DESCR	(	device,
		function,
		device_id
	)

Value:

.dev = (device),            \
    .func = (function),         \
    .dev_id = (device_id)

Definition at line 291 of file i7core_edac.c.

#define PCI_ID_TABLE_ENTRY ( A ) { .descr=A, .n_devs = ARRAY_SIZE(A) }

Definition at line 386 of file i7core_edac.c.

#define QUAD_RANK_PRESENT (1 << 22)

Definition at line 130 of file i7core_edac.c.

#define RANK_PRESENT_MASK 0xffff

Definition at line 138 of file i7core_edac.c.

#define RANKOFFSET ( x ) ((x & RANKOFFSET_MASK) >> 10)

Definition at line 158 of file i7core_edac.c.

#define RANKOFFSET_MASK ((1 << 12) | (1 << 11) | (1 << 10))

Definition at line 157 of file i7core_edac.c.

#define RDLCH	(	r,
		ch
	)	((((r) >> (3 + (ch * 6))) & 0x07) - 1)

Definition at line 134 of file i7core_edac.c.

#define REGISTERED_DIMM (1 << 15)

Definition at line 131 of file i7core_edac.c.

#define REPEAT_EN 0x01

Definition at line 150 of file i7core_edac.c.

#define SCRUBINTERVAL_MASK 0xffffff

Definition at line 112 of file i7core_edac.c.

#define SINGLE_QUAD_RANK_PRESENT (1 << 23)

Definition at line 129 of file i7core_edac.c.

#define SSR_MODE_DISABLE 0x00

Definition at line 106 of file i7core_edac.c.

#define SSR_MODE_ENABLE 0x01

Definition at line 107 of file i7core_edac.c.

#define SSR_MODE_MASK 0x03

Definition at line 108 of file i7core_edac.c.

#define STARTSCRUB (1 << 24)

Definition at line 111 of file i7core_edac.c.

#define THREE_DIMMS_PRESENT (1 << 24)

Definition at line 128 of file i7core_edac.c.

#define to_mci ( k ) container_of(k, struct mem_ctl_info, dev)

Definition at line 664 of file i7core_edac.c.

#define WRLCH	(	r,
		ch
	)	((((r) >> (ch * 6)) & 0x07) - 1)

Definition at line 135 of file i7core_edac.c.

Function Documentation

struct memdev_dmi_entry __attribute__ ( (__packed__) )

read

Definition at line 85 of file mpc512x_dma.c.

ATTR_ADDR_MATCH ( channel )

ATTR_ADDR_MATCH ( dimm )

ATTR_ADDR_MATCH ( rank )

ATTR_ADDR_MATCH ( bank )

ATTR_ADDR_MATCH ( page )

ATTR_ADDR_MATCH ( col )

ATTR_COUNTER ( 0 )

ATTR_COUNTER ( 1 )

ATTR_COUNTER ( 2 )

DECLARE_ADDR_MATCH	(	channel	,
		3
	)

DECLARE_ADDR_MATCH	(	dimm	,
		3
	)

DECLARE_ADDR_MATCH	(	rank	,
		4
	)

DECLARE_ADDR_MATCH	(	bank	,
		32
	)

DECLARE_ADDR_MATCH	(	page	,
		0x10000
	)

DECLARE_ADDR_MATCH	(	col	,
		0x4000
	)

DECLARE_COUNTER ( 0 )

DECLARE_COUNTER ( 1 )

DECLARE_COUNTER ( 2 )

MODULE_AUTHOR ( "Mauro Carvalho Chehab <[email protected]>" )

MODULE_AUTHOR ( "Red Hat Inc. (http://www.redhat.com)" )

MODULE_DESCRIPTION ( "MC Driver for Intel i7 Core memory controllers - " I7CORE_REVISION )

MODULE_DEVICE_TABLE	(	pci	,
		i7core_pci_tbl
	)

module_exit ( i7core_exit )

module_init ( i7core_init )

MODULE_LICENSE ( "GPL" )

module_param	(	use_pci_fixup	,
		int	,
		0444
	)

module_param	(	edac_op_state	,
		int	,
		0444
	)

MODULE_PARM_DESC	(	use_pci_fixup	,
		"Enable PCI fixup to seek for hidden devices"
	)

MODULE_PARM_DESC	(	edac_op_state	,
		"EDAC Error Reporting state:	0 = `Poll`
	)

Variable Documentation

u8 asset_tag

Definition at line 1957 of file i7core_edac.c.

u8 attributes

Definition at line 1959 of file i7core_edac.c.

u8 bank_locator

Definition at line 1951 of file i7core_edac.c.

u16 conf_mem_clk_speed

Definition at line 1961 of file i7core_edac.c.

u16 data_width

Definition at line 1946 of file i7core_edac.c.

u8 device_locator

Definition at line 1950 of file i7core_edac.c.

u8 device_set

Definition at line 1949 of file i7core_edac.c.

u32 extended_size

Definition at line 1960 of file i7core_edac.c.

u8 form

Definition at line 1948 of file i7core_edac.c.

u16 handle

Definition at line 1942 of file i7core_edac.c.

u8 length

Definition at line 1941 of file i7core_edac.c.

u8 manufacturer

Definition at line 1955 of file i7core_edac.c.

u16 mem_err_info_handle

Definition at line 1944 of file i7core_edac.c.

u8 memory_type

Definition at line 1952 of file i7core_edac.c.

u8 part_number

Definition at line 1958 of file i7core_edac.c.

u16 phys_mem_array_handle

Definition at line 1943 of file i7core_edac.c.

__u64 serial_number

Definition at line 1956 of file i7core_edac.c.

u16 size

Definition at line 1947 of file i7core_edac.c.

u16 speed

Definition at line 1954 of file i7core_edac.c.

u16 total_width

Definition at line 1945 of file i7core_edac.c.

u8 type

Definition at line 1940 of file i7core_edac.c.

u16 type_detail

Definition at line 1953 of file i7core_edac.c.

Data Structures

Macros

Functions

Variables

Macro Definition Documentation

Function Documentation

Variable Documentation