#include <linux/module.h>
#include <linux/bitops.h>
#include <linux/cdev.h>
#include <linux/dma-mapping.h>
#include <linux/dmapool.h>
#include <linux/fs.h>
#include <linux/hdlc.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/poll.h>
#include <linux/slab.h>
#include <mach/npe.h>
#include <mach/qmgr.h>

Data Structures
struct	port

struct	msg

struct	desc

Macros
#define	pr_fmt(fmt) KBUILD_MODNAME ": " fmt

#define	DEBUG_DESC 0

#define	DEBUG_RX 0

#define	DEBUG_TX 0

#define	DEBUG_PKT_BYTES 0

#define	DEBUG_CLOSE 0

#define	DRV_NAME "ixp4xx_hss"

#define	PKT_EXTRA_FLAGS 0 /* orig 1 */

#define	PKT_NUM_PIPES 1 /* 1, 2 or 4 */

#define	PKT_PIPE_FIFO_SIZEW 4 /* total 4 dwords per HSS */

#define	RX_DESCS 16 /* also length of all RX queues */

#define	TX_DESCS 16 /* also length of all TX queues */

#define	POOL_ALLOC_SIZE (sizeof(struct desc) * (RX_DESCS + TX_DESCS))

#define	RX_SIZE (HDLC_MAX_MRU + 4) /* NPE needs more space */

#define	MAX_CLOSE_WAIT 1000 /* microseconds */

#define	HSS_COUNT 2

#define	FRAME_SIZE 256 /* doesn't matter at this point */

#define	FRAME_OFFSET 0

#define	MAX_CHANNELS (FRAME_SIZE / 8)

#define	NAPI_WEIGHT 16

#define	HSS0_CHL_RXTRIG_QUEUE 12 /* orig size = 32 dwords */

#define	HSS0_PKT_RX_QUEUE 13 /* orig size = 32 dwords */

#define	HSS0_PKT_TX0_QUEUE 14 /* orig size = 16 dwords */

#define	HSS0_PKT_TX1_QUEUE 15

#define	HSS0_PKT_TX2_QUEUE 16

#define	HSS0_PKT_TX3_QUEUE 17

#define	HSS0_PKT_RXFREE0_QUEUE 18 /* orig size = 16 dwords */

#define	HSS0_PKT_RXFREE1_QUEUE 19

#define	HSS0_PKT_RXFREE2_QUEUE 20

#define	HSS0_PKT_RXFREE3_QUEUE 21

#define	HSS0_PKT_TXDONE_QUEUE 22 /* orig size = 64 dwords */

#define	HSS1_CHL_RXTRIG_QUEUE 10

#define	HSS1_PKT_RX_QUEUE 0

#define	HSS1_PKT_TX0_QUEUE 5

#define	HSS1_PKT_TX1_QUEUE 6

#define	HSS1_PKT_TX2_QUEUE 7

#define	HSS1_PKT_TX3_QUEUE 8

#define	HSS1_PKT_RXFREE0_QUEUE 1

#define	HSS1_PKT_RXFREE1_QUEUE 2

#define	HSS1_PKT_RXFREE2_QUEUE 3

#define	HSS1_PKT_RXFREE3_QUEUE 4

#define	HSS1_PKT_TXDONE_QUEUE 9

#define	NPE_PKT_MODE_HDLC 0

#define	NPE_PKT_MODE_RAW 1

#define	NPE_PKT_MODE_56KMODE 2

#define	NPE_PKT_MODE_56KENDIAN_MSB 4

#define	PKT_HDLC_IDLE_ONES 0x1 /* default = flags */

#define	PKT_HDLC_CRC_32 0x2 /* default = CRC-16 */

#define	PKT_HDLC_MSB_ENDIAN 0x4 /* default = LE */

#define	PCR_FRM_SYNC_ACTIVE_HIGH 0x40000000

#define	PCR_FRM_SYNC_FALLINGEDGE 0x80000000

#define	PCR_FRM_SYNC_RISINGEDGE 0xC0000000

#define	PCR_FRM_SYNC_OUTPUT_FALLING 0x20000000

#define	PCR_FRM_SYNC_OUTPUT_RISING 0x30000000

#define	PCR_FCLK_EDGE_RISING 0x08000000

#define	PCR_DCLK_EDGE_RISING 0x04000000

#define	PCR_SYNC_CLK_DIR_OUTPUT 0x02000000

#define	PCR_FRM_PULSE_DISABLED 0x01000000

#define	PCR_HALF_CLK_RATE 0x00200000

#define	PCR_DATA_POLARITY_INVERT 0x00100000

#define	PCR_MSB_ENDIAN 0x00080000

#define	PCR_TX_PINS_OPEN_DRAIN 0x00040000

#define	PCR_SOF_NO_FBIT 0x00020000

#define	PCR_TX_DATA_ENABLE 0x00010000

#define	PCR_TX_V56K_HIGH 0x00002000

#define	PCR_TX_V56K_HIGH_IMP 0x00004000

#define	PCR_TX_UNASS_HIGH 0x00000800

#define	PCR_TX_UNASS_HIGH_IMP 0x00001000

#define	PCR_TX_FB_HIGH_IMP 0x00000400

#define	PCR_TX_56KE_BIT_0_UNUSED 0x00000200

#define	PCR_TX_56KS_56K_DATA 0x00000100

#define	CCR_NPE_HFIFO_2_HDLC 0x04000000

#define	CCR_NPE_HFIFO_3_OR_4HDLC 0x08000000

#define	CCR_LOOPBACK 0x02000000

#define	CCR_SECOND_HSS 0x01000000

#define	CLK42X_SPEED_EXP ((0x3FF << 22) \| ( 2 << 12) \| 15) /65 KHz/

#define	CLK42X_SPEED_512KHZ (( 130 << 22) \| ( 2 << 12) \| 15)

#define	CLK42X_SPEED_1536KHZ (( 43 << 22) \| ( 18 << 12) \| 47)

#define	CLK42X_SPEED_1544KHZ (( 43 << 22) \| ( 33 << 12) \| 192)

#define	CLK42X_SPEED_2048KHZ (( 32 << 22) \| ( 34 << 12) \| 63)

#define	CLK42X_SPEED_4096KHZ (( 16 << 22) \| ( 34 << 12) \| 127)

#define	CLK42X_SPEED_8192KHZ (( 8 << 22) \| ( 34 << 12) \| 255)

#define	CLK46X_SPEED_512KHZ (( 130 << 22) \| ( 24 << 12) \| 127)

#define	CLK46X_SPEED_1536KHZ (( 43 << 22) \| (152 << 12) \| 383)

#define	CLK46X_SPEED_1544KHZ (( 43 << 22) \| ( 66 << 12) \| 385)

#define	CLK46X_SPEED_2048KHZ (( 32 << 22) \| (280 << 12) \| 511)

#define	CLK46X_SPEED_4096KHZ (( 16 << 22) \| (280 << 12) \| 1023)

#define	CLK46X_SPEED_8192KHZ (( 8 << 22) \| (280 << 12) \| 2047)

#define	TDMMAP_UNASSIGNED 0

#define	TDMMAP_HDLC 1 /* HDLC - packetized */

#define	TDMMAP_VOICE56K 2 /* Voice56K - 7-bit channelized */

#define	TDMMAP_VOICE64K 3 /* Voice64K - 8-bit channelized */

#define	HSS_CONFIG_TX_PCR 0x00 /* port configuration registers */

#define	HSS_CONFIG_RX_PCR 0x04

#define	HSS_CONFIG_CORE_CR 0x08 /* loopback control, HSS# */

#define	HSS_CONFIG_CLOCK_CR 0x0C /* clock generator control */

#define	HSS_CONFIG_TX_FCR 0x10 /* frame configuration registers */

#define	HSS_CONFIG_RX_FCR 0x14

#define	HSS_CONFIG_TX_LUT 0x18 /* channel look-up tables */

#define	HSS_CONFIG_RX_LUT 0x38

#define	PORT_CONFIG_WRITE 0x40

#define	PORT_CONFIG_LOAD 0x41

#define	PORT_ERROR_READ 0x42

#define	PKT_PIPE_FLOW_ENABLE 0x50

#define	PKT_PIPE_FLOW_DISABLE 0x51

#define	PKT_NUM_PIPES_WRITE 0x52

#define	PKT_PIPE_FIFO_SIZEW_WRITE 0x53

#define	PKT_PIPE_HDLC_CFG_WRITE 0x54

#define	PKT_PIPE_IDLE_PATTERN_WRITE 0x55

#define	PKT_PIPE_RX_SIZE_WRITE 0x56

#define	PKT_PIPE_MODE_WRITE 0x57

#define	ERR_SHUTDOWN 1 /* stop or shutdown occurrence */

#define	ERR_HDLC_ALIGN 2 /* HDLC alignment error */

#define	ERR_HDLC_FCS 3 /* HDLC Frame Check Sum error */

#define	ERR_RXFREE_Q_EMPTY

#define	ERR_HDLC_TOO_LONG 5 /* HDLC frame size too long */

#define	ERR_HDLC_ABORT 6 /* abort sequence received */

#define	ERR_DISCONNECTING 7 /* disconnect is in progress */

#define	free_buffer kfree

#define	free_buffer_irq kfree

#define	rx_desc_phys(port, n)

#define	rx_desc_ptr(port, n) (&(port)->desc_tab[n])

#define	tx_desc_phys(port, n)

#define	tx_desc_ptr(port, n) (&(port)->desc_tab[(n) + RX_DESCS])

Typedefs
typedef void	buffer_t

Functions
	MODULE_AUTHOR ("Krzysztof Halasa")

	MODULE_DESCRIPTION ("Intel IXP4xx HSS driver")

	MODULE_LICENSE ("GPL v2")

	MODULE_ALIAS ("platform:ixp4xx_hss")

	module_init (hss_init_module)

	module_exit (hss_cleanup_module)

Macro Definition Documentation

#define CCR_LOOPBACK 0x02000000

Definition at line 150 of file ixp4xx_hss.c.

#define CCR_NPE_HFIFO_2_HDLC 0x04000000

Definition at line 146 of file ixp4xx_hss.c.

#define CCR_NPE_HFIFO_3_OR_4HDLC 0x08000000

Definition at line 147 of file ixp4xx_hss.c.

#define CCR_SECOND_HSS 0x01000000

Definition at line 153 of file ixp4xx_hss.c.

#define CLK42X_SPEED_1536KHZ (( 43 << 22) | ( 18 << 12) | 47)

Definition at line 160 of file ixp4xx_hss.c.

#define CLK42X_SPEED_1544KHZ (( 43 << 22) | ( 33 << 12) | 192)

Definition at line 161 of file ixp4xx_hss.c.

#define CLK42X_SPEED_2048KHZ (( 32 << 22) | ( 34 << 12) | 63)

Definition at line 162 of file ixp4xx_hss.c.

#define CLK42X_SPEED_4096KHZ (( 16 << 22) | ( 34 << 12) | 127)

Definition at line 163 of file ixp4xx_hss.c.

#define CLK42X_SPEED_512KHZ (( 130 << 22) | ( 2 << 12) | 15)

Definition at line 159 of file ixp4xx_hss.c.

#define CLK42X_SPEED_8192KHZ (( 8 << 22) | ( 34 << 12) | 255)

Definition at line 164 of file ixp4xx_hss.c.

#define CLK42X_SPEED_EXP ((0x3FF << 22) | ( 2 << 12) | 15) /*65 KHz*/

Definition at line 157 of file ixp4xx_hss.c.

#define CLK46X_SPEED_1536KHZ (( 43 << 22) | (152 << 12) | 383)

Definition at line 167 of file ixp4xx_hss.c.

#define CLK46X_SPEED_1544KHZ (( 43 << 22) | ( 66 << 12) | 385)

Definition at line 168 of file ixp4xx_hss.c.

#define CLK46X_SPEED_2048KHZ (( 32 << 22) | (280 << 12) | 511)

Definition at line 169 of file ixp4xx_hss.c.

#define CLK46X_SPEED_4096KHZ (( 16 << 22) | (280 << 12) | 1023)

Definition at line 170 of file ixp4xx_hss.c.

#define CLK46X_SPEED_512KHZ (( 130 << 22) | ( 24 << 12) | 127)

Definition at line 166 of file ixp4xx_hss.c.

#define CLK46X_SPEED_8192KHZ (( 8 << 22) | (280 << 12) | 2047)

Definition at line 171 of file ixp4xx_hss.c.

#define DEBUG_CLOSE 0

Definition at line 32 of file ixp4xx_hss.c.

#define DEBUG_DESC 0

Definition at line 28 of file ixp4xx_hss.c.

#define DEBUG_PKT_BYTES 0

Definition at line 31 of file ixp4xx_hss.c.

#define DEBUG_RX 0

Definition at line 29 of file ixp4xx_hss.c.

#define DEBUG_TX 0

Definition at line 30 of file ixp4xx_hss.c.

#define DRV_NAME "ixp4xx_hss"

Definition at line 34 of file ixp4xx_hss.c.

#define ERR_DISCONNECTING 7 /* disconnect is in progress */

Definition at line 242 of file ixp4xx_hss.c.

#define ERR_HDLC_ABORT 6 /* abort sequence received */

Definition at line 241 of file ixp4xx_hss.c.

#define ERR_HDLC_ALIGN 2 /* HDLC alignment error */

Definition at line 237 of file ixp4xx_hss.c.

#define ERR_HDLC_FCS 3 /* HDLC Frame Check Sum error */

Definition at line 238 of file ixp4xx_hss.c.

#define ERR_HDLC_TOO_LONG 5 /* HDLC frame size too long */

Definition at line 240 of file ixp4xx_hss.c.

#define ERR_RXFREE_Q_EMPTY

Value:

4 /* RX-free queue became empty while receiving

this packet (if buf_len < pkt_len) */

Definition at line 239 of file ixp4xx_hss.c.

#define ERR_SHUTDOWN 1 /* stop or shutdown occurrence */

Definition at line 236 of file ixp4xx_hss.c.

#define FRAME_OFFSET 0

Definition at line 48 of file ixp4xx_hss.c.

#define FRAME_SIZE 256 /* doesn't matter at this point */

Definition at line 47 of file ixp4xx_hss.c.

#define free_buffer kfree

Definition at line 251 of file ixp4xx_hss.c.

#define free_buffer_irq kfree

Definition at line 252 of file ixp4xx_hss.c.

#define HSS0_CHL_RXTRIG_QUEUE 12 /* orig size = 32 dwords */

Definition at line 54 of file ixp4xx_hss.c.

#define HSS0_PKT_RX_QUEUE 13 /* orig size = 32 dwords */

Definition at line 55 of file ixp4xx_hss.c.

#define HSS0_PKT_RXFREE0_QUEUE 18 /* orig size = 16 dwords */

Definition at line 60 of file ixp4xx_hss.c.

#define HSS0_PKT_RXFREE1_QUEUE 19

Definition at line 61 of file ixp4xx_hss.c.

#define HSS0_PKT_RXFREE2_QUEUE 20

Definition at line 62 of file ixp4xx_hss.c.

#define HSS0_PKT_RXFREE3_QUEUE 21

Definition at line 63 of file ixp4xx_hss.c.

#define HSS0_PKT_TX0_QUEUE 14 /* orig size = 16 dwords */

Definition at line 56 of file ixp4xx_hss.c.

#define HSS0_PKT_TX1_QUEUE 15

Definition at line 57 of file ixp4xx_hss.c.

#define HSS0_PKT_TX2_QUEUE 16

Definition at line 58 of file ixp4xx_hss.c.

#define HSS0_PKT_TX3_QUEUE 17

Definition at line 59 of file ixp4xx_hss.c.

#define HSS0_PKT_TXDONE_QUEUE 22 /* orig size = 64 dwords */

Definition at line 64 of file ixp4xx_hss.c.

#define HSS1_CHL_RXTRIG_QUEUE 10

Definition at line 66 of file ixp4xx_hss.c.

#define HSS1_PKT_RX_QUEUE 0

Definition at line 67 of file ixp4xx_hss.c.

#define HSS1_PKT_RXFREE0_QUEUE 1

Definition at line 72 of file ixp4xx_hss.c.

#define HSS1_PKT_RXFREE1_QUEUE 2

Definition at line 73 of file ixp4xx_hss.c.

#define HSS1_PKT_RXFREE2_QUEUE 3

Definition at line 74 of file ixp4xx_hss.c.

#define HSS1_PKT_RXFREE3_QUEUE 4

Definition at line 75 of file ixp4xx_hss.c.

#define HSS1_PKT_TX0_QUEUE 5

Definition at line 68 of file ixp4xx_hss.c.

#define HSS1_PKT_TX1_QUEUE 6

Definition at line 69 of file ixp4xx_hss.c.

#define HSS1_PKT_TX2_QUEUE 7

Definition at line 70 of file ixp4xx_hss.c.

#define HSS1_PKT_TX3_QUEUE 8

Definition at line 71 of file ixp4xx_hss.c.

#define HSS1_PKT_TXDONE_QUEUE 9

Definition at line 76 of file ixp4xx_hss.c.

#define HSS_CONFIG_CLOCK_CR 0x0C /* clock generator control */

Definition at line 207 of file ixp4xx_hss.c.

#define HSS_CONFIG_CORE_CR 0x08 /* loopback control, HSS# */

Definition at line 206 of file ixp4xx_hss.c.

#define HSS_CONFIG_RX_FCR 0x14

Definition at line 209 of file ixp4xx_hss.c.

#define HSS_CONFIG_RX_LUT 0x38

Definition at line 211 of file ixp4xx_hss.c.

#define HSS_CONFIG_RX_PCR 0x04

Definition at line 205 of file ixp4xx_hss.c.

#define HSS_CONFIG_TX_FCR 0x10 /* frame configuration registers */

Definition at line 208 of file ixp4xx_hss.c.

#define HSS_CONFIG_TX_LUT 0x18 /* channel look-up tables */

Definition at line 210 of file ixp4xx_hss.c.

#define HSS_CONFIG_TX_PCR 0x00 /* port configuration registers */

Definition at line 204 of file ixp4xx_hss.c.

#define HSS_COUNT 2

Definition at line 46 of file ixp4xx_hss.c.

#define MAX_CHANNELS (FRAME_SIZE / 8)

Definition at line 49 of file ixp4xx_hss.c.

#define MAX_CLOSE_WAIT 1000 /* microseconds */

Definition at line 45 of file ixp4xx_hss.c.

#define NAPI_WEIGHT 16

Definition at line 51 of file ixp4xx_hss.c.

#define NPE_PKT_MODE_56KENDIAN_MSB 4

Definition at line 81 of file ixp4xx_hss.c.

#define NPE_PKT_MODE_56KMODE 2

Definition at line 80 of file ixp4xx_hss.c.

#define NPE_PKT_MODE_HDLC 0

Definition at line 78 of file ixp4xx_hss.c.

#define NPE_PKT_MODE_RAW 1

Definition at line 79 of file ixp4xx_hss.c.

#define PCR_DATA_POLARITY_INVERT 0x00100000

Definition at line 113 of file ixp4xx_hss.c.

#define PCR_DCLK_EDGE_RISING 0x04000000

Definition at line 101 of file ixp4xx_hss.c.

#define PCR_FCLK_EDGE_RISING 0x08000000

Definition at line 100 of file ixp4xx_hss.c.

#define PCR_FRM_PULSE_DISABLED 0x01000000

Definition at line 107 of file ixp4xx_hss.c.

#define PCR_FRM_SYNC_ACTIVE_HIGH 0x40000000

Definition at line 91 of file ixp4xx_hss.c.

#define PCR_FRM_SYNC_FALLINGEDGE 0x80000000

Definition at line 92 of file ixp4xx_hss.c.

#define PCR_FRM_SYNC_OUTPUT_FALLING 0x20000000

Definition at line 96 of file ixp4xx_hss.c.

#define PCR_FRM_SYNC_OUTPUT_RISING 0x30000000

Definition at line 97 of file ixp4xx_hss.c.

#define PCR_FRM_SYNC_RISINGEDGE 0xC0000000

Definition at line 93 of file ixp4xx_hss.c.

#define PCR_HALF_CLK_RATE 0x00200000

Definition at line 110 of file ixp4xx_hss.c.

#define PCR_MSB_ENDIAN 0x00080000

Definition at line 116 of file ixp4xx_hss.c.

#define PCR_SOF_NO_FBIT 0x00020000

Definition at line 122 of file ixp4xx_hss.c.

#define PCR_SYNC_CLK_DIR_OUTPUT 0x02000000

Definition at line 104 of file ixp4xx_hss.c.

#define PCR_TX_56KE_BIT_0_UNUSED 0x00000200

Definition at line 139 of file ixp4xx_hss.c.

#define PCR_TX_56KS_56K_DATA 0x00000100

Definition at line 142 of file ixp4xx_hss.c.

#define PCR_TX_DATA_ENABLE 0x00010000

Definition at line 125 of file ixp4xx_hss.c.

#define PCR_TX_FB_HIGH_IMP 0x00000400

Definition at line 136 of file ixp4xx_hss.c.

#define PCR_TX_PINS_OPEN_DRAIN 0x00040000

Definition at line 119 of file ixp4xx_hss.c.

#define PCR_TX_UNASS_HIGH 0x00000800

Definition at line 132 of file ixp4xx_hss.c.

#define PCR_TX_UNASS_HIGH_IMP 0x00001000

Definition at line 133 of file ixp4xx_hss.c.

#define PCR_TX_V56K_HIGH 0x00002000

Definition at line 128 of file ixp4xx_hss.c.

#define PCR_TX_V56K_HIGH_IMP 0x00004000

Definition at line 129 of file ixp4xx_hss.c.

#define PKT_EXTRA_FLAGS 0 /* orig 1 */

Definition at line 36 of file ixp4xx_hss.c.

#define PKT_HDLC_CRC_32 0x2 /* default = CRC-16 */

Definition at line 85 of file ixp4xx_hss.c.

#define PKT_HDLC_IDLE_ONES 0x1 /* default = flags */

Definition at line 84 of file ixp4xx_hss.c.

#define PKT_HDLC_MSB_ENDIAN 0x4 /* default = LE */

Definition at line 86 of file ixp4xx_hss.c.

#define PKT_NUM_PIPES 1 /* 1, 2 or 4 */

Definition at line 37 of file ixp4xx_hss.c.

#define PKT_NUM_PIPES_WRITE 0x52

Definition at line 228 of file ixp4xx_hss.c.

#define PKT_PIPE_FIFO_SIZEW 4 /* total 4 dwords per HSS */

Definition at line 38 of file ixp4xx_hss.c.

#define PKT_PIPE_FIFO_SIZEW_WRITE 0x53

Definition at line 229 of file ixp4xx_hss.c.

#define PKT_PIPE_FLOW_DISABLE 0x51

Definition at line 227 of file ixp4xx_hss.c.

#define PKT_PIPE_FLOW_ENABLE 0x50

Definition at line 226 of file ixp4xx_hss.c.

#define PKT_PIPE_HDLC_CFG_WRITE 0x54

Definition at line 230 of file ixp4xx_hss.c.

#define PKT_PIPE_IDLE_PATTERN_WRITE 0x55

Definition at line 231 of file ixp4xx_hss.c.

#define PKT_PIPE_MODE_WRITE 0x57

Definition at line 233 of file ixp4xx_hss.c.

#define PKT_PIPE_RX_SIZE_WRITE 0x56

Definition at line 232 of file ixp4xx_hss.c.

#define POOL_ALLOC_SIZE (sizeof(struct desc) * (RX_DESCS + TX_DESCS))

Definition at line 43 of file ixp4xx_hss.c.

#define PORT_CONFIG_LOAD 0x41

Definition at line 219 of file ixp4xx_hss.c.

#define PORT_CONFIG_WRITE 0x40

Definition at line 216 of file ixp4xx_hss.c.

#define PORT_ERROR_READ 0x42

Definition at line 222 of file ixp4xx_hss.c.

#define pr_fmt ( fmt ) KBUILD_MODNAME ": " fmt

Definition at line 11 of file ixp4xx_hss.c.

#define rx_desc_phys	(	port,
		n
	)

Value:

((port)->desc_tab_phys + \

(n) * sizeof(struct desc))

Definition at line 313 of file ixp4xx_hss.c.

#define rx_desc_ptr	(	port,
		n
	)	(&(port)->desc_tab[n])

Definition at line 315 of file ixp4xx_hss.c.

#define RX_DESCS 16 /* also length of all RX queues */

Definition at line 40 of file ixp4xx_hss.c.

#define RX_SIZE (HDLC_MAX_MRU + 4) /* NPE needs more space */

Definition at line 44 of file ixp4xx_hss.c.

#define TDMMAP_HDLC 1 /* HDLC - packetized */

Definition at line 199 of file ixp4xx_hss.c.

#define TDMMAP_UNASSIGNED 0

Definition at line 198 of file ixp4xx_hss.c.

#define TDMMAP_VOICE56K 2 /* Voice56K - 7-bit channelized */

Definition at line 200 of file ixp4xx_hss.c.

#define TDMMAP_VOICE64K 3 /* Voice64K - 8-bit channelized */

Definition at line 201 of file ixp4xx_hss.c.

#define tx_desc_phys	(	port,
		n
	)

Value:

((port)->desc_tab_phys + \

((n) + RX_DESCS) * sizeof(struct desc))

Definition at line 317 of file ixp4xx_hss.c.

#define tx_desc_ptr	(	port,
		n
	)	(&(port)->desc_tab[(n) + RX_DESCS])

Definition at line 319 of file ixp4xx_hss.c.

#define TX_DESCS 16 /* also length of all TX queues */

Definition at line 41 of file ixp4xx_hss.c.

Typedef Documentation

typedef void buffer_t

Definition at line 250 of file ixp4xx_hss.c.

Function Documentation

MODULE_ALIAS ( "platform:ixp4xx_hss" )

MODULE_AUTHOR ( "Krzysztof Halasa" )

MODULE_DESCRIPTION ( "Intel IXP4xx HSS driver" )

module_exit ( hss_cleanup_module )

module_init ( hss_init_module )

MODULE_LICENSE ( "GPL v2" )

Variable Documentation

static void rx

Definition at line 330 of file ixp4xx_hss.c.

int rxfree

Definition at line 330 of file ixp4xx_hss.c.

int tx

Definition at line 330 of file ixp4xx_hss.c.

int txdone

Definition at line 330 of file ixp4xx_hss.c.

Data Structures

Macros

Typedefs

Functions

Macro Definition Documentation

Typedef Documentation

Function Documentation

Variable Documentation