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20 #ifndef _ASM_X86_AMD_IOMMU_TYPES_H
21 #define _ASM_X86_AMD_IOMMU_TYPES_H
23 #include <linux/types.h>
25 #include <linux/list.h>
36 #define DEV_TABLE_ENTRY_SIZE 32
37 #define ALIAS_TABLE_ENTRY_SIZE 2
38 #define RLOOKUP_TABLE_ENTRY_SIZE (sizeof(void *))
41 #define MMIO_REGION_LENGTH 0x4000
44 #define MMIO_CAP_HDR_OFFSET 0x00
45 #define MMIO_RANGE_OFFSET 0x0c
46 #define MMIO_MISC_OFFSET 0x10
49 #define MMIO_RANGE_LD_MASK 0xff000000
50 #define MMIO_RANGE_FD_MASK 0x00ff0000
51 #define MMIO_RANGE_BUS_MASK 0x0000ff00
52 #define MMIO_RANGE_LD_SHIFT 24
53 #define MMIO_RANGE_FD_SHIFT 16
54 #define MMIO_RANGE_BUS_SHIFT 8
55 #define MMIO_GET_LD(x) (((x) & MMIO_RANGE_LD_MASK) >> MMIO_RANGE_LD_SHIFT)
56 #define MMIO_GET_FD(x) (((x) & MMIO_RANGE_FD_MASK) >> MMIO_RANGE_FD_SHIFT)
57 #define MMIO_GET_BUS(x) (((x) & MMIO_RANGE_BUS_MASK) >> MMIO_RANGE_BUS_SHIFT)
58 #define MMIO_MSI_NUM(x) ((x) & 0x1f)
61 #define MMIO_EXCL_ENABLE_MASK 0x01ULL
62 #define MMIO_EXCL_ALLOW_MASK 0x02ULL
65 #define MMIO_DEV_TABLE_OFFSET 0x0000
66 #define MMIO_CMD_BUF_OFFSET 0x0008
67 #define MMIO_EVT_BUF_OFFSET 0x0010
68 #define MMIO_CONTROL_OFFSET 0x0018
69 #define MMIO_EXCL_BASE_OFFSET 0x0020
70 #define MMIO_EXCL_LIMIT_OFFSET 0x0028
71 #define MMIO_EXT_FEATURES 0x0030
72 #define MMIO_PPR_LOG_OFFSET 0x0038
73 #define MMIO_CMD_HEAD_OFFSET 0x2000
74 #define MMIO_CMD_TAIL_OFFSET 0x2008
75 #define MMIO_EVT_HEAD_OFFSET 0x2010
76 #define MMIO_EVT_TAIL_OFFSET 0x2018
77 #define MMIO_STATUS_OFFSET 0x2020
78 #define MMIO_PPR_HEAD_OFFSET 0x2030
79 #define MMIO_PPR_TAIL_OFFSET 0x2038
83 #define FEATURE_PREFETCH (1ULL<<0)
84 #define FEATURE_PPR (1ULL<<1)
85 #define FEATURE_X2APIC (1ULL<<2)
86 #define FEATURE_NX (1ULL<<3)
87 #define FEATURE_GT (1ULL<<4)
88 #define FEATURE_IA (1ULL<<6)
89 #define FEATURE_GA (1ULL<<7)
90 #define FEATURE_HE (1ULL<<8)
91 #define FEATURE_PC (1ULL<<9)
93 #define FEATURE_PASID_SHIFT 32
94 #define FEATURE_PASID_MASK (0x1fULL << FEATURE_PASID_SHIFT)
96 #define FEATURE_GLXVAL_SHIFT 14
97 #define FEATURE_GLXVAL_MASK (0x03ULL << FEATURE_GLXVAL_SHIFT)
99 #define PASID_MASK 0x000fffff
102 #define MMIO_STATUS_COM_WAIT_INT_MASK (1 << 2)
103 #define MMIO_STATUS_PPR_INT_MASK (1 << 6)
106 #define EVENT_ENTRY_SIZE 0x10
107 #define EVENT_TYPE_SHIFT 28
108 #define EVENT_TYPE_MASK 0xf
109 #define EVENT_TYPE_ILL_DEV 0x1
110 #define EVENT_TYPE_IO_FAULT 0x2
111 #define EVENT_TYPE_DEV_TAB_ERR 0x3
112 #define EVENT_TYPE_PAGE_TAB_ERR 0x4
113 #define EVENT_TYPE_ILL_CMD 0x5
114 #define EVENT_TYPE_CMD_HARD_ERR 0x6
115 #define EVENT_TYPE_IOTLB_INV_TO 0x7
116 #define EVENT_TYPE_INV_DEV_REQ 0x8
117 #define EVENT_DEVID_MASK 0xffff
118 #define EVENT_DEVID_SHIFT 0
119 #define EVENT_DOMID_MASK 0xffff
120 #define EVENT_DOMID_SHIFT 0
121 #define EVENT_FLAGS_MASK 0xfff
122 #define EVENT_FLAGS_SHIFT 0x10
125 #define CONTROL_IOMMU_EN 0x00ULL
126 #define CONTROL_HT_TUN_EN 0x01ULL
127 #define CONTROL_EVT_LOG_EN 0x02ULL
128 #define CONTROL_EVT_INT_EN 0x03ULL
129 #define CONTROL_COMWAIT_EN 0x04ULL
130 #define CONTROL_INV_TIMEOUT 0x05ULL
131 #define CONTROL_PASSPW_EN 0x08ULL
132 #define CONTROL_RESPASSPW_EN 0x09ULL
133 #define CONTROL_COHERENT_EN 0x0aULL
134 #define CONTROL_ISOC_EN 0x0bULL
135 #define CONTROL_CMDBUF_EN 0x0cULL
136 #define CONTROL_PPFLOG_EN 0x0dULL
137 #define CONTROL_PPFINT_EN 0x0eULL
138 #define CONTROL_PPR_EN 0x0fULL
139 #define CONTROL_GT_EN 0x10ULL
141 #define CTRL_INV_TO_MASK (7 << CONTROL_INV_TIMEOUT)
142 #define CTRL_INV_TO_NONE 0
143 #define CTRL_INV_TO_1MS 1
144 #define CTRL_INV_TO_10MS 2
145 #define CTRL_INV_TO_100MS 3
146 #define CTRL_INV_TO_1S 4
147 #define CTRL_INV_TO_10S 5
148 #define CTRL_INV_TO_100S 6
151 #define CMD_COMPL_WAIT 0x01
152 #define CMD_INV_DEV_ENTRY 0x02
153 #define CMD_INV_IOMMU_PAGES 0x03
154 #define CMD_INV_IOTLB_PAGES 0x04
155 #define CMD_INV_IRT 0x05
156 #define CMD_COMPLETE_PPR 0x07
157 #define CMD_INV_ALL 0x08
159 #define CMD_COMPL_WAIT_STORE_MASK 0x01
160 #define CMD_COMPL_WAIT_INT_MASK 0x02
161 #define CMD_INV_IOMMU_PAGES_SIZE_MASK 0x01
162 #define CMD_INV_IOMMU_PAGES_PDE_MASK 0x02
163 #define CMD_INV_IOMMU_PAGES_GN_MASK 0x04
165 #define PPR_STATUS_MASK 0xf
166 #define PPR_STATUS_SHIFT 12
168 #define CMD_INV_IOMMU_ALL_PAGES_ADDRESS 0x7fffffffffffffffULL
171 #define DEV_ENTRY_VALID 0x00
172 #define DEV_ENTRY_TRANSLATION 0x01
173 #define DEV_ENTRY_IR 0x3d
174 #define DEV_ENTRY_IW 0x3e
175 #define DEV_ENTRY_NO_PAGE_FAULT 0x62
176 #define DEV_ENTRY_EX 0x67
177 #define DEV_ENTRY_SYSMGT1 0x68
178 #define DEV_ENTRY_SYSMGT2 0x69
179 #define DEV_ENTRY_IRQ_TBL_EN 0x80
180 #define DEV_ENTRY_INIT_PASS 0xb8
181 #define DEV_ENTRY_EINT_PASS 0xb9
182 #define DEV_ENTRY_NMI_PASS 0xba
183 #define DEV_ENTRY_LINT0_PASS 0xbe
184 #define DEV_ENTRY_LINT1_PASS 0xbf
185 #define DEV_ENTRY_MODE_MASK 0x07
186 #define DEV_ENTRY_MODE_SHIFT 0x09
188 #define MAX_DEV_TABLE_ENTRIES 0xffff
191 #define CMD_BUFFER_SIZE 8192
192 #define CMD_BUFFER_UNINITIALIZED 1
193 #define CMD_BUFFER_ENTRIES 512
194 #define MMIO_CMD_SIZE_SHIFT 56
195 #define MMIO_CMD_SIZE_512 (0x9ULL << MMIO_CMD_SIZE_SHIFT)
198 #define EVT_BUFFER_SIZE 8192
199 #define EVT_LEN_MASK (0x9ULL << 56)
202 #define PPR_LOG_ENTRIES 512
203 #define PPR_LOG_SIZE_SHIFT 56
204 #define PPR_LOG_SIZE_512 (0x9ULL << PPR_LOG_SIZE_SHIFT)
205 #define PPR_ENTRY_SIZE 16
206 #define PPR_LOG_SIZE (PPR_ENTRY_SIZE * PPR_LOG_ENTRIES)
208 #define PPR_REQ_TYPE(x) (((x) >> 60) & 0xfULL)
209 #define PPR_FLAGS(x) (((x) >> 48) & 0xfffULL)
210 #define PPR_DEVID(x) ((x) & 0xffffULL)
211 #define PPR_TAG(x) (((x) >> 32) & 0x3ffULL)
212 #define PPR_PASID1(x) (((x) >> 16) & 0xffffULL)
213 #define PPR_PASID2(x) (((x) >> 42) & 0xfULL)
214 #define PPR_PASID(x) ((PPR_PASID2(x) << 16) | PPR_PASID1(x))
216 #define PPR_REQ_FAULT 0x01
218 #define PAGE_MODE_NONE 0x00
219 #define PAGE_MODE_1_LEVEL 0x01
220 #define PAGE_MODE_2_LEVEL 0x02
221 #define PAGE_MODE_3_LEVEL 0x03
222 #define PAGE_MODE_4_LEVEL 0x04
223 #define PAGE_MODE_5_LEVEL 0x05
224 #define PAGE_MODE_6_LEVEL 0x06
226 #define PM_LEVEL_SHIFT(x) (12 + ((x) * 9))
227 #define PM_LEVEL_SIZE(x) (((x) < 6) ? \
228 ((1ULL << PM_LEVEL_SHIFT((x))) - 1): \
229 (0xffffffffffffffffULL))
230 #define PM_LEVEL_INDEX(x, a) (((a) >> PM_LEVEL_SHIFT((x))) & 0x1ffULL)
231 #define PM_LEVEL_ENC(x) (((x) << 9) & 0xe00ULL)
232 #define PM_LEVEL_PDE(x, a) ((a) | PM_LEVEL_ENC((x)) | \
233 IOMMU_PTE_P | IOMMU_PTE_IR | IOMMU_PTE_IW)
234 #define PM_PTE_LEVEL(pte) (((pte) >> 9) & 0x7ULL)
237 #define PM_ADDR_MASK 0x000ffffffffff000ULL
238 #define PM_MAP_MASK(lvl) (PM_ADDR_MASK & \
239 (~((1ULL << (12 + ((lvl) * 9))) - 1)))
240 #define PM_ALIGNED(lvl, addr) ((PM_MAP_MASK(lvl) & (addr)) == (addr))
246 #define PAGE_SIZE_LEVEL(pagesize) \
247 ((__ffs(pagesize) - 12) / 9)
252 #define PAGE_SIZE_PTE_COUNT(pagesize) \
253 (1ULL << ((__ffs(pagesize) - 12) % 9))
259 #define PAGE_SIZE_ALIGN(address, pagesize) \
260 ((address) & ~((pagesize) - 1))
266 #define PAGE_SIZE_PTE(address, pagesize) \
267 (((address) | ((pagesize) - 1)) & \
268 (~(pagesize >> 1)) & PM_ADDR_MASK)
273 #define PTE_PAGE_SIZE(pte) \
274 (1ULL << (1 + ffz(((pte) | 0xfffULL))))
276 #define IOMMU_PTE_P (1ULL << 0)
277 #define IOMMU_PTE_TV (1ULL << 1)
278 #define IOMMU_PTE_U (1ULL << 59)
279 #define IOMMU_PTE_FC (1ULL << 60)
280 #define IOMMU_PTE_IR (1ULL << 61)
281 #define IOMMU_PTE_IW (1ULL << 62)
283 #define DTE_FLAG_IOTLB (0x01UL << 32)
284 #define DTE_FLAG_GV (0x01ULL << 55)
285 #define DTE_GLX_SHIFT (56)
286 #define DTE_GLX_MASK (3)
288 #define DTE_GCR3_VAL_A(x) (((x) >> 12) & 0x00007ULL)
289 #define DTE_GCR3_VAL_B(x) (((x) >> 15) & 0x0ffffULL)
290 #define DTE_GCR3_VAL_C(x) (((x) >> 31) & 0xfffffULL)
292 #define DTE_GCR3_INDEX_A 0
293 #define DTE_GCR3_INDEX_B 1
294 #define DTE_GCR3_INDEX_C 1
296 #define DTE_GCR3_SHIFT_A 58
297 #define DTE_GCR3_SHIFT_B 16
298 #define DTE_GCR3_SHIFT_C 43
300 #define GCR3_VALID 0x01ULL
302 #define IOMMU_PAGE_MASK (((1ULL << 52) - 1) & ~0xfffULL)
303 #define IOMMU_PTE_PRESENT(pte) ((pte) & IOMMU_PTE_P)
304 #define IOMMU_PTE_PAGE(pte) (phys_to_virt((pte) & IOMMU_PAGE_MASK))
305 #define IOMMU_PTE_MODE(pte) (((pte) >> 9) & 0x07)
307 #define IOMMU_PROT_MASK 0x03
308 #define IOMMU_PROT_IR 0x01
309 #define IOMMU_PROT_IW 0x02
312 #define IOMMU_CAP_IOTLB 24
313 #define IOMMU_CAP_NPCACHE 26
314 #define IOMMU_CAP_EFR 27
316 #define MAX_DOMAIN_ID 65536
319 #define PCI_BUS(x) (((x) >> 8) & 0xff)
322 #define PD_DMA_OPS_MASK (1UL << 0)
323 #define PD_DEFAULT_MASK (1UL << 1)
325 #define PD_PASSTHROUGH_MASK (1UL << 2)
327 #define PD_IOMMUV2_MASK (1UL << 3)
330 #define DUMP_printk(format, arg...) \
332 if (amd_iommu_dump) \
333 printk(KERN_INFO "AMD-Vi: " format, ## arg); \
341 #define MAX_IRQS_PER_TABLE 256
342 #define IRQ_TABLE_ALIGNMENT 128
361 #define for_each_iommu(iommu) \
362 list_for_each_entry((iommu), &amd_iommu_list, list)
363 #define for_each_iommu_safe(iommu, next) \
364 list_for_each_entry_safe((iommu), (next), &amd_iommu_list, list)
366 #define APERTURE_RANGE_SHIFT 27
367 #define APERTURE_RANGE_SIZE (1ULL << APERTURE_RANGE_SHIFT)
368 #define APERTURE_RANGE_PAGES (APERTURE_RANGE_SIZE >> PAGE_SHIFT)
369 #define APERTURE_MAX_RANGES 32
370 #define APERTURE_RANGE_INDEX(a) ((a) >> APERTURE_RANGE_SHIFT)
371 #define APERTURE_PAGE_INDEX(a) (((a) >> 21) & 0x3fULL)
387 #define PPR_FAULT_EXEC (1 << 1)
388 #define PPR_FAULT_READ (1 << 2)
389 #define PPR_FAULT_WRITE (1 << 5)
390 #define PPR_FAULT_USER (1 << 6)
391 #define PPR_FAULT_RSVD (1 << 7)
392 #define PPR_FAULT_GN (1 << 8)
712 static inline int get_ioapic_devid(
int id)
724 static inline int get_hpet_devid(
int id)
736 #ifdef CONFIG_AMD_IOMMU_STATS
738 struct __iommu_counter {
744 #define DECLARE_STATS_COUNTER(nm) \
745 static struct __iommu_counter nm = { \
749 #define INC_STATS_COUNTER(name) name.value += 1
750 #define ADD_STATS_COUNTER(name, x) name.value += (x)
751 #define SUB_STATS_COUNTER(name, x) name.value -= (x)
755 #define DECLARE_STATS_COUNTER(name)
756 #define INC_STATS_COUNTER(name)
757 #define ADD_STATS_COUNTER(name, x)
758 #define SUB_STATS_COUNTER(name, x)