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amd_iommu_types.h
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1 /*
2  * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
3  * Author: Joerg Roedel <[email protected]>
4  * Leo Duran <[email protected]>
5  *
6  * This program is free software; you can redistribute it and/or modify it
7  * under the terms of the GNU General Public License version 2 as published
8  * by the Free Software Foundation.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13  * GNU General Public License for more details.
14  *
15  * You should have received a copy of the GNU General Public License
16  * along with this program; if not, write to the Free Software
17  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18  */
19 
20 #ifndef _ASM_X86_AMD_IOMMU_TYPES_H
21 #define _ASM_X86_AMD_IOMMU_TYPES_H
22 
23 #include <linux/types.h>
24 #include <linux/mutex.h>
25 #include <linux/list.h>
26 #include <linux/spinlock.h>
27 
28 /*
29  * Maximum number of IOMMUs supported
30  */
31 #define MAX_IOMMUS 32
32 
33 /*
34  * some size calculation constants
35  */
36 #define DEV_TABLE_ENTRY_SIZE 32
37 #define ALIAS_TABLE_ENTRY_SIZE 2
38 #define RLOOKUP_TABLE_ENTRY_SIZE (sizeof(void *))
39 
40 /* Length of the MMIO region for the AMD IOMMU */
41 #define MMIO_REGION_LENGTH 0x4000
42 
43 /* Capability offsets used by the driver */
44 #define MMIO_CAP_HDR_OFFSET 0x00
45 #define MMIO_RANGE_OFFSET 0x0c
46 #define MMIO_MISC_OFFSET 0x10
47 
48 /* Masks, shifts and macros to parse the device range capability */
49 #define MMIO_RANGE_LD_MASK 0xff000000
50 #define MMIO_RANGE_FD_MASK 0x00ff0000
51 #define MMIO_RANGE_BUS_MASK 0x0000ff00
52 #define MMIO_RANGE_LD_SHIFT 24
53 #define MMIO_RANGE_FD_SHIFT 16
54 #define MMIO_RANGE_BUS_SHIFT 8
55 #define MMIO_GET_LD(x) (((x) & MMIO_RANGE_LD_MASK) >> MMIO_RANGE_LD_SHIFT)
56 #define MMIO_GET_FD(x) (((x) & MMIO_RANGE_FD_MASK) >> MMIO_RANGE_FD_SHIFT)
57 #define MMIO_GET_BUS(x) (((x) & MMIO_RANGE_BUS_MASK) >> MMIO_RANGE_BUS_SHIFT)
58 #define MMIO_MSI_NUM(x) ((x) & 0x1f)
59 
60 /* Flag masks for the AMD IOMMU exclusion range */
61 #define MMIO_EXCL_ENABLE_MASK 0x01ULL
62 #define MMIO_EXCL_ALLOW_MASK 0x02ULL
63 
64 /* Used offsets into the MMIO space */
65 #define MMIO_DEV_TABLE_OFFSET 0x0000
66 #define MMIO_CMD_BUF_OFFSET 0x0008
67 #define MMIO_EVT_BUF_OFFSET 0x0010
68 #define MMIO_CONTROL_OFFSET 0x0018
69 #define MMIO_EXCL_BASE_OFFSET 0x0020
70 #define MMIO_EXCL_LIMIT_OFFSET 0x0028
71 #define MMIO_EXT_FEATURES 0x0030
72 #define MMIO_PPR_LOG_OFFSET 0x0038
73 #define MMIO_CMD_HEAD_OFFSET 0x2000
74 #define MMIO_CMD_TAIL_OFFSET 0x2008
75 #define MMIO_EVT_HEAD_OFFSET 0x2010
76 #define MMIO_EVT_TAIL_OFFSET 0x2018
77 #define MMIO_STATUS_OFFSET 0x2020
78 #define MMIO_PPR_HEAD_OFFSET 0x2030
79 #define MMIO_PPR_TAIL_OFFSET 0x2038
80 
81 
82 /* Extended Feature Bits */
83 #define FEATURE_PREFETCH (1ULL<<0)
84 #define FEATURE_PPR (1ULL<<1)
85 #define FEATURE_X2APIC (1ULL<<2)
86 #define FEATURE_NX (1ULL<<3)
87 #define FEATURE_GT (1ULL<<4)
88 #define FEATURE_IA (1ULL<<6)
89 #define FEATURE_GA (1ULL<<7)
90 #define FEATURE_HE (1ULL<<8)
91 #define FEATURE_PC (1ULL<<9)
92 
93 #define FEATURE_PASID_SHIFT 32
94 #define FEATURE_PASID_MASK (0x1fULL << FEATURE_PASID_SHIFT)
95 
96 #define FEATURE_GLXVAL_SHIFT 14
97 #define FEATURE_GLXVAL_MASK (0x03ULL << FEATURE_GLXVAL_SHIFT)
98 
99 #define PASID_MASK 0x000fffff
100 
101 /* MMIO status bits */
102 #define MMIO_STATUS_COM_WAIT_INT_MASK (1 << 2)
103 #define MMIO_STATUS_PPR_INT_MASK (1 << 6)
104 
105 /* event logging constants */
106 #define EVENT_ENTRY_SIZE 0x10
107 #define EVENT_TYPE_SHIFT 28
108 #define EVENT_TYPE_MASK 0xf
109 #define EVENT_TYPE_ILL_DEV 0x1
110 #define EVENT_TYPE_IO_FAULT 0x2
111 #define EVENT_TYPE_DEV_TAB_ERR 0x3
112 #define EVENT_TYPE_PAGE_TAB_ERR 0x4
113 #define EVENT_TYPE_ILL_CMD 0x5
114 #define EVENT_TYPE_CMD_HARD_ERR 0x6
115 #define EVENT_TYPE_IOTLB_INV_TO 0x7
116 #define EVENT_TYPE_INV_DEV_REQ 0x8
117 #define EVENT_DEVID_MASK 0xffff
118 #define EVENT_DEVID_SHIFT 0
119 #define EVENT_DOMID_MASK 0xffff
120 #define EVENT_DOMID_SHIFT 0
121 #define EVENT_FLAGS_MASK 0xfff
122 #define EVENT_FLAGS_SHIFT 0x10
123 
124 /* feature control bits */
125 #define CONTROL_IOMMU_EN 0x00ULL
126 #define CONTROL_HT_TUN_EN 0x01ULL
127 #define CONTROL_EVT_LOG_EN 0x02ULL
128 #define CONTROL_EVT_INT_EN 0x03ULL
129 #define CONTROL_COMWAIT_EN 0x04ULL
130 #define CONTROL_INV_TIMEOUT 0x05ULL
131 #define CONTROL_PASSPW_EN 0x08ULL
132 #define CONTROL_RESPASSPW_EN 0x09ULL
133 #define CONTROL_COHERENT_EN 0x0aULL
134 #define CONTROL_ISOC_EN 0x0bULL
135 #define CONTROL_CMDBUF_EN 0x0cULL
136 #define CONTROL_PPFLOG_EN 0x0dULL
137 #define CONTROL_PPFINT_EN 0x0eULL
138 #define CONTROL_PPR_EN 0x0fULL
139 #define CONTROL_GT_EN 0x10ULL
140 
141 #define CTRL_INV_TO_MASK (7 << CONTROL_INV_TIMEOUT)
142 #define CTRL_INV_TO_NONE 0
143 #define CTRL_INV_TO_1MS 1
144 #define CTRL_INV_TO_10MS 2
145 #define CTRL_INV_TO_100MS 3
146 #define CTRL_INV_TO_1S 4
147 #define CTRL_INV_TO_10S 5
148 #define CTRL_INV_TO_100S 6
149 
150 /* command specific defines */
151 #define CMD_COMPL_WAIT 0x01
152 #define CMD_INV_DEV_ENTRY 0x02
153 #define CMD_INV_IOMMU_PAGES 0x03
154 #define CMD_INV_IOTLB_PAGES 0x04
155 #define CMD_INV_IRT 0x05
156 #define CMD_COMPLETE_PPR 0x07
157 #define CMD_INV_ALL 0x08
158 
159 #define CMD_COMPL_WAIT_STORE_MASK 0x01
160 #define CMD_COMPL_WAIT_INT_MASK 0x02
161 #define CMD_INV_IOMMU_PAGES_SIZE_MASK 0x01
162 #define CMD_INV_IOMMU_PAGES_PDE_MASK 0x02
163 #define CMD_INV_IOMMU_PAGES_GN_MASK 0x04
164 
165 #define PPR_STATUS_MASK 0xf
166 #define PPR_STATUS_SHIFT 12
167 
168 #define CMD_INV_IOMMU_ALL_PAGES_ADDRESS 0x7fffffffffffffffULL
169 
170 /* macros and definitions for device table entries */
171 #define DEV_ENTRY_VALID 0x00
172 #define DEV_ENTRY_TRANSLATION 0x01
173 #define DEV_ENTRY_IR 0x3d
174 #define DEV_ENTRY_IW 0x3e
175 #define DEV_ENTRY_NO_PAGE_FAULT 0x62
176 #define DEV_ENTRY_EX 0x67
177 #define DEV_ENTRY_SYSMGT1 0x68
178 #define DEV_ENTRY_SYSMGT2 0x69
179 #define DEV_ENTRY_IRQ_TBL_EN 0x80
180 #define DEV_ENTRY_INIT_PASS 0xb8
181 #define DEV_ENTRY_EINT_PASS 0xb9
182 #define DEV_ENTRY_NMI_PASS 0xba
183 #define DEV_ENTRY_LINT0_PASS 0xbe
184 #define DEV_ENTRY_LINT1_PASS 0xbf
185 #define DEV_ENTRY_MODE_MASK 0x07
186 #define DEV_ENTRY_MODE_SHIFT 0x09
187 
188 #define MAX_DEV_TABLE_ENTRIES 0xffff
189 
190 /* constants to configure the command buffer */
191 #define CMD_BUFFER_SIZE 8192
192 #define CMD_BUFFER_UNINITIALIZED 1
193 #define CMD_BUFFER_ENTRIES 512
194 #define MMIO_CMD_SIZE_SHIFT 56
195 #define MMIO_CMD_SIZE_512 (0x9ULL << MMIO_CMD_SIZE_SHIFT)
196 
197 /* constants for event buffer handling */
198 #define EVT_BUFFER_SIZE 8192 /* 512 entries */
199 #define EVT_LEN_MASK (0x9ULL << 56)
200 
201 /* Constants for PPR Log handling */
202 #define PPR_LOG_ENTRIES 512
203 #define PPR_LOG_SIZE_SHIFT 56
204 #define PPR_LOG_SIZE_512 (0x9ULL << PPR_LOG_SIZE_SHIFT)
205 #define PPR_ENTRY_SIZE 16
206 #define PPR_LOG_SIZE (PPR_ENTRY_SIZE * PPR_LOG_ENTRIES)
207 
208 #define PPR_REQ_TYPE(x) (((x) >> 60) & 0xfULL)
209 #define PPR_FLAGS(x) (((x) >> 48) & 0xfffULL)
210 #define PPR_DEVID(x) ((x) & 0xffffULL)
211 #define PPR_TAG(x) (((x) >> 32) & 0x3ffULL)
212 #define PPR_PASID1(x) (((x) >> 16) & 0xffffULL)
213 #define PPR_PASID2(x) (((x) >> 42) & 0xfULL)
214 #define PPR_PASID(x) ((PPR_PASID2(x) << 16) | PPR_PASID1(x))
215 
216 #define PPR_REQ_FAULT 0x01
217 
218 #define PAGE_MODE_NONE 0x00
219 #define PAGE_MODE_1_LEVEL 0x01
220 #define PAGE_MODE_2_LEVEL 0x02
221 #define PAGE_MODE_3_LEVEL 0x03
222 #define PAGE_MODE_4_LEVEL 0x04
223 #define PAGE_MODE_5_LEVEL 0x05
224 #define PAGE_MODE_6_LEVEL 0x06
225 
226 #define PM_LEVEL_SHIFT(x) (12 + ((x) * 9))
227 #define PM_LEVEL_SIZE(x) (((x) < 6) ? \
228  ((1ULL << PM_LEVEL_SHIFT((x))) - 1): \
229  (0xffffffffffffffffULL))
230 #define PM_LEVEL_INDEX(x, a) (((a) >> PM_LEVEL_SHIFT((x))) & 0x1ffULL)
231 #define PM_LEVEL_ENC(x) (((x) << 9) & 0xe00ULL)
232 #define PM_LEVEL_PDE(x, a) ((a) | PM_LEVEL_ENC((x)) | \
233  IOMMU_PTE_P | IOMMU_PTE_IR | IOMMU_PTE_IW)
234 #define PM_PTE_LEVEL(pte) (((pte) >> 9) & 0x7ULL)
235 
236 #define PM_MAP_4k 0
237 #define PM_ADDR_MASK 0x000ffffffffff000ULL
238 #define PM_MAP_MASK(lvl) (PM_ADDR_MASK & \
239  (~((1ULL << (12 + ((lvl) * 9))) - 1)))
240 #define PM_ALIGNED(lvl, addr) ((PM_MAP_MASK(lvl) & (addr)) == (addr))
241 
242 /*
243  * Returns the page table level to use for a given page size
244  * Pagesize is expected to be a power-of-two
245  */
246 #define PAGE_SIZE_LEVEL(pagesize) \
247  ((__ffs(pagesize) - 12) / 9)
248 /*
249  * Returns the number of ptes to use for a given page size
250  * Pagesize is expected to be a power-of-two
251  */
252 #define PAGE_SIZE_PTE_COUNT(pagesize) \
253  (1ULL << ((__ffs(pagesize) - 12) % 9))
254 
255 /*
256  * Aligns a given io-virtual address to a given page size
257  * Pagesize is expected to be a power-of-two
258  */
259 #define PAGE_SIZE_ALIGN(address, pagesize) \
260  ((address) & ~((pagesize) - 1))
261 /*
262  * Creates an IOMMU PTE for an address and a given pagesize
263  * The PTE has no permission bits set
264  * Pagesize is expected to be a power-of-two larger than 4096
265  */
266 #define PAGE_SIZE_PTE(address, pagesize) \
267  (((address) | ((pagesize) - 1)) & \
268  (~(pagesize >> 1)) & PM_ADDR_MASK)
269 
270 /*
271  * Takes a PTE value with mode=0x07 and returns the page size it maps
272  */
273 #define PTE_PAGE_SIZE(pte) \
274  (1ULL << (1 + ffz(((pte) | 0xfffULL))))
275 
276 #define IOMMU_PTE_P (1ULL << 0)
277 #define IOMMU_PTE_TV (1ULL << 1)
278 #define IOMMU_PTE_U (1ULL << 59)
279 #define IOMMU_PTE_FC (1ULL << 60)
280 #define IOMMU_PTE_IR (1ULL << 61)
281 #define IOMMU_PTE_IW (1ULL << 62)
282 
283 #define DTE_FLAG_IOTLB (0x01UL << 32)
284 #define DTE_FLAG_GV (0x01ULL << 55)
285 #define DTE_GLX_SHIFT (56)
286 #define DTE_GLX_MASK (3)
287 
288 #define DTE_GCR3_VAL_A(x) (((x) >> 12) & 0x00007ULL)
289 #define DTE_GCR3_VAL_B(x) (((x) >> 15) & 0x0ffffULL)
290 #define DTE_GCR3_VAL_C(x) (((x) >> 31) & 0xfffffULL)
291 
292 #define DTE_GCR3_INDEX_A 0
293 #define DTE_GCR3_INDEX_B 1
294 #define DTE_GCR3_INDEX_C 1
295 
296 #define DTE_GCR3_SHIFT_A 58
297 #define DTE_GCR3_SHIFT_B 16
298 #define DTE_GCR3_SHIFT_C 43
299 
300 #define GCR3_VALID 0x01ULL
301 
302 #define IOMMU_PAGE_MASK (((1ULL << 52) - 1) & ~0xfffULL)
303 #define IOMMU_PTE_PRESENT(pte) ((pte) & IOMMU_PTE_P)
304 #define IOMMU_PTE_PAGE(pte) (phys_to_virt((pte) & IOMMU_PAGE_MASK))
305 #define IOMMU_PTE_MODE(pte) (((pte) >> 9) & 0x07)
306 
307 #define IOMMU_PROT_MASK 0x03
308 #define IOMMU_PROT_IR 0x01
309 #define IOMMU_PROT_IW 0x02
310 
311 /* IOMMU capabilities */
312 #define IOMMU_CAP_IOTLB 24
313 #define IOMMU_CAP_NPCACHE 26
314 #define IOMMU_CAP_EFR 27
315 
316 #define MAX_DOMAIN_ID 65536
317 
318 /* FIXME: move this macro to <linux/pci.h> */
319 #define PCI_BUS(x) (((x) >> 8) & 0xff)
320 
321 /* Protection domain flags */
322 #define PD_DMA_OPS_MASK (1UL << 0) /* domain used for dma_ops */
323 #define PD_DEFAULT_MASK (1UL << 1) /* domain is a default dma_ops
324  domain for an IOMMU */
325 #define PD_PASSTHROUGH_MASK (1UL << 2) /* domain has no page
326  translation */
327 #define PD_IOMMUV2_MASK (1UL << 3) /* domain has gcr3 table */
329 extern bool amd_iommu_dump;
330 #define DUMP_printk(format, arg...) \
331  do { \
332  if (amd_iommu_dump) \
333  printk(KERN_INFO "AMD-Vi: " format, ## arg); \
334  } while(0);
335 
336 /* global flag if IOMMUs cache non-present entries */
337 extern bool amd_iommu_np_cache;
338 /* Only true if all IOMMUs support device IOTLBs */
341 #define MAX_IRQS_PER_TABLE 256
342 #define IRQ_TABLE_ALIGNMENT 128
346  unsigned min_index;
347  u32 *table;
348 };
349 
350 extern struct irq_remap_table **irq_lookup_table;
351 
352 /* Interrupt remapping feature used? */
353 extern bool amd_iommu_irq_remap;
354 
355 /* kmem_cache to get tables with 128 byte alignement */
356 extern struct kmem_cache *amd_iommu_irq_cache;
357 
358 /*
359  * Make iterating over all IOMMUs easier
360  */
361 #define for_each_iommu(iommu) \
362  list_for_each_entry((iommu), &amd_iommu_list, list)
363 #define for_each_iommu_safe(iommu, next) \
364  list_for_each_entry_safe((iommu), (next), &amd_iommu_list, list)
366 #define APERTURE_RANGE_SHIFT 27 /* 128 MB */
367 #define APERTURE_RANGE_SIZE (1ULL << APERTURE_RANGE_SHIFT)
368 #define APERTURE_RANGE_PAGES (APERTURE_RANGE_SIZE >> PAGE_SHIFT)
369 #define APERTURE_MAX_RANGES 32 /* allows 4GB of DMA address space */
370 #define APERTURE_RANGE_INDEX(a) ((a) >> APERTURE_RANGE_SHIFT)
371 #define APERTURE_PAGE_INDEX(a) (((a) >> 21) & 0x3fULL)
372 
373 
374 /*
375  * This struct is used to pass information about
376  * incoming PPR faults around.
377  */
379  u64 address; /* IO virtual address of the fault*/
380  u32 pasid; /* Address space identifier */
381  u16 device_id; /* Originating PCI device id */
382  u16 tag; /* PPR tag */
383  u16 flags; /* Fault flags */
384 
385 };
387 #define PPR_FAULT_EXEC (1 << 1)
388 #define PPR_FAULT_READ (1 << 2)
389 #define PPR_FAULT_WRITE (1 << 5)
390 #define PPR_FAULT_USER (1 << 6)
391 #define PPR_FAULT_RSVD (1 << 7)
392 #define PPR_FAULT_GN (1 << 8)
393 
394 struct iommu_domain;
395 
396 /*
397  * This structure contains generic data for IOMMU protection domains
398  * independent of their use.
399  */
401  struct list_head list; /* for list of all protection domains */
402  struct list_head dev_list; /* List of all devices in this domain */
403  spinlock_t lock; /* mostly used to lock the page table*/
404  struct mutex api_lock; /* protect page tables in the iommu-api path */
405  u16 id; /* the domain id written to the device table */
406  int mode; /* paging mode (0-6 levels) */
407  u64 *pt_root; /* page table root pointer */
408  int glx; /* Number of levels for GCR3 table */
409  u64 *gcr3_tbl; /* Guest CR3 table */
410  unsigned long flags; /* flags to find out type of domain */
411  bool updated; /* complete domain flush required */
412  unsigned dev_cnt; /* devices assigned to this domain */
413  unsigned dev_iommu[MAX_IOMMUS]; /* per-IOMMU reference count */
414  void *priv; /* private data */
415  struct iommu_domain *iommu_domain; /* Pointer to generic
416  domain structure */
417 
418 };
419 
420 /*
421  * This struct contains device specific data for the IOMMU
422  */
424  struct list_head list; /* For domain->dev_list */
425  struct list_head dev_data_list; /* For global dev_data_list */
426  struct iommu_dev_data *alias_data;/* The alias dev_data */
427  struct protection_domain *domain; /* Domain the device is bound to */
428  atomic_t bind; /* Domain attach reference count */
429  u16 devid; /* PCI Device ID */
430  bool iommu_v2; /* Device can make use of IOMMUv2 */
431  bool passthrough; /* Default for device is pt_domain */
432  struct {
433  bool enabled;
434  int qdep;
435  } ats; /* ATS state */
436  bool pri_tlp; /* PASID TLB required for
437  PPR completions */
438  u32 errata; /* Bitmap for errata to apply */
439 };
440 
441 /*
442  * For dynamic growth the aperture size is split into ranges of 128MB of
443  * DMA address space each. This struct represents one such range.
444  */
445 struct aperture_range {
447  /* address allocation bitmap */
448  unsigned long *bitmap;
449 
450  /*
451  * Array of PTE pages for the aperture. In this array we save all the
452  * leaf pages of the domain page table used for the aperture. This way
453  * we don't need to walk the page table to find a specific PTE. We can
454  * just calculate its address in constant time.
455  */
457 
458  unsigned long offset;
459 };
460 
461 /*
462  * Data container for a dma_ops specific protection domain
463  */
464 struct dma_ops_domain {
465  struct list_head list;
467  /* generic protection domain information */
468  struct protection_domain domain;
470  /* size of the aperture for the mappings */
471  unsigned long aperture_size;
473  /* address we start to search for free addresses */
474  unsigned long next_address;
476  /* address space relevant data */
479  /* This will be set to true when TLB needs to be flushed */
480  bool need_flush;
481 
482  /*
483  * if this is a preallocated domain, keep the device for which it was
484  * preallocated in this variable
485  */
486  u16 target_dev;
487 };
488 
489 /*
490  * Structure where we save information about one hardware AMD IOMMU in the
491  * system.
492  */
493 struct amd_iommu {
494  struct list_head list;
496  /* Index within the IOMMU array */
497  int index;
499  /* locks the accesses to the hardware */
502  /* Pointer to PCI device of this IOMMU */
503  struct pci_dev *dev;
505  /* Cache pdev to root device for resume quirks */
506  struct pci_dev *root_pdev;
508  /* physical address of MMIO space */
510  /* virtual address of MMIO space */
513  /* capabilities of that IOMMU read from ACPI */
514  u32 cap;
516  /* flags read from acpi table */
517  u8 acpi_flags;
519  /* Extended features */
520  u64 features;
522  /* IOMMUv2 */
523  bool is_iommu_v2;
525  /* PCI device id of the IOMMU device */
526  u16 devid;
527 
528  /*
529  * Capability pointer. There could be more than one IOMMU per PCI
530  * device function if there are more than one AMD IOMMU capability
531  * pointers.
532  */
533  u16 cap_ptr;
535  /* pci domain of this IOMMU */
536  u16 pci_seg;
538  /* first device this IOMMU handles. read from PCI */
540  /* last device this IOMMU handles. read from PCI */
543  /* start of exclusion range of that IOMMU */
545  /* length of exclusion range of that IOMMU */
548  /* command buffer virtual address */
550  /* size of command buffer */
553  /* size of event buffer */
555  /* event buffer virtual address */
556  u8 *evt_buf;
558  /* Base of the PPR log, if present */
559  u8 *ppr_log;
561  /* true if interrupts for this IOMMU are already enabled */
562  bool int_enabled;
564  /* if one, we need to send a completion wait command */
565  bool need_sync;
567  /* default dma_ops domain for that IOMMU */
568  struct dma_ops_domain *default_dom;
569 
570  /*
571  * We can't rely on the BIOS to restore all values on reinit, so we
572  * need to stash them
573  */
575  /* The iommu BAR */
578 
579  /*
580  * Each iommu has 6 l1s, each of which is documented as having 0x12
581  * registers
582  */
583  u32 stored_l1[6][0x12];
585  /* The l2 indirect registers */
586  u32 stored_l2[0x83];
587 };
589 struct devid_map {
590  struct list_head list;
591  u8 id;
592  u16 devid;
593 };
594 
595 /* Map HPET and IOAPIC ids to the devid used by the IOMMU */
596 extern struct list_head ioapic_map;
597 extern struct list_head hpet_map;
598 
599 /*
600  * List with all IOMMUs in the system. This list is not locked because it is
601  * only written and read at driver initialization or suspend time
602  */
603 extern struct list_head amd_iommu_list;
604 
605 /*
606  * Array with pointers to each IOMMU struct
607  * The indices are referenced in the protection domains
608  */
609 extern struct amd_iommu *amd_iommus[MAX_IOMMUS];
610 
611 /* Number of IOMMUs present in the system */
612 extern int amd_iommus_present;
613 
614 /*
615  * Declarations for the global list of all protection domains
616  */
618 extern struct list_head amd_iommu_pd_list;
619 
620 /*
621  * Structure defining one entry in the device table
622  */
623 struct dev_table_entry {
624  u64 data[4];
625 };
626 
627 /*
628  * One entry for unity mappings parsed out of the ACPI table.
629  */
630 struct unity_map_entry {
631  struct list_head list;
633  /* starting device id this entry is used for (including) */
635  /* end device id this entry is used for (including) */
636  u16 devid_end;
638  /* start address to unity map (including) */
640  /* end address to unity map (including) */
643  /* required protection */
644  int prot;
645 };
646 
647 /*
648  * List of all unity mappings. It is not locked because as runtime it is only
649  * read. It is created at ACPI table parsing time.
650  */
651 extern struct list_head amd_iommu_unity_map;
652 
653 /*
654  * Data structures for device handling
655  */
656 
657 /*
658  * Device table used by hardware. Read and write accesses by software are
659  * locked with the amd_iommu_pd_table lock.
660  */
661 extern struct dev_table_entry *amd_iommu_dev_table;
662 
663 /*
664  * Alias table to find requestor ids to device ids. Not locked because only
665  * read on runtime.
666  */
667 extern u16 *amd_iommu_alias_table;
668 
669 /*
670  * Reverse lookup table to find the IOMMU which translates a specific device.
671  */
672 extern struct amd_iommu **amd_iommu_rlookup_table;
673 
674 /* size of the dma_ops aperture as power of 2 */
675 extern unsigned amd_iommu_aperture_order;
676 
677 /* largest PCI device id we expect translation requests for */
678 extern u16 amd_iommu_last_bdf;
679 
680 /* allocation bitmap for domain ids */
681 extern unsigned long *amd_iommu_pd_alloc_bitmap;
682 
683 /*
684  * If true, the addresses will be flushed on unmap time, not when
685  * they are reused
686  */
688 
689 /* Smallest number of PASIDs supported by any IOMMU in the system */
691 
692 extern bool amd_iommu_v2_present;
693 
694 extern bool amd_iommu_force_isolation;
695 
696 /* Max levels of glxval supported */
697 extern int amd_iommu_max_glx_val;
698 
699 /*
700  * This function flushes all internal caches of
701  * the IOMMU used by this driver.
702  */
703 extern void iommu_flush_all_caches(struct amd_iommu *iommu);
704 
705 /* takes bus and device/function and returns the device id
706  * FIXME: should that be in generic PCI code? */
707 static inline u16 calc_devid(u8 bus, u8 devfn)
708 {
709  return (((u16)bus) << 8) | devfn;
710 }
711 
712 static inline int get_ioapic_devid(int id)
713 {
714  struct devid_map *entry;
715 
716  list_for_each_entry(entry, &ioapic_map, list) {
717  if (entry->id == id)
718  return entry->devid;
719  }
720 
721  return -EINVAL;
722 }
723 
724 static inline int get_hpet_devid(int id)
725 {
726  struct devid_map *entry;
727 
728  list_for_each_entry(entry, &hpet_map, list) {
729  if (entry->id == id)
730  return entry->devid;
731  }
732 
733  return -EINVAL;
734 }
735 
736 #ifdef CONFIG_AMD_IOMMU_STATS
737 
738 struct __iommu_counter {
739  char *name;
740  struct dentry *dent;
741  u64 value;
742 };
743 
744 #define DECLARE_STATS_COUNTER(nm) \
745  static struct __iommu_counter nm = { \
746  .name = #nm, \
747  }
748 
749 #define INC_STATS_COUNTER(name) name.value += 1
750 #define ADD_STATS_COUNTER(name, x) name.value += (x)
751 #define SUB_STATS_COUNTER(name, x) name.value -= (x)
752 
753 #else /* CONFIG_AMD_IOMMU_STATS */
755 #define DECLARE_STATS_COUNTER(name)
756 #define INC_STATS_COUNTER(name)
757 #define ADD_STATS_COUNTER(name, x)
758 #define SUB_STATS_COUNTER(name, x)
759 
760 #endif /* CONFIG_AMD_IOMMU_STATS */
761 
762 #endif /* _ASM_X86_AMD_IOMMU_TYPES_H */