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Linux Kernel
3.7.1
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All Data Structures Namespaces Files Functions Variables Typedefs Enumerations Enumerator Macros Groups Pages
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Linux Kernel
3.7.1
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#include <linux/types.h>#include <linux/mutex.h>#include <linux/list.h>#include <linux/spinlock.h>Go to the source code of this file.
Data Structures | |
| struct | irq_remap_table |
| struct | amd_iommu_fault |
| struct | protection_domain |
| struct | iommu_dev_data |
| struct | aperture_range |
| struct | dma_ops_domain |
| struct | amd_iommu |
| struct | devid_map |
| struct | dev_table_entry |
| struct | unity_map_entry |
Macros | |
| #define | MAX_IOMMUS 32 |
| #define | DEV_TABLE_ENTRY_SIZE 32 |
| #define | ALIAS_TABLE_ENTRY_SIZE 2 |
| #define | RLOOKUP_TABLE_ENTRY_SIZE (sizeof(void *)) |
| #define | MMIO_REGION_LENGTH 0x4000 |
| #define | MMIO_CAP_HDR_OFFSET 0x00 |
| #define | MMIO_RANGE_OFFSET 0x0c |
| #define | MMIO_MISC_OFFSET 0x10 |
| #define | MMIO_RANGE_LD_MASK 0xff000000 |
| #define | MMIO_RANGE_FD_MASK 0x00ff0000 |
| #define | MMIO_RANGE_BUS_MASK 0x0000ff00 |
| #define | MMIO_RANGE_LD_SHIFT 24 |
| #define | MMIO_RANGE_FD_SHIFT 16 |
| #define | MMIO_RANGE_BUS_SHIFT 8 |
| #define | MMIO_GET_LD(x) (((x) & MMIO_RANGE_LD_MASK) >> MMIO_RANGE_LD_SHIFT) |
| #define | MMIO_GET_FD(x) (((x) & MMIO_RANGE_FD_MASK) >> MMIO_RANGE_FD_SHIFT) |
| #define | MMIO_GET_BUS(x) (((x) & MMIO_RANGE_BUS_MASK) >> MMIO_RANGE_BUS_SHIFT) |
| #define | MMIO_MSI_NUM(x) ((x) & 0x1f) |
| #define | MMIO_EXCL_ENABLE_MASK 0x01ULL |
| #define | MMIO_EXCL_ALLOW_MASK 0x02ULL |
| #define | MMIO_DEV_TABLE_OFFSET 0x0000 |
| #define | MMIO_CMD_BUF_OFFSET 0x0008 |
| #define | MMIO_EVT_BUF_OFFSET 0x0010 |
| #define | MMIO_CONTROL_OFFSET 0x0018 |
| #define | MMIO_EXCL_BASE_OFFSET 0x0020 |
| #define | MMIO_EXCL_LIMIT_OFFSET 0x0028 |
| #define | MMIO_EXT_FEATURES 0x0030 |
| #define | MMIO_PPR_LOG_OFFSET 0x0038 |
| #define | MMIO_CMD_HEAD_OFFSET 0x2000 |
| #define | MMIO_CMD_TAIL_OFFSET 0x2008 |
| #define | MMIO_EVT_HEAD_OFFSET 0x2010 |
| #define | MMIO_EVT_TAIL_OFFSET 0x2018 |
| #define | MMIO_STATUS_OFFSET 0x2020 |
| #define | MMIO_PPR_HEAD_OFFSET 0x2030 |
| #define | MMIO_PPR_TAIL_OFFSET 0x2038 |
| #define | FEATURE_PREFETCH (1ULL<<0) |
| #define | FEATURE_PPR (1ULL<<1) |
| #define | FEATURE_X2APIC (1ULL<<2) |
| #define | FEATURE_NX (1ULL<<3) |
| #define | FEATURE_GT (1ULL<<4) |
| #define | FEATURE_IA (1ULL<<6) |
| #define | FEATURE_GA (1ULL<<7) |
| #define | FEATURE_HE (1ULL<<8) |
| #define | FEATURE_PC (1ULL<<9) |
| #define | FEATURE_PASID_SHIFT 32 |
| #define | FEATURE_PASID_MASK (0x1fULL << FEATURE_PASID_SHIFT) |
| #define | FEATURE_GLXVAL_SHIFT 14 |
| #define | FEATURE_GLXVAL_MASK (0x03ULL << FEATURE_GLXVAL_SHIFT) |
| #define | PASID_MASK 0x000fffff |
| #define | MMIO_STATUS_COM_WAIT_INT_MASK (1 << 2) |
| #define | MMIO_STATUS_PPR_INT_MASK (1 << 6) |
| #define | EVENT_ENTRY_SIZE 0x10 |
| #define | EVENT_TYPE_SHIFT 28 |
| #define | EVENT_TYPE_MASK 0xf |
| #define | EVENT_TYPE_ILL_DEV 0x1 |
| #define | EVENT_TYPE_IO_FAULT 0x2 |
| #define | EVENT_TYPE_DEV_TAB_ERR 0x3 |
| #define | EVENT_TYPE_PAGE_TAB_ERR 0x4 |
| #define | EVENT_TYPE_ILL_CMD 0x5 |
| #define | EVENT_TYPE_CMD_HARD_ERR 0x6 |
| #define | EVENT_TYPE_IOTLB_INV_TO 0x7 |
| #define | EVENT_TYPE_INV_DEV_REQ 0x8 |
| #define | EVENT_DEVID_MASK 0xffff |
| #define | EVENT_DEVID_SHIFT 0 |
| #define | EVENT_DOMID_MASK 0xffff |
| #define | EVENT_DOMID_SHIFT 0 |
| #define | EVENT_FLAGS_MASK 0xfff |
| #define | EVENT_FLAGS_SHIFT 0x10 |
| #define | CONTROL_IOMMU_EN 0x00ULL |
| #define | CONTROL_HT_TUN_EN 0x01ULL |
| #define | CONTROL_EVT_LOG_EN 0x02ULL |
| #define | CONTROL_EVT_INT_EN 0x03ULL |
| #define | CONTROL_COMWAIT_EN 0x04ULL |
| #define | CONTROL_INV_TIMEOUT 0x05ULL |
| #define | CONTROL_PASSPW_EN 0x08ULL |
| #define | CONTROL_RESPASSPW_EN 0x09ULL |
| #define | CONTROL_COHERENT_EN 0x0aULL |
| #define | CONTROL_ISOC_EN 0x0bULL |
| #define | CONTROL_CMDBUF_EN 0x0cULL |
| #define | CONTROL_PPFLOG_EN 0x0dULL |
| #define | CONTROL_PPFINT_EN 0x0eULL |
| #define | CONTROL_PPR_EN 0x0fULL |
| #define | CONTROL_GT_EN 0x10ULL |
| #define | CTRL_INV_TO_MASK (7 << CONTROL_INV_TIMEOUT) |
| #define | CTRL_INV_TO_NONE 0 |
| #define | CTRL_INV_TO_1MS 1 |
| #define | CTRL_INV_TO_10MS 2 |
| #define | CTRL_INV_TO_100MS 3 |
| #define | CTRL_INV_TO_1S 4 |
| #define | CTRL_INV_TO_10S 5 |
| #define | CTRL_INV_TO_100S 6 |
| #define | CMD_COMPL_WAIT 0x01 |
| #define | CMD_INV_DEV_ENTRY 0x02 |
| #define | CMD_INV_IOMMU_PAGES 0x03 |
| #define | CMD_INV_IOTLB_PAGES 0x04 |
| #define | CMD_INV_IRT 0x05 |
| #define | CMD_COMPLETE_PPR 0x07 |
| #define | CMD_INV_ALL 0x08 |
| #define | CMD_COMPL_WAIT_STORE_MASK 0x01 |
| #define | CMD_COMPL_WAIT_INT_MASK 0x02 |
| #define | CMD_INV_IOMMU_PAGES_SIZE_MASK 0x01 |
| #define | CMD_INV_IOMMU_PAGES_PDE_MASK 0x02 |
| #define | CMD_INV_IOMMU_PAGES_GN_MASK 0x04 |
| #define | PPR_STATUS_MASK 0xf |
| #define | PPR_STATUS_SHIFT 12 |
| #define | CMD_INV_IOMMU_ALL_PAGES_ADDRESS 0x7fffffffffffffffULL |
| #define | DEV_ENTRY_VALID 0x00 |
| #define | DEV_ENTRY_TRANSLATION 0x01 |
| #define | DEV_ENTRY_IR 0x3d |
| #define | DEV_ENTRY_IW 0x3e |
| #define | DEV_ENTRY_NO_PAGE_FAULT 0x62 |
| #define | DEV_ENTRY_EX 0x67 |
| #define | DEV_ENTRY_SYSMGT1 0x68 |
| #define | DEV_ENTRY_SYSMGT2 0x69 |
| #define | DEV_ENTRY_IRQ_TBL_EN 0x80 |
| #define | DEV_ENTRY_INIT_PASS 0xb8 |
| #define | DEV_ENTRY_EINT_PASS 0xb9 |
| #define | DEV_ENTRY_NMI_PASS 0xba |
| #define | DEV_ENTRY_LINT0_PASS 0xbe |
| #define | DEV_ENTRY_LINT1_PASS 0xbf |
| #define | DEV_ENTRY_MODE_MASK 0x07 |
| #define | DEV_ENTRY_MODE_SHIFT 0x09 |
| #define | MAX_DEV_TABLE_ENTRIES 0xffff |
| #define | CMD_BUFFER_SIZE 8192 |
| #define | CMD_BUFFER_UNINITIALIZED 1 |
| #define | CMD_BUFFER_ENTRIES 512 |
| #define | MMIO_CMD_SIZE_SHIFT 56 |
| #define | MMIO_CMD_SIZE_512 (0x9ULL << MMIO_CMD_SIZE_SHIFT) |
| #define | EVT_BUFFER_SIZE 8192 /* 512 entries */ |
| #define | EVT_LEN_MASK (0x9ULL << 56) |
| #define | PPR_LOG_ENTRIES 512 |
| #define | PPR_LOG_SIZE_SHIFT 56 |
| #define | PPR_LOG_SIZE_512 (0x9ULL << PPR_LOG_SIZE_SHIFT) |
| #define | PPR_ENTRY_SIZE 16 |
| #define | PPR_LOG_SIZE (PPR_ENTRY_SIZE * PPR_LOG_ENTRIES) |
| #define | PPR_REQ_TYPE(x) (((x) >> 60) & 0xfULL) |
| #define | PPR_FLAGS(x) (((x) >> 48) & 0xfffULL) |
| #define | PPR_DEVID(x) ((x) & 0xffffULL) |
| #define | PPR_TAG(x) (((x) >> 32) & 0x3ffULL) |
| #define | PPR_PASID1(x) (((x) >> 16) & 0xffffULL) |
| #define | PPR_PASID2(x) (((x) >> 42) & 0xfULL) |
| #define | PPR_PASID(x) ((PPR_PASID2(x) << 16) | PPR_PASID1(x)) |
| #define | PPR_REQ_FAULT 0x01 |
| #define | PAGE_MODE_NONE 0x00 |
| #define | PAGE_MODE_1_LEVEL 0x01 |
| #define | PAGE_MODE_2_LEVEL 0x02 |
| #define | PAGE_MODE_3_LEVEL 0x03 |
| #define | PAGE_MODE_4_LEVEL 0x04 |
| #define | PAGE_MODE_5_LEVEL 0x05 |
| #define | PAGE_MODE_6_LEVEL 0x06 |
| #define | PM_LEVEL_SHIFT(x) (12 + ((x) * 9)) |
| #define | PM_LEVEL_SIZE(x) |
| #define | PM_LEVEL_INDEX(x, a) (((a) >> PM_LEVEL_SHIFT((x))) & 0x1ffULL) |
| #define | PM_LEVEL_ENC(x) (((x) << 9) & 0xe00ULL) |
| #define | PM_LEVEL_PDE(x, a) |
| #define | PM_PTE_LEVEL(pte) (((pte) >> 9) & 0x7ULL) |
| #define | PM_MAP_4k 0 |
| #define | PM_ADDR_MASK 0x000ffffffffff000ULL |
| #define | PM_MAP_MASK(lvl) |
| #define | PM_ALIGNED(lvl, addr) ((PM_MAP_MASK(lvl) & (addr)) == (addr)) |
| #define | PAGE_SIZE_LEVEL(pagesize) ((__ffs(pagesize) - 12) / 9) |
| #define | PAGE_SIZE_PTE_COUNT(pagesize) (1ULL << ((__ffs(pagesize) - 12) % 9)) |
| #define | PAGE_SIZE_ALIGN(address, pagesize) ((address) & ~((pagesize) - 1)) |
| #define | PAGE_SIZE_PTE(address, pagesize) |
| #define | PTE_PAGE_SIZE(pte) (1ULL << (1 + ffz(((pte) | 0xfffULL)))) |
| #define | IOMMU_PTE_P (1ULL << 0) |
| #define | IOMMU_PTE_TV (1ULL << 1) |
| #define | IOMMU_PTE_U (1ULL << 59) |
| #define | IOMMU_PTE_FC (1ULL << 60) |
| #define | IOMMU_PTE_IR (1ULL << 61) |
| #define | IOMMU_PTE_IW (1ULL << 62) |
| #define | DTE_FLAG_IOTLB (0x01UL << 32) |
| #define | DTE_FLAG_GV (0x01ULL << 55) |
| #define | DTE_GLX_SHIFT (56) |
| #define | DTE_GLX_MASK (3) |
| #define | DTE_GCR3_VAL_A(x) (((x) >> 12) & 0x00007ULL) |
| #define | DTE_GCR3_VAL_B(x) (((x) >> 15) & 0x0ffffULL) |
| #define | DTE_GCR3_VAL_C(x) (((x) >> 31) & 0xfffffULL) |
| #define | DTE_GCR3_INDEX_A 0 |
| #define | DTE_GCR3_INDEX_B 1 |
| #define | DTE_GCR3_INDEX_C 1 |
| #define | DTE_GCR3_SHIFT_A 58 |
| #define | DTE_GCR3_SHIFT_B 16 |
| #define | DTE_GCR3_SHIFT_C 43 |
| #define | GCR3_VALID 0x01ULL |
| #define | IOMMU_PAGE_MASK (((1ULL << 52) - 1) & ~0xfffULL) |
| #define | IOMMU_PTE_PRESENT(pte) ((pte) & IOMMU_PTE_P) |
| #define | IOMMU_PTE_PAGE(pte) (phys_to_virt((pte) & IOMMU_PAGE_MASK)) |
| #define | IOMMU_PTE_MODE(pte) (((pte) >> 9) & 0x07) |
| #define | IOMMU_PROT_MASK 0x03 |
| #define | IOMMU_PROT_IR 0x01 |
| #define | IOMMU_PROT_IW 0x02 |
| #define | IOMMU_CAP_IOTLB 24 |
| #define | IOMMU_CAP_NPCACHE 26 |
| #define | IOMMU_CAP_EFR 27 |
| #define | MAX_DOMAIN_ID 65536 |
| #define | PCI_BUS(x) (((x) >> 8) & 0xff) |
| #define | PD_DMA_OPS_MASK (1UL << 0) /* domain used for dma_ops */ |
| #define | PD_DEFAULT_MASK |
| #define | PD_PASSTHROUGH_MASK |
| #define | PD_IOMMUV2_MASK (1UL << 3) /* domain has gcr3 table */ |
| #define | DUMP_printk(format, arg...) |
| #define | MAX_IRQS_PER_TABLE 256 |
| #define | IRQ_TABLE_ALIGNMENT 128 |
| #define | for_each_iommu(iommu) list_for_each_entry((iommu), &amd_iommu_list, list) |
| #define | for_each_iommu_safe(iommu, next) list_for_each_entry_safe((iommu), (next), &amd_iommu_list, list) |
| #define | APERTURE_RANGE_SHIFT 27 /* 128 MB */ |
| #define | APERTURE_RANGE_SIZE (1ULL << APERTURE_RANGE_SHIFT) |
| #define | APERTURE_RANGE_PAGES (APERTURE_RANGE_SIZE >> PAGE_SHIFT) |
| #define | APERTURE_MAX_RANGES 32 /* allows 4GB of DMA address space */ |
| #define | APERTURE_RANGE_INDEX(a) ((a) >> APERTURE_RANGE_SHIFT) |
| #define | APERTURE_PAGE_INDEX(a) (((a) >> 21) & 0x3fULL) |
| #define | PPR_FAULT_EXEC (1 << 1) |
| #define | PPR_FAULT_READ (1 << 2) |
| #define | PPR_FAULT_WRITE (1 << 5) |
| #define | PPR_FAULT_USER (1 << 6) |
| #define | PPR_FAULT_RSVD (1 << 7) |
| #define | PPR_FAULT_GN (1 << 8) |
| #define | DECLARE_STATS_COUNTER(name) |
| #define | INC_STATS_COUNTER(name) |
| #define | ADD_STATS_COUNTER(name, x) |
| #define | SUB_STATS_COUNTER(name, x) |
Functions | |
| void | iommu_flush_all_caches (struct amd_iommu *iommu) |
Definition at line 755 of file amd_iommu_types.h.
| #define ALIAS_TABLE_ENTRY_SIZE 2 |
Definition at line 37 of file amd_iommu_types.h.
| #define APERTURE_MAX_RANGES 32 /* allows 4GB of DMA address space */ |
Definition at line 367 of file amd_iommu_types.h.
Definition at line 369 of file amd_iommu_types.h.
| #define APERTURE_RANGE_INDEX | ( | a | ) | ((a) >> APERTURE_RANGE_SHIFT) |
Definition at line 368 of file amd_iommu_types.h.
| #define APERTURE_RANGE_PAGES (APERTURE_RANGE_SIZE >> PAGE_SHIFT) |
Definition at line 366 of file amd_iommu_types.h.
| #define APERTURE_RANGE_SHIFT 27 /* 128 MB */ |
Definition at line 364 of file amd_iommu_types.h.
| #define APERTURE_RANGE_SIZE (1ULL << APERTURE_RANGE_SHIFT) |
Definition at line 365 of file amd_iommu_types.h.
| #define CMD_BUFFER_ENTRIES 512 |
Definition at line 193 of file amd_iommu_types.h.
| #define CMD_BUFFER_SIZE 8192 |
Definition at line 191 of file amd_iommu_types.h.
| #define CMD_BUFFER_UNINITIALIZED 1 |
Definition at line 192 of file amd_iommu_types.h.
| #define CMD_COMPL_WAIT 0x01 |
Definition at line 151 of file amd_iommu_types.h.
| #define CMD_COMPL_WAIT_INT_MASK 0x02 |
Definition at line 160 of file amd_iommu_types.h.
| #define CMD_COMPL_WAIT_STORE_MASK 0x01 |
Definition at line 159 of file amd_iommu_types.h.
| #define CMD_COMPLETE_PPR 0x07 |
Definition at line 156 of file amd_iommu_types.h.
| #define CMD_INV_ALL 0x08 |
Definition at line 157 of file amd_iommu_types.h.
| #define CMD_INV_DEV_ENTRY 0x02 |
Definition at line 152 of file amd_iommu_types.h.
| #define CMD_INV_IOMMU_ALL_PAGES_ADDRESS 0x7fffffffffffffffULL |
Definition at line 168 of file amd_iommu_types.h.
| #define CMD_INV_IOMMU_PAGES 0x03 |
Definition at line 153 of file amd_iommu_types.h.
| #define CMD_INV_IOMMU_PAGES_GN_MASK 0x04 |
Definition at line 163 of file amd_iommu_types.h.
| #define CMD_INV_IOMMU_PAGES_PDE_MASK 0x02 |
Definition at line 162 of file amd_iommu_types.h.
| #define CMD_INV_IOMMU_PAGES_SIZE_MASK 0x01 |
Definition at line 161 of file amd_iommu_types.h.
| #define CMD_INV_IOTLB_PAGES 0x04 |
Definition at line 154 of file amd_iommu_types.h.
| #define CMD_INV_IRT 0x05 |
Definition at line 155 of file amd_iommu_types.h.
| #define CONTROL_CMDBUF_EN 0x0cULL |
Definition at line 135 of file amd_iommu_types.h.
| #define CONTROL_COHERENT_EN 0x0aULL |
Definition at line 133 of file amd_iommu_types.h.
| #define CONTROL_COMWAIT_EN 0x04ULL |
Definition at line 129 of file amd_iommu_types.h.
| #define CONTROL_EVT_INT_EN 0x03ULL |
Definition at line 128 of file amd_iommu_types.h.
| #define CONTROL_EVT_LOG_EN 0x02ULL |
Definition at line 127 of file amd_iommu_types.h.
| #define CONTROL_GT_EN 0x10ULL |
Definition at line 139 of file amd_iommu_types.h.
| #define CONTROL_HT_TUN_EN 0x01ULL |
Definition at line 126 of file amd_iommu_types.h.
| #define CONTROL_INV_TIMEOUT 0x05ULL |
Definition at line 130 of file amd_iommu_types.h.
| #define CONTROL_IOMMU_EN 0x00ULL |
Definition at line 125 of file amd_iommu_types.h.
| #define CONTROL_ISOC_EN 0x0bULL |
Definition at line 134 of file amd_iommu_types.h.
| #define CONTROL_PASSPW_EN 0x08ULL |
Definition at line 131 of file amd_iommu_types.h.
| #define CONTROL_PPFINT_EN 0x0eULL |
Definition at line 137 of file amd_iommu_types.h.
| #define CONTROL_PPFLOG_EN 0x0dULL |
Definition at line 136 of file amd_iommu_types.h.
| #define CONTROL_PPR_EN 0x0fULL |
Definition at line 138 of file amd_iommu_types.h.
| #define CONTROL_RESPASSPW_EN 0x09ULL |
Definition at line 132 of file amd_iommu_types.h.
| #define CTRL_INV_TO_100MS 3 |
Definition at line 145 of file amd_iommu_types.h.
| #define CTRL_INV_TO_100S 6 |
Definition at line 148 of file amd_iommu_types.h.
| #define CTRL_INV_TO_10MS 2 |
Definition at line 144 of file amd_iommu_types.h.
| #define CTRL_INV_TO_10S 5 |
Definition at line 147 of file amd_iommu_types.h.
| #define CTRL_INV_TO_1MS 1 |
Definition at line 143 of file amd_iommu_types.h.
| #define CTRL_INV_TO_1S 4 |
Definition at line 146 of file amd_iommu_types.h.
| #define CTRL_INV_TO_MASK (7 << CONTROL_INV_TIMEOUT) |
Definition at line 141 of file amd_iommu_types.h.
| #define CTRL_INV_TO_NONE 0 |
Definition at line 142 of file amd_iommu_types.h.
| #define DECLARE_STATS_COUNTER | ( | name | ) |
Definition at line 753 of file amd_iommu_types.h.
| #define DEV_ENTRY_EINT_PASS 0xb9 |
Definition at line 181 of file amd_iommu_types.h.
| #define DEV_ENTRY_EX 0x67 |
Definition at line 176 of file amd_iommu_types.h.
| #define DEV_ENTRY_INIT_PASS 0xb8 |
Definition at line 180 of file amd_iommu_types.h.
| #define DEV_ENTRY_IR 0x3d |
Definition at line 173 of file amd_iommu_types.h.
| #define DEV_ENTRY_IRQ_TBL_EN 0x80 |
Definition at line 179 of file amd_iommu_types.h.
| #define DEV_ENTRY_IW 0x3e |
Definition at line 174 of file amd_iommu_types.h.
| #define DEV_ENTRY_LINT0_PASS 0xbe |
Definition at line 183 of file amd_iommu_types.h.
| #define DEV_ENTRY_LINT1_PASS 0xbf |
Definition at line 184 of file amd_iommu_types.h.
| #define DEV_ENTRY_MODE_MASK 0x07 |
Definition at line 185 of file amd_iommu_types.h.
| #define DEV_ENTRY_MODE_SHIFT 0x09 |
Definition at line 186 of file amd_iommu_types.h.
| #define DEV_ENTRY_NMI_PASS 0xba |
Definition at line 182 of file amd_iommu_types.h.
| #define DEV_ENTRY_NO_PAGE_FAULT 0x62 |
Definition at line 175 of file amd_iommu_types.h.
| #define DEV_ENTRY_SYSMGT1 0x68 |
Definition at line 177 of file amd_iommu_types.h.
| #define DEV_ENTRY_SYSMGT2 0x69 |
Definition at line 178 of file amd_iommu_types.h.
| #define DEV_ENTRY_TRANSLATION 0x01 |
Definition at line 172 of file amd_iommu_types.h.
| #define DEV_ENTRY_VALID 0x00 |
Definition at line 171 of file amd_iommu_types.h.
| #define DEV_TABLE_ENTRY_SIZE 32 |
Definition at line 36 of file amd_iommu_types.h.
| #define DTE_FLAG_GV (0x01ULL << 55) |
Definition at line 284 of file amd_iommu_types.h.
| #define DTE_FLAG_IOTLB (0x01UL << 32) |
Definition at line 283 of file amd_iommu_types.h.
| #define DTE_GCR3_INDEX_A 0 |
Definition at line 292 of file amd_iommu_types.h.
| #define DTE_GCR3_INDEX_B 1 |
Definition at line 293 of file amd_iommu_types.h.
| #define DTE_GCR3_INDEX_C 1 |
Definition at line 294 of file amd_iommu_types.h.
| #define DTE_GCR3_SHIFT_A 58 |
Definition at line 296 of file amd_iommu_types.h.
| #define DTE_GCR3_SHIFT_B 16 |
Definition at line 297 of file amd_iommu_types.h.
| #define DTE_GCR3_SHIFT_C 43 |
Definition at line 298 of file amd_iommu_types.h.
Definition at line 288 of file amd_iommu_types.h.
Definition at line 289 of file amd_iommu_types.h.
Definition at line 290 of file amd_iommu_types.h.
| #define DTE_GLX_MASK (3) |
Definition at line 286 of file amd_iommu_types.h.
| #define DTE_GLX_SHIFT (56) |
Definition at line 285 of file amd_iommu_types.h.
| #define DUMP_printk | ( | format, | |
| arg... | |||
| ) |
Definition at line 328 of file amd_iommu_types.h.
| #define EVENT_DEVID_MASK 0xffff |
Definition at line 117 of file amd_iommu_types.h.
| #define EVENT_DEVID_SHIFT 0 |
Definition at line 118 of file amd_iommu_types.h.
| #define EVENT_DOMID_MASK 0xffff |
Definition at line 119 of file amd_iommu_types.h.
| #define EVENT_DOMID_SHIFT 0 |
Definition at line 120 of file amd_iommu_types.h.
| #define EVENT_ENTRY_SIZE 0x10 |
Definition at line 106 of file amd_iommu_types.h.
| #define EVENT_FLAGS_MASK 0xfff |
Definition at line 121 of file amd_iommu_types.h.
| #define EVENT_FLAGS_SHIFT 0x10 |
Definition at line 122 of file amd_iommu_types.h.
| #define EVENT_TYPE_CMD_HARD_ERR 0x6 |
Definition at line 114 of file amd_iommu_types.h.
| #define EVENT_TYPE_DEV_TAB_ERR 0x3 |
Definition at line 111 of file amd_iommu_types.h.
| #define EVENT_TYPE_ILL_CMD 0x5 |
Definition at line 113 of file amd_iommu_types.h.
| #define EVENT_TYPE_ILL_DEV 0x1 |
Definition at line 109 of file amd_iommu_types.h.
| #define EVENT_TYPE_INV_DEV_REQ 0x8 |
Definition at line 116 of file amd_iommu_types.h.
| #define EVENT_TYPE_IO_FAULT 0x2 |
Definition at line 110 of file amd_iommu_types.h.
| #define EVENT_TYPE_IOTLB_INV_TO 0x7 |
Definition at line 115 of file amd_iommu_types.h.
| #define EVENT_TYPE_MASK 0xf |
Definition at line 108 of file amd_iommu_types.h.
| #define EVENT_TYPE_PAGE_TAB_ERR 0x4 |
Definition at line 112 of file amd_iommu_types.h.
| #define EVENT_TYPE_SHIFT 28 |
Definition at line 107 of file amd_iommu_types.h.
| #define EVT_BUFFER_SIZE 8192 /* 512 entries */ |
Definition at line 198 of file amd_iommu_types.h.
| #define EVT_LEN_MASK (0x9ULL << 56) |
Definition at line 199 of file amd_iommu_types.h.
| #define FEATURE_GA (1ULL<<7) |
Definition at line 89 of file amd_iommu_types.h.
| #define FEATURE_GLXVAL_MASK (0x03ULL << FEATURE_GLXVAL_SHIFT) |
Definition at line 97 of file amd_iommu_types.h.
| #define FEATURE_GLXVAL_SHIFT 14 |
Definition at line 96 of file amd_iommu_types.h.
| #define FEATURE_GT (1ULL<<4) |
Definition at line 87 of file amd_iommu_types.h.
| #define FEATURE_HE (1ULL<<8) |
Definition at line 90 of file amd_iommu_types.h.
| #define FEATURE_IA (1ULL<<6) |
Definition at line 88 of file amd_iommu_types.h.
| #define FEATURE_NX (1ULL<<3) |
Definition at line 86 of file amd_iommu_types.h.
| #define FEATURE_PASID_MASK (0x1fULL << FEATURE_PASID_SHIFT) |
Definition at line 94 of file amd_iommu_types.h.
| #define FEATURE_PASID_SHIFT 32 |
Definition at line 93 of file amd_iommu_types.h.
| #define FEATURE_PC (1ULL<<9) |
Definition at line 91 of file amd_iommu_types.h.
| #define FEATURE_PPR (1ULL<<1) |
Definition at line 84 of file amd_iommu_types.h.
| #define FEATURE_PREFETCH (1ULL<<0) |
Definition at line 83 of file amd_iommu_types.h.
| #define FEATURE_X2APIC (1ULL<<2) |
Definition at line 85 of file amd_iommu_types.h.
| #define for_each_iommu | ( | iommu | ) | list_for_each_entry((iommu), &amd_iommu_list, list) |
Definition at line 359 of file amd_iommu_types.h.
| #define for_each_iommu_safe | ( | iommu, | |
| next | |||
| ) | list_for_each_entry_safe((iommu), (next), &amd_iommu_list, list) |
Definition at line 361 of file amd_iommu_types.h.
| #define GCR3_VALID 0x01ULL |
Definition at line 300 of file amd_iommu_types.h.
| #define INC_STATS_COUNTER | ( | name | ) |
Definition at line 754 of file amd_iommu_types.h.
| #define IOMMU_CAP_EFR 27 |
Definition at line 314 of file amd_iommu_types.h.
| #define IOMMU_CAP_IOTLB 24 |
Definition at line 312 of file amd_iommu_types.h.
| #define IOMMU_CAP_NPCACHE 26 |
Definition at line 313 of file amd_iommu_types.h.
| #define IOMMU_PAGE_MASK (((1ULL << 52) - 1) & ~0xfffULL) |
Definition at line 302 of file amd_iommu_types.h.
| #define IOMMU_PROT_IR 0x01 |
Definition at line 308 of file amd_iommu_types.h.
| #define IOMMU_PROT_IW 0x02 |
Definition at line 309 of file amd_iommu_types.h.
| #define IOMMU_PROT_MASK 0x03 |
Definition at line 307 of file amd_iommu_types.h.
| #define IOMMU_PTE_FC (1ULL << 60) |
Definition at line 279 of file amd_iommu_types.h.
| #define IOMMU_PTE_IR (1ULL << 61) |
Definition at line 280 of file amd_iommu_types.h.
| #define IOMMU_PTE_IW (1ULL << 62) |
Definition at line 281 of file amd_iommu_types.h.
Definition at line 305 of file amd_iommu_types.h.
| #define IOMMU_PTE_P (1ULL << 0) |
Definition at line 276 of file amd_iommu_types.h.
| #define IOMMU_PTE_PAGE | ( | pte | ) | (phys_to_virt((pte) & IOMMU_PAGE_MASK)) |
Definition at line 304 of file amd_iommu_types.h.
| #define IOMMU_PTE_PRESENT | ( | pte | ) | ((pte) & IOMMU_PTE_P) |
Definition at line 303 of file amd_iommu_types.h.
| #define IOMMU_PTE_TV (1ULL << 1) |
Definition at line 277 of file amd_iommu_types.h.
| #define IOMMU_PTE_U (1ULL << 59) |
Definition at line 278 of file amd_iommu_types.h.
| #define IRQ_TABLE_ALIGNMENT 128 |
Definition at line 340 of file amd_iommu_types.h.
| #define MAX_DEV_TABLE_ENTRIES 0xffff |
Definition at line 188 of file amd_iommu_types.h.
| #define MAX_DOMAIN_ID 65536 |
Definition at line 316 of file amd_iommu_types.h.
| #define MAX_IOMMUS 32 |
Definition at line 31 of file amd_iommu_types.h.
| #define MAX_IRQS_PER_TABLE 256 |
Definition at line 339 of file amd_iommu_types.h.
| #define MMIO_CAP_HDR_OFFSET 0x00 |
Definition at line 44 of file amd_iommu_types.h.
| #define MMIO_CMD_BUF_OFFSET 0x0008 |
Definition at line 66 of file amd_iommu_types.h.
| #define MMIO_CMD_HEAD_OFFSET 0x2000 |
Definition at line 73 of file amd_iommu_types.h.
| #define MMIO_CMD_SIZE_512 (0x9ULL << MMIO_CMD_SIZE_SHIFT) |
Definition at line 195 of file amd_iommu_types.h.
| #define MMIO_CMD_SIZE_SHIFT 56 |
Definition at line 194 of file amd_iommu_types.h.
| #define MMIO_CMD_TAIL_OFFSET 0x2008 |
Definition at line 74 of file amd_iommu_types.h.
| #define MMIO_CONTROL_OFFSET 0x0018 |
Definition at line 68 of file amd_iommu_types.h.
| #define MMIO_DEV_TABLE_OFFSET 0x0000 |
Definition at line 65 of file amd_iommu_types.h.
| #define MMIO_EVT_BUF_OFFSET 0x0010 |
Definition at line 67 of file amd_iommu_types.h.
| #define MMIO_EVT_HEAD_OFFSET 0x2010 |
Definition at line 75 of file amd_iommu_types.h.
| #define MMIO_EVT_TAIL_OFFSET 0x2018 |
Definition at line 76 of file amd_iommu_types.h.
| #define MMIO_EXCL_ALLOW_MASK 0x02ULL |
Definition at line 62 of file amd_iommu_types.h.
| #define MMIO_EXCL_BASE_OFFSET 0x0020 |
Definition at line 69 of file amd_iommu_types.h.
| #define MMIO_EXCL_ENABLE_MASK 0x01ULL |
Definition at line 61 of file amd_iommu_types.h.
| #define MMIO_EXCL_LIMIT_OFFSET 0x0028 |
Definition at line 70 of file amd_iommu_types.h.
| #define MMIO_EXT_FEATURES 0x0030 |
Definition at line 71 of file amd_iommu_types.h.
| #define MMIO_GET_BUS | ( | x | ) | (((x) & MMIO_RANGE_BUS_MASK) >> MMIO_RANGE_BUS_SHIFT) |
Definition at line 57 of file amd_iommu_types.h.
| #define MMIO_GET_FD | ( | x | ) | (((x) & MMIO_RANGE_FD_MASK) >> MMIO_RANGE_FD_SHIFT) |
Definition at line 56 of file amd_iommu_types.h.
| #define MMIO_GET_LD | ( | x | ) | (((x) & MMIO_RANGE_LD_MASK) >> MMIO_RANGE_LD_SHIFT) |
Definition at line 55 of file amd_iommu_types.h.
| #define MMIO_MISC_OFFSET 0x10 |
Definition at line 46 of file amd_iommu_types.h.
Definition at line 58 of file amd_iommu_types.h.
| #define MMIO_PPR_HEAD_OFFSET 0x2030 |
Definition at line 78 of file amd_iommu_types.h.
| #define MMIO_PPR_LOG_OFFSET 0x0038 |
Definition at line 72 of file amd_iommu_types.h.
| #define MMIO_PPR_TAIL_OFFSET 0x2038 |
Definition at line 79 of file amd_iommu_types.h.
| #define MMIO_RANGE_BUS_MASK 0x0000ff00 |
Definition at line 51 of file amd_iommu_types.h.
| #define MMIO_RANGE_BUS_SHIFT 8 |
Definition at line 54 of file amd_iommu_types.h.
| #define MMIO_RANGE_FD_MASK 0x00ff0000 |
Definition at line 50 of file amd_iommu_types.h.
| #define MMIO_RANGE_FD_SHIFT 16 |
Definition at line 53 of file amd_iommu_types.h.
| #define MMIO_RANGE_LD_MASK 0xff000000 |
Definition at line 49 of file amd_iommu_types.h.
| #define MMIO_RANGE_LD_SHIFT 24 |
Definition at line 52 of file amd_iommu_types.h.
| #define MMIO_RANGE_OFFSET 0x0c |
Definition at line 45 of file amd_iommu_types.h.
| #define MMIO_REGION_LENGTH 0x4000 |
Definition at line 41 of file amd_iommu_types.h.
| #define MMIO_STATUS_COM_WAIT_INT_MASK (1 << 2) |
Definition at line 102 of file amd_iommu_types.h.
| #define MMIO_STATUS_OFFSET 0x2020 |
Definition at line 77 of file amd_iommu_types.h.
| #define MMIO_STATUS_PPR_INT_MASK (1 << 6) |
Definition at line 103 of file amd_iommu_types.h.
| #define PAGE_MODE_1_LEVEL 0x01 |
Definition at line 219 of file amd_iommu_types.h.
| #define PAGE_MODE_2_LEVEL 0x02 |
Definition at line 220 of file amd_iommu_types.h.
| #define PAGE_MODE_3_LEVEL 0x03 |
Definition at line 221 of file amd_iommu_types.h.
| #define PAGE_MODE_4_LEVEL 0x04 |
Definition at line 222 of file amd_iommu_types.h.
| #define PAGE_MODE_5_LEVEL 0x05 |
Definition at line 223 of file amd_iommu_types.h.
| #define PAGE_MODE_6_LEVEL 0x06 |
Definition at line 224 of file amd_iommu_types.h.
| #define PAGE_MODE_NONE 0x00 |
Definition at line 218 of file amd_iommu_types.h.
Definition at line 259 of file amd_iommu_types.h.
| #define PAGE_SIZE_LEVEL | ( | pagesize | ) | ((__ffs(pagesize) - 12) / 9) |
Definition at line 246 of file amd_iommu_types.h.
| #define PAGE_SIZE_PTE | ( | address, | |
| pagesize | |||
| ) |
Definition at line 266 of file amd_iommu_types.h.
| #define PAGE_SIZE_PTE_COUNT | ( | pagesize | ) | (1ULL << ((__ffs(pagesize) - 12) % 9)) |
Definition at line 252 of file amd_iommu_types.h.
| #define PASID_MASK 0x000fffff |
Definition at line 99 of file amd_iommu_types.h.
Definition at line 319 of file amd_iommu_types.h.
| #define PD_DEFAULT_MASK |
Definition at line 323 of file amd_iommu_types.h.
| #define PD_DMA_OPS_MASK (1UL << 0) /* domain used for dma_ops */ |
Definition at line 322 of file amd_iommu_types.h.
| #define PD_IOMMUV2_MASK (1UL << 3) /* domain has gcr3 table */ |
Definition at line 325 of file amd_iommu_types.h.
| #define PD_PASSTHROUGH_MASK |
Definition at line 324 of file amd_iommu_types.h.
| #define PM_ADDR_MASK 0x000ffffffffff000ULL |
Definition at line 237 of file amd_iommu_types.h.
| #define PM_ALIGNED | ( | lvl, | |
| addr | |||
| ) | ((PM_MAP_MASK(lvl) & (addr)) == (addr)) |
Definition at line 240 of file amd_iommu_types.h.
Definition at line 231 of file amd_iommu_types.h.
| #define PM_LEVEL_INDEX | ( | x, | |
| a | |||
| ) | (((a) >> PM_LEVEL_SHIFT((x))) & 0x1ffULL) |
Definition at line 230 of file amd_iommu_types.h.
Definition at line 232 of file amd_iommu_types.h.
Definition at line 226 of file amd_iommu_types.h.
| #define PM_LEVEL_SIZE | ( | x | ) |
Definition at line 227 of file amd_iommu_types.h.
| #define PM_MAP_4k 0 |
Definition at line 236 of file amd_iommu_types.h.
| #define PM_MAP_MASK | ( | lvl | ) |
Definition at line 238 of file amd_iommu_types.h.
Definition at line 234 of file amd_iommu_types.h.
Definition at line 210 of file amd_iommu_types.h.
| #define PPR_ENTRY_SIZE 16 |
Definition at line 205 of file amd_iommu_types.h.
| #define PPR_FAULT_EXEC (1 << 1) |
Definition at line 385 of file amd_iommu_types.h.
| #define PPR_FAULT_GN (1 << 8) |
Definition at line 390 of file amd_iommu_types.h.
| #define PPR_FAULT_READ (1 << 2) |
Definition at line 386 of file amd_iommu_types.h.
| #define PPR_FAULT_RSVD (1 << 7) |
Definition at line 389 of file amd_iommu_types.h.
| #define PPR_FAULT_USER (1 << 6) |
Definition at line 388 of file amd_iommu_types.h.
| #define PPR_FAULT_WRITE (1 << 5) |
Definition at line 387 of file amd_iommu_types.h.
Definition at line 209 of file amd_iommu_types.h.
| #define PPR_LOG_ENTRIES 512 |
Definition at line 202 of file amd_iommu_types.h.
| #define PPR_LOG_SIZE (PPR_ENTRY_SIZE * PPR_LOG_ENTRIES) |
Definition at line 206 of file amd_iommu_types.h.
| #define PPR_LOG_SIZE_512 (0x9ULL << PPR_LOG_SIZE_SHIFT) |
Definition at line 204 of file amd_iommu_types.h.
| #define PPR_LOG_SIZE_SHIFT 56 |
Definition at line 203 of file amd_iommu_types.h.
| #define PPR_PASID | ( | x | ) | ((PPR_PASID2(x) << 16) | PPR_PASID1(x)) |
Definition at line 214 of file amd_iommu_types.h.
Definition at line 212 of file amd_iommu_types.h.
Definition at line 213 of file amd_iommu_types.h.
| #define PPR_REQ_FAULT 0x01 |
Definition at line 216 of file amd_iommu_types.h.
Definition at line 208 of file amd_iommu_types.h.
| #define PPR_STATUS_MASK 0xf |
Definition at line 165 of file amd_iommu_types.h.
| #define PPR_STATUS_SHIFT 12 |
Definition at line 166 of file amd_iommu_types.h.
Definition at line 211 of file amd_iommu_types.h.
| #define PTE_PAGE_SIZE | ( | pte | ) | (1ULL << (1 + ffz(((pte) | 0xfffULL)))) |
Definition at line 273 of file amd_iommu_types.h.
Definition at line 38 of file amd_iommu_types.h.
Definition at line 756 of file amd_iommu_types.h.
Definition at line 1061 of file amd_iommu.c.
| u16* amd_iommu_alias_table |
Definition at line 179 of file amd_iommu_init.c.
| unsigned amd_iommu_aperture_order |
| struct dev_table_entry* amd_iommu_dev_table |
Definition at line 172 of file amd_iommu_init.c.
| bool amd_iommu_dump |
Definition at line 131 of file amd_iommu_init.c.
| bool amd_iommu_force_isolation |
| bool amd_iommu_iotlb_sup |
| struct kmem_cache* amd_iommu_irq_cache |
Definition at line 105 of file amd_iommu.c.
| bool amd_iommu_irq_remap |
| u16 amd_iommu_last_bdf |
Definition at line 137 of file amd_iommu_init.c.
| int amd_iommu_max_glx_val |
Definition at line 94 of file amd_iommu.c.
| u32 amd_iommu_max_pasids |
| bool amd_iommu_np_cache |
| unsigned long* amd_iommu_pd_alloc_bitmap |
Definition at line 197 of file amd_iommu_init.c.
| spinlock_t amd_iommu_pd_lock |
Definition at line 164 of file amd_iommu_init.c.
Definition at line 185 of file amd_iommu_init.c.
| u32 amd_iommu_unmap_flush |
Definition at line 141 of file amd_iommu_init.c.
| bool amd_iommu_v2_present |
| struct amd_iommu* amd_iommus[MAX_IOMMUS] |
Definition at line 147 of file amd_iommu_init.c.
| int amd_iommus_present |
Definition at line 148 of file amd_iommu_init.c.
| struct irq_remap_table** irq_lookup_table |
Definition at line 191 of file amd_iommu_init.c.
1.8.2