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Linux Kernel
3.7.1
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Linux Kernel
3.7.1
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Macros | |
| #define | dma_outb outb |
| #define | dma_inb inb |
| #define | MAX_DMA_CHANNELS 8 |
| #define | ALPHA_XL_MAX_ISA_DMA_ADDRESS 0x04000000UL |
| #define | ALPHA_RUFFIAN_MAX_ISA_DMA_ADDRESS 0x01000000UL |
| #define | ALPHA_SABLE_MAX_ISA_DMA_ADDRESS 0x80000000UL |
| #define | ALPHA_ALCOR_MAX_ISA_DMA_ADDRESS 0x80000000UL |
| #define | ALPHA_MAX_ISA_DMA_ADDRESS 0x100000000UL |
| #define | MAX_ISA_DMA_ADDRESS ALPHA_MAX_ISA_DMA_ADDRESS |
| #define | MAX_DMA_ADDRESS |
| #define | IO_DMA1_BASE 0x00 /* 8 bit slave DMA, channels 0..3 */ |
| #define | IO_DMA2_BASE 0xC0 /* 16 bit master DMA, ch 4(=slave input)..7 */ |
| #define | DMA1_CMD_REG 0x08 /* command register (w) */ |
| #define | DMA1_STAT_REG 0x08 /* status register (r) */ |
| #define | DMA1_REQ_REG 0x09 /* request register (w) */ |
| #define | DMA1_MASK_REG 0x0A /* single-channel mask (w) */ |
| #define | DMA1_MODE_REG 0x0B /* mode register (w) */ |
| #define | DMA1_CLEAR_FF_REG 0x0C /* clear pointer flip-flop (w) */ |
| #define | DMA1_TEMP_REG 0x0D /* Temporary Register (r) */ |
| #define | DMA1_RESET_REG 0x0D /* Master Clear (w) */ |
| #define | DMA1_CLR_MASK_REG 0x0E /* Clear Mask */ |
| #define | DMA1_MASK_ALL_REG 0x0F /* all-channels mask (w) */ |
| #define | DMA1_EXT_MODE_REG (0x400 | DMA1_MODE_REG) |
| #define | DMA2_CMD_REG 0xD0 /* command register (w) */ |
| #define | DMA2_STAT_REG 0xD0 /* status register (r) */ |
| #define | DMA2_REQ_REG 0xD2 /* request register (w) */ |
| #define | DMA2_MASK_REG 0xD4 /* single-channel mask (w) */ |
| #define | DMA2_MODE_REG 0xD6 /* mode register (w) */ |
| #define | DMA2_CLEAR_FF_REG 0xD8 /* clear pointer flip-flop (w) */ |
| #define | DMA2_TEMP_REG 0xDA /* Temporary Register (r) */ |
| #define | DMA2_RESET_REG 0xDA /* Master Clear (w) */ |
| #define | DMA2_CLR_MASK_REG 0xDC /* Clear Mask */ |
| #define | DMA2_MASK_ALL_REG 0xDE /* all-channels mask (w) */ |
| #define | DMA2_EXT_MODE_REG (0x400 | DMA2_MODE_REG) |
| #define | DMA_ADDR_0 0x00 /* DMA address registers */ |
| #define | DMA_ADDR_1 0x02 |
| #define | DMA_ADDR_2 0x04 |
| #define | DMA_ADDR_3 0x06 |
| #define | DMA_ADDR_4 0xC0 |
| #define | DMA_ADDR_5 0xC4 |
| #define | DMA_ADDR_6 0xC8 |
| #define | DMA_ADDR_7 0xCC |
| #define | DMA_CNT_0 0x01 /* DMA count registers */ |
| #define | DMA_CNT_1 0x03 |
| #define | DMA_CNT_2 0x05 |
| #define | DMA_CNT_3 0x07 |
| #define | DMA_CNT_4 0xC2 |
| #define | DMA_CNT_5 0xC6 |
| #define | DMA_CNT_6 0xCA |
| #define | DMA_CNT_7 0xCE |
| #define | DMA_PAGE_0 0x87 /* DMA page registers */ |
| #define | DMA_PAGE_1 0x83 |
| #define | DMA_PAGE_2 0x81 |
| #define | DMA_PAGE_3 0x82 |
| #define | DMA_PAGE_5 0x8B |
| #define | DMA_PAGE_6 0x89 |
| #define | DMA_PAGE_7 0x8A |
| #define | DMA_HIPAGE_0 (0x400 | DMA_PAGE_0) |
| #define | DMA_HIPAGE_1 (0x400 | DMA_PAGE_1) |
| #define | DMA_HIPAGE_2 (0x400 | DMA_PAGE_2) |
| #define | DMA_HIPAGE_3 (0x400 | DMA_PAGE_3) |
| #define | DMA_HIPAGE_4 (0x400 | DMA_PAGE_4) |
| #define | DMA_HIPAGE_5 (0x400 | DMA_PAGE_5) |
| #define | DMA_HIPAGE_6 (0x400 | DMA_PAGE_6) |
| #define | DMA_HIPAGE_7 (0x400 | DMA_PAGE_7) |
| #define | DMA_MODE_READ 0x44 /* I/O to memory, no autoinit, increment, single mode */ |
| #define | DMA_MODE_WRITE 0x48 /* memory to I/O, no autoinit, increment, single mode */ |
| #define | DMA_MODE_CASCADE 0xC0 /* pass thru DREQ->HRQ, DACK<-HLDA only */ |
| #define | DMA_AUTOINIT 0x10 |
| #define | KERNEL_HAVE_CHECK_DMA |
| #define | isa_dma_bridge_buggy (0) |
Functions | |
| int | request_dma (unsigned int dmanr, const char *device_id) |
| void | free_dma (unsigned int dmanr) |
| int | check_dma (unsigned int dmanr) |
Variables | |
| spinlock_t | dma_spin_lock |
| #define DMA1_CLEAR_FF_REG 0x0C /* clear pointer flip-flop (w) */ |
| #define DMA2_CLEAR_FF_REG 0xD8 /* clear pointer flip-flop (w) */ |
| #define DMA_MODE_CASCADE 0xC0 /* pass thru DREQ->HRQ, DACK<-HLDA only */ |
| #define DMA_MODE_READ 0x44 /* I/O to memory, no autoinit, increment, single mode */ |
| #define DMA_MODE_WRITE 0x48 /* memory to I/O, no autoinit, increment, single mode */ |
| #define IO_DMA1_BASE 0x00 /* 8 bit slave DMA, channels 0..3 */ |
| #define IO_DMA2_BASE 0xC0 /* 16 bit master DMA, ch 4(=slave input)..7 */ |
| #define MAX_DMA_ADDRESS |
| #define MAX_ISA_DMA_ADDRESS ALPHA_MAX_ISA_DMA_ADDRESS |
| spinlock_t dma_spin_lock |
1.8.2