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dma.h
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1 /*
2  * include/asm-alpha/dma.h
3  *
4  * This is essentially the same as the i386 DMA stuff, as the AlphaPCs
5  * use ISA-compatible dma. The only extension is support for high-page
6  * registers that allow to set the top 8 bits of a 32-bit DMA address.
7  * This register should be written last when setting up a DMA address
8  * as this will also enable DMA across 64 KB boundaries.
9  */
10 
11 /* $Id: dma.h,v 1.7 1992/12/14 00:29:34 root Exp root $
12  * linux/include/asm/dma.h: Defines for using and allocating dma channels.
13  * Written by Hennus Bergman, 1992.
14  * High DMA channel support & info by Hannu Savolainen
15  * and John Boyd, Nov. 1992.
16  */
17 
18 #ifndef _ASM_DMA_H
19 #define _ASM_DMA_H
20 
21 #include <linux/spinlock.h>
22 #include <asm/io.h>
23 
24 #define dma_outb outb
25 #define dma_inb inb
26 
27 /*
28  * NOTES about DMA transfers:
29  *
30  * controller 1: channels 0-3, byte operations, ports 00-1F
31  * controller 2: channels 4-7, word operations, ports C0-DF
32  *
33  * - ALL registers are 8 bits only, regardless of transfer size
34  * - channel 4 is not used - cascades 1 into 2.
35  * - channels 0-3 are byte - addresses/counts are for physical bytes
36  * - channels 5-7 are word - addresses/counts are for physical words
37  * - transfers must not cross physical 64K (0-3) or 128K (5-7) boundaries
38  * - transfer count loaded to registers is 1 less than actual count
39  * - controller 2 offsets are all even (2x offsets for controller 1)
40  * - page registers for 5-7 don't use data bit 0, represent 128K pages
41  * - page registers for 0-3 use bit 0, represent 64K pages
42  *
43  * DMA transfers are limited to the lower 16MB of _physical_ memory.
44  * Note that addresses loaded into registers must be _physical_ addresses,
45  * not logical addresses (which may differ if paging is active).
46  *
47  * Address mapping for channels 0-3:
48  *
49  * A23 ... A16 A15 ... A8 A7 ... A0 (Physical addresses)
50  * | ... | | ... | | ... |
51  * | ... | | ... | | ... |
52  * | ... | | ... | | ... |
53  * P7 ... P0 A7 ... A0 A7 ... A0
54  * | Page | Addr MSB | Addr LSB | (DMA registers)
55  *
56  * Address mapping for channels 5-7:
57  *
58  * A23 ... A17 A16 A15 ... A9 A8 A7 ... A1 A0 (Physical addresses)
59  * | ... | \ \ ... \ \ \ ... \ \
60  * | ... | \ \ ... \ \ \ ... \ (not used)
61  * | ... | \ \ ... \ \ \ ... \
62  * P7 ... P1 (0) A7 A6 ... A0 A7 A6 ... A0
63  * | Page | Addr MSB | Addr LSB | (DMA registers)
64  *
65  * Again, channels 5-7 transfer _physical_ words (16 bits), so addresses
66  * and counts _must_ be word-aligned (the lowest address bit is _ignored_ at
67  * the hardware level, so odd-byte transfers aren't possible).
68  *
69  * Transfer count (_not # bytes_) is limited to 64K, represented as actual
70  * count - 1 : 64K => 0xFFFF, 1 => 0x0000. Thus, count is always 1 or more,
71  * and up to 128K bytes may be transferred on channels 5-7 in one operation.
72  *
73  */
74 
75 #define MAX_DMA_CHANNELS 8
76 
77 /*
78  ISA DMA limitations on Alpha platforms,
79 
80  These may be due to SIO (PCI<->ISA bridge) chipset limitation, or
81  just a wiring limit.
82 */
83 
84 /* The maximum address for ISA DMA transfer on Alpha XL, due to an
85  hardware SIO limitation, is 64MB.
86 */
87 #define ALPHA_XL_MAX_ISA_DMA_ADDRESS 0x04000000UL
88 
89 /* The maximum address for ISA DMA transfer on RUFFIAN,
90  due to an hardware SIO limitation, is 16MB.
91 */
92 #define ALPHA_RUFFIAN_MAX_ISA_DMA_ADDRESS 0x01000000UL
93 
94 /* The maximum address for ISA DMA transfer on SABLE, and some ALCORs,
95  due to an hardware SIO chip limitation, is 2GB.
96 */
97 #define ALPHA_SABLE_MAX_ISA_DMA_ADDRESS 0x80000000UL
98 #define ALPHA_ALCOR_MAX_ISA_DMA_ADDRESS 0x80000000UL
99 
100 /*
101  Maximum address for all the others is the complete 32-bit bus
102  address space.
103 */
104 #define ALPHA_MAX_ISA_DMA_ADDRESS 0x100000000UL
105 
106 #ifdef CONFIG_ALPHA_GENERIC
107 # define MAX_ISA_DMA_ADDRESS (alpha_mv.max_isa_dma_address)
108 #else
109 # if defined(CONFIG_ALPHA_XL)
110 # define MAX_ISA_DMA_ADDRESS ALPHA_XL_MAX_ISA_DMA_ADDRESS
111 # elif defined(CONFIG_ALPHA_RUFFIAN)
112 # define MAX_ISA_DMA_ADDRESS ALPHA_RUFFIAN_MAX_ISA_DMA_ADDRESS
113 # elif defined(CONFIG_ALPHA_SABLE)
114 # define MAX_ISA_DMA_ADDRESS ALPHA_SABLE_MAX_ISA_DMA_ADDRESS
115 # elif defined(CONFIG_ALPHA_ALCOR)
116 # define MAX_ISA_DMA_ADDRESS ALPHA_ALCOR_MAX_ISA_DMA_ADDRESS
117 # else
118 # define MAX_ISA_DMA_ADDRESS ALPHA_MAX_ISA_DMA_ADDRESS
119 # endif
120 #endif
121 
122 /* If we have the iommu, we don't have any address limitations on DMA.
123  Otherwise (Nautilus, RX164), we have to have 0-16 Mb DMA zone
124  like i386. */
125 #define MAX_DMA_ADDRESS (alpha_mv.mv_pci_tbi ? \
126  ~0UL : IDENT_ADDR + 0x01000000)
127 
128 /* 8237 DMA controllers */
129 #define IO_DMA1_BASE 0x00 /* 8 bit slave DMA, channels 0..3 */
130 #define IO_DMA2_BASE 0xC0 /* 16 bit master DMA, ch 4(=slave input)..7 */
131 
132 /* DMA controller registers */
133 #define DMA1_CMD_REG 0x08 /* command register (w) */
134 #define DMA1_STAT_REG 0x08 /* status register (r) */
135 #define DMA1_REQ_REG 0x09 /* request register (w) */
136 #define DMA1_MASK_REG 0x0A /* single-channel mask (w) */
137 #define DMA1_MODE_REG 0x0B /* mode register (w) */
138 #define DMA1_CLEAR_FF_REG 0x0C /* clear pointer flip-flop (w) */
139 #define DMA1_TEMP_REG 0x0D /* Temporary Register (r) */
140 #define DMA1_RESET_REG 0x0D /* Master Clear (w) */
141 #define DMA1_CLR_MASK_REG 0x0E /* Clear Mask */
142 #define DMA1_MASK_ALL_REG 0x0F /* all-channels mask (w) */
143 #define DMA1_EXT_MODE_REG (0x400 | DMA1_MODE_REG)
144 
145 #define DMA2_CMD_REG 0xD0 /* command register (w) */
146 #define DMA2_STAT_REG 0xD0 /* status register (r) */
147 #define DMA2_REQ_REG 0xD2 /* request register (w) */
148 #define DMA2_MASK_REG 0xD4 /* single-channel mask (w) */
149 #define DMA2_MODE_REG 0xD6 /* mode register (w) */
150 #define DMA2_CLEAR_FF_REG 0xD8 /* clear pointer flip-flop (w) */
151 #define DMA2_TEMP_REG 0xDA /* Temporary Register (r) */
152 #define DMA2_RESET_REG 0xDA /* Master Clear (w) */
153 #define DMA2_CLR_MASK_REG 0xDC /* Clear Mask */
154 #define DMA2_MASK_ALL_REG 0xDE /* all-channels mask (w) */
155 #define DMA2_EXT_MODE_REG (0x400 | DMA2_MODE_REG)
156 
157 #define DMA_ADDR_0 0x00 /* DMA address registers */
158 #define DMA_ADDR_1 0x02
159 #define DMA_ADDR_2 0x04
160 #define DMA_ADDR_3 0x06
161 #define DMA_ADDR_4 0xC0
162 #define DMA_ADDR_5 0xC4
163 #define DMA_ADDR_6 0xC8
164 #define DMA_ADDR_7 0xCC
165 
166 #define DMA_CNT_0 0x01 /* DMA count registers */
167 #define DMA_CNT_1 0x03
168 #define DMA_CNT_2 0x05
169 #define DMA_CNT_3 0x07
170 #define DMA_CNT_4 0xC2
171 #define DMA_CNT_5 0xC6
172 #define DMA_CNT_6 0xCA
173 #define DMA_CNT_7 0xCE
174 
175 #define DMA_PAGE_0 0x87 /* DMA page registers */
176 #define DMA_PAGE_1 0x83
177 #define DMA_PAGE_2 0x81
178 #define DMA_PAGE_3 0x82
179 #define DMA_PAGE_5 0x8B
180 #define DMA_PAGE_6 0x89
181 #define DMA_PAGE_7 0x8A
182 
183 #define DMA_HIPAGE_0 (0x400 | DMA_PAGE_0)
184 #define DMA_HIPAGE_1 (0x400 | DMA_PAGE_1)
185 #define DMA_HIPAGE_2 (0x400 | DMA_PAGE_2)
186 #define DMA_HIPAGE_3 (0x400 | DMA_PAGE_3)
187 #define DMA_HIPAGE_4 (0x400 | DMA_PAGE_4)
188 #define DMA_HIPAGE_5 (0x400 | DMA_PAGE_5)
189 #define DMA_HIPAGE_6 (0x400 | DMA_PAGE_6)
190 #define DMA_HIPAGE_7 (0x400 | DMA_PAGE_7)
191 
192 #define DMA_MODE_READ 0x44 /* I/O to memory, no autoinit, increment, single mode */
193 #define DMA_MODE_WRITE 0x48 /* memory to I/O, no autoinit, increment, single mode */
194 #define DMA_MODE_CASCADE 0xC0 /* pass thru DREQ->HRQ, DACK<-HLDA only */
195 
196 #define DMA_AUTOINIT 0x10
197 
198 extern spinlock_t dma_spin_lock;
199 
200 static __inline__ unsigned long claim_dma_lock(void)
201 {
202  unsigned long flags;
203  spin_lock_irqsave(&dma_spin_lock, flags);
204  return flags;
205 }
206 
207 static __inline__ void release_dma_lock(unsigned long flags)
208 {
209  spin_unlock_irqrestore(&dma_spin_lock, flags);
210 }
211 
212 /* enable/disable a specific DMA channel */
213 static __inline__ void enable_dma(unsigned int dmanr)
214 {
215  if (dmanr<=3)
216  dma_outb(dmanr, DMA1_MASK_REG);
217  else
218  dma_outb(dmanr & 3, DMA2_MASK_REG);
219 }
220 
221 static __inline__ void disable_dma(unsigned int dmanr)
222 {
223  if (dmanr<=3)
224  dma_outb(dmanr | 4, DMA1_MASK_REG);
225  else
226  dma_outb((dmanr & 3) | 4, DMA2_MASK_REG);
227 }
228 
229 /* Clear the 'DMA Pointer Flip Flop'.
230  * Write 0 for LSB/MSB, 1 for MSB/LSB access.
231  * Use this once to initialize the FF to a known state.
232  * After that, keep track of it. :-)
233  * --- In order to do that, the DMA routines below should ---
234  * --- only be used while interrupts are disabled! ---
235  */
236 static __inline__ void clear_dma_ff(unsigned int dmanr)
237 {
238  if (dmanr<=3)
239  dma_outb(0, DMA1_CLEAR_FF_REG);
240  else
241  dma_outb(0, DMA2_CLEAR_FF_REG);
242 }
243 
244 /* set mode (above) for a specific DMA channel */
245 static __inline__ void set_dma_mode(unsigned int dmanr, char mode)
246 {
247  if (dmanr<=3)
248  dma_outb(mode | dmanr, DMA1_MODE_REG);
249  else
250  dma_outb(mode | (dmanr&3), DMA2_MODE_REG);
251 }
252 
253 /* set extended mode for a specific DMA channel */
254 static __inline__ void set_dma_ext_mode(unsigned int dmanr, char ext_mode)
255 {
256  if (dmanr<=3)
257  dma_outb(ext_mode | dmanr, DMA1_EXT_MODE_REG);
258  else
259  dma_outb(ext_mode | (dmanr&3), DMA2_EXT_MODE_REG);
260 }
261 
262 /* Set only the page register bits of the transfer address.
263  * This is used for successive transfers when we know the contents of
264  * the lower 16 bits of the DMA current address register.
265  */
266 static __inline__ void set_dma_page(unsigned int dmanr, unsigned int pagenr)
267 {
268  switch(dmanr) {
269  case 0:
270  dma_outb(pagenr, DMA_PAGE_0);
271  dma_outb((pagenr >> 8), DMA_HIPAGE_0);
272  break;
273  case 1:
274  dma_outb(pagenr, DMA_PAGE_1);
275  dma_outb((pagenr >> 8), DMA_HIPAGE_1);
276  break;
277  case 2:
278  dma_outb(pagenr, DMA_PAGE_2);
279  dma_outb((pagenr >> 8), DMA_HIPAGE_2);
280  break;
281  case 3:
282  dma_outb(pagenr, DMA_PAGE_3);
283  dma_outb((pagenr >> 8), DMA_HIPAGE_3);
284  break;
285  case 5:
286  dma_outb(pagenr & 0xfe, DMA_PAGE_5);
287  dma_outb((pagenr >> 8), DMA_HIPAGE_5);
288  break;
289  case 6:
290  dma_outb(pagenr & 0xfe, DMA_PAGE_6);
291  dma_outb((pagenr >> 8), DMA_HIPAGE_6);
292  break;
293  case 7:
294  dma_outb(pagenr & 0xfe, DMA_PAGE_7);
295  dma_outb((pagenr >> 8), DMA_HIPAGE_7);
296  break;
297  }
298 }
299 
300 
301 /* Set transfer address & page bits for specific DMA channel.
302  * Assumes dma flipflop is clear.
303  */
304 static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int a)
305 {
306  if (dmanr <= 3) {
307  dma_outb( a & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE );
308  dma_outb( (a>>8) & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE );
309  } else {
310  dma_outb( (a>>1) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
311  dma_outb( (a>>9) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
312  }
313  set_dma_page(dmanr, a>>16); /* set hipage last to enable 32-bit mode */
314 }
315 
316 
317 /* Set transfer size (max 64k for DMA1..3, 128k for DMA5..7) for
318  * a specific DMA channel.
319  * You must ensure the parameters are valid.
320  * NOTE: from a manual: "the number of transfers is one more
321  * than the initial word count"! This is taken into account.
322  * Assumes dma flip-flop is clear.
323  * NOTE 2: "count" represents _bytes_ and must be even for channels 5-7.
324  */
325 static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count)
326 {
327  count--;
328  if (dmanr <= 3) {
329  dma_outb( count & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE );
330  dma_outb( (count>>8) & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE );
331  } else {
332  dma_outb( (count>>1) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
333  dma_outb( (count>>9) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
334  }
335 }
336 
337 
338 /* Get DMA residue count. After a DMA transfer, this
339  * should return zero. Reading this while a DMA transfer is
340  * still in progress will return unpredictable results.
341  * If called before the channel has been used, it may return 1.
342  * Otherwise, it returns the number of _bytes_ left to transfer.
343  *
344  * Assumes DMA flip-flop is clear.
345  */
346 static __inline__ int get_dma_residue(unsigned int dmanr)
347 {
348  unsigned int io_port = (dmanr<=3)? ((dmanr&3)<<1) + 1 + IO_DMA1_BASE
349  : ((dmanr&3)<<2) + 2 + IO_DMA2_BASE;
350 
351  /* using short to get 16-bit wrap around */
352  unsigned short count;
353 
354  count = 1 + dma_inb(io_port);
355  count += dma_inb(io_port) << 8;
356 
357  return (dmanr<=3)? count : (count<<1);
358 }
359 
360 
361 /* These are in kernel/dma.c: */
362 extern int request_dma(unsigned int dmanr, const char * device_id); /* reserve a DMA channel */
363 extern void free_dma(unsigned int dmanr); /* release it again */
364 #define KERNEL_HAVE_CHECK_DMA
365 extern int check_dma(unsigned int dmanr);
366 
367 /* From PCI */
368 
369 #ifdef CONFIG_PCI
370 extern int isa_dma_bridge_buggy;
371 #else
372 #define isa_dma_bridge_buggy (0)
373 #endif
374 
375 
376 #endif /* _ASM_DMA_H */
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