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#define | dma_outb outb |
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#define | dma_inb inb |
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#define | DMA_CHUNK_SIZE (BITS_PER_LONG*PAGE_SIZE) |
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#define | MAX_DMA_ADDRESS (~0UL) |
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#define | MAX_DMA_CHANNELS 8 |
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#define | DMA_MODE_READ 0x44 /* I/O to memory, no autoinit, increment, single mode */ |
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#define | DMA_MODE_WRITE 0x48 /* memory to I/O, no autoinit, increment, single mode */ |
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#define | DMA_MODE_CASCADE 0xC0 /* pass thru DREQ->HRQ, DACK<-HLDA only */ |
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#define | DMA_AUTOINIT 0x10 |
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#define | IO_DMA1_BASE 0x00 /* 8 bit slave DMA, channels 0..3 */ |
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#define | IO_DMA2_BASE 0xC0 /* 16 bit master DMA, ch 4(=slave input)..7 */ |
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#define | DMA1_CMD_REG 0x08 /* command register (w) */ |
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#define | DMA1_STAT_REG 0x08 /* status register (r) */ |
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#define | DMA1_REQ_REG 0x09 /* request register (w) */ |
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#define | DMA1_MASK_REG 0x0A /* single-channel mask (w) */ |
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#define | DMA1_MODE_REG 0x0B /* mode register (w) */ |
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#define | DMA1_CLEAR_FF_REG 0x0C /* clear pointer flip-flop (w) */ |
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#define | DMA1_TEMP_REG 0x0D /* Temporary Register (r) */ |
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#define | DMA1_RESET_REG 0x0D /* Master Clear (w) */ |
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#define | DMA1_CLR_MASK_REG 0x0E /* Clear Mask */ |
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#define | DMA1_MASK_ALL_REG 0x0F /* all-channels mask (w) */ |
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#define | DMA1_EXT_MODE_REG (0x400 | DMA1_MODE_REG) |
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#define | DMA2_CMD_REG 0xD0 /* command register (w) */ |
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#define | DMA2_STAT_REG 0xD0 /* status register (r) */ |
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#define | DMA2_REQ_REG 0xD2 /* request register (w) */ |
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#define | DMA2_MASK_REG 0xD4 /* single-channel mask (w) */ |
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#define | DMA2_MODE_REG 0xD6 /* mode register (w) */ |
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#define | DMA2_CLEAR_FF_REG 0xD8 /* clear pointer flip-flop (w) */ |
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#define | DMA2_TEMP_REG 0xDA /* Temporary Register (r) */ |
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#define | DMA2_RESET_REG 0xDA /* Master Clear (w) */ |
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#define | DMA2_CLR_MASK_REG 0xDC /* Clear Mask */ |
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#define | DMA2_MASK_ALL_REG 0xDE /* all-channels mask (w) */ |
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#define | DMA2_EXT_MODE_REG (0x400 | DMA2_MODE_REG) |
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#define | request_dma(dmanr, device_id) (0) |
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#define | free_dma(dmanr) |
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#define | isa_dma_bridge_buggy (0) |
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