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pm.h
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1 /*
2  * AT91 Power Management
3  *
4  * Copyright (C) 2005 David Brownell
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10  */
11 #ifndef __ARCH_ARM_MACH_AT91_PM
12 #define __ARCH_ARM_MACH_AT91_PM
13 
14 #include <mach/at91_ramc.h>
15 #include <mach/at91rm9200_sdramc.h>
16 
17 /*
18  * The AT91RM9200 goes into self-refresh mode with this command, and will
19  * terminate self-refresh automatically on the next SDRAM access.
20  *
21  * Self-refresh mode is exited as soon as a memory access is made, but we don't
22  * know for sure when that happens. However, we need to restore the low-power
23  * mode if it was enabled before going idle. Restoring low-power mode while
24  * still in self-refresh is "not recommended", but seems to work.
25  */
26 
27 static inline void at91rm9200_standby(void)
28 {
30 
31  asm volatile(
32  "b 1f\n\t"
33  ".align 5\n\t"
34  "1: mcr p15, 0, %0, c7, c10, 4\n\t"
35  " str %0, [%1, %2]\n\t"
36  " str %3, [%1, %4]\n\t"
37  " mcr p15, 0, %0, c7, c0, 4\n\t"
38  " str %5, [%1, %2]"
39  :
40  : "r" (0), "r" (AT91_BASE_SYS), "r" (AT91RM9200_SDRAMC_LPR),
41  "r" (1), "r" (AT91RM9200_SDRAMC_SRR),
42  "r" (lpr));
43 }
44 
45 /* We manage both DDRAM/SDRAM controllers, we need more than one value to
46  * remember.
47  */
48 static inline void at91sam9g45_standby(void)
49 {
50  /* Those two values allow us to delay self-refresh activation
51  * to the maximum. */
52  u32 lpr0, lpr1;
53  u32 saved_lpr0, saved_lpr1;
54 
55  saved_lpr1 = at91_ramc_read(1, AT91_DDRSDRC_LPR);
56  lpr1 = saved_lpr1 & ~AT91_DDRSDRC_LPCB;
58 
59  saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR);
60  lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB;
62 
63  /* self-refresh mode now */
66 
67  cpu_do_idle();
68 
69  at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0);
70  at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1);
71 }
72 
73 #ifdef CONFIG_SOC_AT91SAM9263
74 /*
75  * FIXME either or both the SDRAM controllers (EB0, EB1) might be in use;
76  * handle those cases both here and in the Suspend-To-RAM support.
77  */
78 #warning Assuming EB1 SDRAM controller is *NOT* used
79 #endif
80 
81 static inline void at91sam9_standby(void)
82 {
83  u32 saved_lpr, lpr;
84 
85  saved_lpr = at91_ramc_read(0, AT91_SDRAMC_LPR);
86 
87  lpr = saved_lpr & ~AT91_SDRAMC_LPCB;
90 
91  cpu_do_idle();
92 
93  at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr);
94 }
95 
96 #endif