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arch
arm
mach-lpc32xx
serial.c
Go to the documentation of this file.
1
/*
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* arch/arm/mach-lpc32xx/serial.c
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*
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* Author: Kevin Wells <
[email protected]
>
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*
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* Copyright (C) 2010 NXP Semiconductors
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/serial.h>
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#include <linux/serial_core.h>
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#include <
linux/serial_reg.h
>
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#include <
linux/serial_8250.h
>
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#include <
linux/clk.h
>
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#include <
linux/io.h
>
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#include <mach/hardware.h>
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#include <mach/platform.h>
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#include "
common.h
"
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#define LPC32XX_SUART_FIFO_SIZE 64
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struct
uartinit
{
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char
*
uart_ck_name
;
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u32
ck_mode_mask
;
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void
__iomem
*
pdiv_clk_reg
;
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resource_size_t
mapbase
;
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};
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static
struct
uartinit
uartinit_data[]
__initdata
= {
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{
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.uart_ck_name =
"uart5_ck"
,
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.ck_mode_mask =
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LPC32XX_UART_CLKMODE_LOAD
(
LPC32XX_UART_CLKMODE_ON
, 5),
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.pdiv_clk_reg =
LPC32XX_CLKPWR_UART5_CLK_CTRL
,
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.mapbase =
LPC32XX_UART5_BASE
,
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},
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{
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.uart_ck_name =
"uart3_ck"
,
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.ck_mode_mask =
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LPC32XX_UART_CLKMODE_LOAD
(
LPC32XX_UART_CLKMODE_ON
, 3),
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.pdiv_clk_reg =
LPC32XX_CLKPWR_UART3_CLK_CTRL
,
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.mapbase =
LPC32XX_UART3_BASE
,
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},
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{
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.uart_ck_name =
"uart4_ck"
,
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.ck_mode_mask =
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LPC32XX_UART_CLKMODE_LOAD
(
LPC32XX_UART_CLKMODE_ON
, 4),
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.pdiv_clk_reg =
LPC32XX_CLKPWR_UART4_CLK_CTRL
,
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.mapbase =
LPC32XX_UART4_BASE
,
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},
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{
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.uart_ck_name =
"uart6_ck"
,
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.ck_mode_mask =
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LPC32XX_UART_CLKMODE_LOAD
(
LPC32XX_UART_CLKMODE_ON
, 6),
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.pdiv_clk_reg =
LPC32XX_CLKPWR_UART6_CLK_CTRL
,
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.mapbase =
LPC32XX_UART6_BASE
,
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},
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};
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void
__init
lpc32xx_serial_init
(
void
)
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{
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u32
tmp
, clkmodes = 0;
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struct
clk
*
clk
;
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unsigned
int
puart;
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int
i
,
j
;
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/* UART clocks are off, let clock driver manage them */
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__raw_writel
(0,
LPC32XX_CLKPWR_UART_CLK_CTRL
);
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for
(i = 0; i <
ARRAY_SIZE
(uartinit_data); i++) {
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clk =
clk_get
(
NULL
, uartinit_data[i].uart_ck_name);
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if
(!IS_ERR(clk)) {
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clk_enable
(clk);
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}
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/* Setup UART clock modes for all UARTs, disable autoclock */
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clkmodes |= uartinit_data[
i
].ck_mode_mask;
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/* pre-UART clock divider set to 1 */
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__raw_writel
(0x0101, uartinit_data[i].pdiv_clk_reg);
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/*
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* Force a flush of the RX FIFOs to work around a
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* HW bug
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*/
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puart = uartinit_data[
i
].mapbase;
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__raw_writel
(0xC1,
LPC32XX_UART_IIR_FCR
(puart));
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__raw_writel
(0x00,
LPC32XX_UART_DLL_FIFO
(puart));
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j =
LPC32XX_SUART_FIFO_SIZE
;
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while
(j--)
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tmp =
__raw_readl
(
104
LPC32XX_UART_DLL_FIFO
(puart));
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__raw_writel
(0,
LPC32XX_UART_IIR_FCR
(puart));
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}
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/* This needs to be done after all UART clocks are setup */
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__raw_writel
(clkmodes,
LPC32XX_UARTCTL_CLKMODE
);
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for
(i = 0; i <
ARRAY_SIZE
(uartinit_data); i++) {
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/* Force a flush of the RX FIFOs to work around a HW bug */
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puart = uartinit_data[
i
].mapbase;
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__raw_writel
(0xC1,
LPC32XX_UART_IIR_FCR
(puart));
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__raw_writel
(0x00,
LPC32XX_UART_DLL_FIFO
(puart));
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j =
LPC32XX_SUART_FIFO_SIZE
;
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while
(j--)
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tmp =
__raw_readl
(
LPC32XX_UART_DLL_FIFO
(puart));
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__raw_writel
(0,
LPC32XX_UART_IIR_FCR
(puart));
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}
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/* Disable IrDA pulsing support on UART6 */
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tmp =
__raw_readl
(
LPC32XX_UARTCTL_CTRL
);
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tmp |=
LPC32XX_UART_UART6_IRDAMOD_BYPASS
;
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__raw_writel
(tmp,
LPC32XX_UARTCTL_CTRL
);
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/* Disable UART5->USB transparent mode or USB won't work */
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tmp =
__raw_readl
(
LPC32XX_UARTCTL_CTRL
);
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tmp &= ~
LPC32XX_UART_U5_ROUTE_TO_USB
;
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__raw_writel
(tmp,
LPC32XX_UARTCTL_CTRL
);
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}
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