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Linux Kernel
3.7.1
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Linux Kernel
3.7.1
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Macros | |
| #define | UART_RX 0 /* In: Receive buffer */ |
| #define | UART_TX 0 /* Out: Transmit buffer */ |
| #define | UART_IER 1 /* Out: Interrupt Enable Register */ |
| #define | UART_IER_MSI 0x08 /* Enable Modem status interrupt */ |
| #define | UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */ |
| #define | UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */ |
| #define | UART_IER_RDI 0x01 /* Enable receiver data interrupt */ |
| #define | UART_IERX_SLEEP 0x10 /* Enable sleep mode */ |
| #define | UART_IIR 2 /* In: Interrupt ID Register */ |
| #define | UART_IIR_NO_INT 0x01 /* No interrupts pending */ |
| #define | UART_IIR_ID 0x06 /* Mask for the interrupt ID */ |
| #define | UART_IIR_MSI 0x00 /* Modem status interrupt */ |
| #define | UART_IIR_THRI 0x02 /* Transmitter holding register empty */ |
| #define | UART_IIR_RDI 0x04 /* Receiver data interrupt */ |
| #define | UART_IIR_RLSI 0x06 /* Receiver line status interrupt */ |
| #define | UART_IIR_BUSY 0x07 /* DesignWare APB Busy Detect */ |
| #define | UART_IIR_RX_TIMEOUT 0x0c /* OMAP RX Timeout interrupt */ |
| #define | UART_IIR_XOFF 0x10 /* OMAP XOFF/Special Character */ |
| #define | UART_IIR_CTS_RTS_DSR 0x20 /* OMAP CTS/RTS/DSR Change */ |
| #define | UART_FCR 2 /* Out: FIFO Control Register */ |
| #define | UART_FCR_ENABLE_FIFO 0x01 /* Enable the FIFO */ |
| #define | UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */ |
| #define | UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */ |
| #define | UART_FCR_DMA_SELECT 0x08 /* For DMA applications */ |
| #define | UART_FCR_R_TRIG_00 0x00 |
| #define | UART_FCR_R_TRIG_01 0x40 |
| #define | UART_FCR_R_TRIG_10 0x80 |
| #define | UART_FCR_R_TRIG_11 0xc0 |
| #define | UART_FCR_T_TRIG_00 0x00 |
| #define | UART_FCR_T_TRIG_01 0x10 |
| #define | UART_FCR_T_TRIG_10 0x20 |
| #define | UART_FCR_T_TRIG_11 0x30 |
| #define | UART_FCR_TRIGGER_MASK 0xC0 /* Mask for the FIFO trigger range */ |
| #define | UART_FCR_TRIGGER_1 0x00 /* Mask for trigger set at 1 */ |
| #define | UART_FCR_TRIGGER_4 0x40 /* Mask for trigger set at 4 */ |
| #define | UART_FCR_TRIGGER_8 0x80 /* Mask for trigger set at 8 */ |
| #define | UART_FCR_TRIGGER_14 0xC0 /* Mask for trigger set at 14 */ |
| #define | UART_FCR6_R_TRIGGER_8 0x00 /* Mask for receive trigger set at 1 */ |
| #define | UART_FCR6_R_TRIGGER_16 0x40 /* Mask for receive trigger set at 4 */ |
| #define | UART_FCR6_R_TRIGGER_24 0x80 /* Mask for receive trigger set at 8 */ |
| #define | UART_FCR6_R_TRIGGER_28 0xC0 /* Mask for receive trigger set at 14 */ |
| #define | UART_FCR6_T_TRIGGER_16 0x00 /* Mask for transmit trigger set at 16 */ |
| #define | UART_FCR6_T_TRIGGER_8 0x10 /* Mask for transmit trigger set at 8 */ |
| #define | UART_FCR6_T_TRIGGER_24 0x20 /* Mask for transmit trigger set at 24 */ |
| #define | UART_FCR6_T_TRIGGER_30 0x30 /* Mask for transmit trigger set at 30 */ |
| #define | UART_FCR7_64BYTE 0x20 /* Go into 64 byte mode (TI16C750) */ |
| #define | UART_LCR 3 /* Out: Line Control Register */ |
| #define | UART_LCR_DLAB 0x80 /* Divisor latch access bit */ |
| #define | UART_LCR_SBC 0x40 /* Set break control */ |
| #define | UART_LCR_SPAR 0x20 /* Stick parity (?) */ |
| #define | UART_LCR_EPAR 0x10 /* Even parity select */ |
| #define | UART_LCR_PARITY 0x08 /* Parity Enable */ |
| #define | UART_LCR_STOP 0x04 /* Stop bits: 0=1 bit, 1=2 bits */ |
| #define | UART_LCR_WLEN5 0x00 /* Wordlength: 5 bits */ |
| #define | UART_LCR_WLEN6 0x01 /* Wordlength: 6 bits */ |
| #define | UART_LCR_WLEN7 0x02 /* Wordlength: 7 bits */ |
| #define | UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */ |
| #define | UART_LCR_CONF_MODE_A UART_LCR_DLAB /* Configutation mode A */ |
| #define | UART_LCR_CONF_MODE_B 0xBF /* Configutation mode B */ |
| #define | UART_MCR 4 /* Out: Modem Control Register */ |
| #define | UART_MCR_CLKSEL 0x80 /* Divide clock by 4 (TI16C752, EFR[4]=1) */ |
| #define | UART_MCR_TCRTLR 0x40 /* Access TCR/TLR (TI16C752, EFR[4]=1) */ |
| #define | UART_MCR_XONANY 0x20 /* Enable Xon Any (TI16C752, EFR[4]=1) */ |
| #define | UART_MCR_AFE 0x20 /* Enable auto-RTS/CTS (TI16C550C/TI16C750) */ |
| #define | UART_MCR_LOOP 0x10 /* Enable loopback test mode */ |
| #define | UART_MCR_OUT2 0x08 /* Out2 complement */ |
| #define | UART_MCR_OUT1 0x04 /* Out1 complement */ |
| #define | UART_MCR_RTS 0x02 /* RTS complement */ |
| #define | UART_MCR_DTR 0x01 /* DTR complement */ |
| #define | UART_LSR 5 /* In: Line Status Register */ |
| #define | UART_LSR_FIFOE 0x80 /* Fifo error */ |
| #define | UART_LSR_TEMT 0x40 /* Transmitter empty */ |
| #define | UART_LSR_THRE 0x20 /* Transmit-hold-register empty */ |
| #define | UART_LSR_BI 0x10 /* Break interrupt indicator */ |
| #define | UART_LSR_FE 0x08 /* Frame error indicator */ |
| #define | UART_LSR_PE 0x04 /* Parity error indicator */ |
| #define | UART_LSR_OE 0x02 /* Overrun error indicator */ |
| #define | UART_LSR_DR 0x01 /* Receiver data ready */ |
| #define | UART_LSR_BRK_ERROR_BITS 0x1E /* BI, FE, PE, OE bits */ |
| #define | UART_MSR 6 /* In: Modem Status Register */ |
| #define | UART_MSR_DCD 0x80 /* Data Carrier Detect */ |
| #define | UART_MSR_RI 0x40 /* Ring Indicator */ |
| #define | UART_MSR_DSR 0x20 /* Data Set Ready */ |
| #define | UART_MSR_CTS 0x10 /* Clear to Send */ |
| #define | UART_MSR_DDCD 0x08 /* Delta DCD */ |
| #define | UART_MSR_TERI 0x04 /* Trailing edge ring indicator */ |
| #define | UART_MSR_DDSR 0x02 /* Delta DSR */ |
| #define | UART_MSR_DCTS 0x01 /* Delta CTS */ |
| #define | UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */ |
| #define | UART_SCR 7 /* I/O: Scratch Register */ |
| #define | UART_DLL 0 /* Out: Divisor Latch Low */ |
| #define | UART_DLM 1 /* Out: Divisor Latch High */ |
| #define | UART_EFR 2 /* I/O: Extended Features Register */ |
| #define | UART_XR_EFR 9 /* I/O: Extended Features Register (XR17D15x) */ |
| #define | UART_EFR_CTS 0x80 /* CTS flow control */ |
| #define | UART_EFR_RTS 0x40 /* RTS flow control */ |
| #define | UART_EFR_SCD 0x20 /* Special character detect */ |
| #define | UART_EFR_ECB 0x10 /* Enhanced control bit */ |
| #define | UART_XON1 4 /* I/O: Xon character 1 */ |
| #define | UART_XON2 5 /* I/O: Xon character 2 */ |
| #define | UART_XOFF1 6 /* I/O: Xoff character 1 */ |
| #define | UART_XOFF2 7 /* I/O: Xoff character 2 */ |
| #define | UART_TI752_TCR 6 /* I/O: transmission control register */ |
| #define | UART_TI752_TLR 7 /* I/O: trigger level register */ |
| #define | UART_TRG |
| #define | UART_TRG_1 0x01 |
| #define | UART_TRG_4 0x04 |
| #define | UART_TRG_8 0x08 |
| #define | UART_TRG_16 0x10 |
| #define | UART_TRG_32 0x20 |
| #define | UART_TRG_64 0x40 |
| #define | UART_TRG_96 0x60 |
| #define | UART_TRG_120 0x78 |
| #define | UART_TRG_128 0x80 |
| #define | UART_FCTR 1 /* Feature Control Register */ |
| #define | UART_FCTR_RTS_NODELAY 0x00 /* RTS flow control delay */ |
| #define | UART_FCTR_RTS_4DELAY 0x01 |
| #define | UART_FCTR_RTS_6DELAY 0x02 |
| #define | UART_FCTR_RTS_8DELAY 0x03 |
| #define | UART_FCTR_IRDA 0x04 /* IrDa data encode select */ |
| #define | UART_FCTR_TX_INT 0x08 /* Tx interrupt type select */ |
| #define | UART_FCTR_TRGA 0x00 /* Tx/Rx 550 trigger table select */ |
| #define | UART_FCTR_TRGB 0x10 /* Tx/Rx 650 trigger table select */ |
| #define | UART_FCTR_TRGC 0x20 /* Tx/Rx 654 trigger table select */ |
| #define | UART_FCTR_TRGD 0x30 /* Tx/Rx 850 programmable trigger select */ |
| #define | UART_FCTR_SCR_SWAP 0x40 /* Scratch pad register swap */ |
| #define | UART_FCTR_RX 0x00 /* Programmable trigger mode select */ |
| #define | UART_FCTR_TX 0x80 /* Programmable trigger mode select */ |
| #define | UART_EMSR 7 /* Extended Mode Select Register */ |
| #define | UART_EMSR_FIFO_COUNT 0x01 /* Rx/Tx select */ |
| #define | UART_EMSR_ALT_COUNT 0x02 /* Alternating count select */ |
| #define | UART_IER_DMAE 0x80 /* DMA Requests Enable */ |
| #define | UART_IER_UUE 0x40 /* UART Unit Enable */ |
| #define | UART_IER_NRZE 0x20 /* NRZ coding Enable */ |
| #define | UART_IER_RTOIE 0x10 /* Receiver Time Out Interrupt Enable */ |
| #define | UART_IIR_TOD 0x08 /* Character Timeout Indication Detected */ |
| #define | UART_FCR_PXAR1 0x00 /* receive FIFO threshold = 1 */ |
| #define | UART_FCR_PXAR8 0x40 /* receive FIFO threshold = 8 */ |
| #define | UART_FCR_PXAR16 0x80 /* receive FIFO threshold = 16 */ |
| #define | UART_FCR_PXAR32 0xc0 /* receive FIFO threshold = 32 */ |
| #define | UART_FCR_HSU_64_1B 0x00 /* receive FIFO treshold = 1 */ |
| #define | UART_FCR_HSU_64_16B 0x40 /* receive FIFO treshold = 16 */ |
| #define | UART_FCR_HSU_64_32B 0x80 /* receive FIFO treshold = 32 */ |
| #define | UART_FCR_HSU_64_56B 0xc0 /* receive FIFO treshold = 56 */ |
| #define | UART_FCR_HSU_16_1B 0x00 /* receive FIFO treshold = 1 */ |
| #define | UART_FCR_HSU_16_4B 0x40 /* receive FIFO treshold = 4 */ |
| #define | UART_FCR_HSU_16_8B 0x80 /* receive FIFO treshold = 8 */ |
| #define | UART_FCR_HSU_16_14B 0xc0 /* receive FIFO treshold = 14 */ |
| #define | UART_FCR_HSU_64B_FIFO 0x20 /* chose 64 bytes FIFO */ |
| #define | UART_FCR_HSU_16B_FIFO 0x00 /* chose 16 bytes FIFO */ |
| #define | UART_FCR_HALF_EMPT_TXI 0x00 /* trigger TX_EMPT IRQ for half empty */ |
| #define | UART_FCR_FULL_EMPT_TXI 0x08 /* trigger TX_EMPT IRQ for full empty */ |
| #define | UART_ASR 0x01 /* Additional Status Register */ |
| #define | UART_RFL 0x03 /* Receiver FIFO level */ |
| #define | UART_TFL 0x04 /* Transmitter FIFO level */ |
| #define | UART_ICR 0x05 /* Index Control Register */ |
| #define | UART_ACR 0x00 /* Additional Control Register */ |
| #define | UART_CPR 0x01 /* Clock Prescalar Register */ |
| #define | UART_TCR 0x02 /* Times Clock Register */ |
| #define | UART_CKS 0x03 /* Clock Select Register */ |
| #define | UART_TTL 0x04 /* Transmitter Interrupt Trigger Level */ |
| #define | UART_RTL 0x05 /* Receiver Interrupt Trigger Level */ |
| #define | UART_FCL 0x06 /* Flow Control Level Lower */ |
| #define | UART_FCH 0x07 /* Flow Control Level Higher */ |
| #define | UART_ID1 0x08 /* ID #1 */ |
| #define | UART_ID2 0x09 /* ID #2 */ |
| #define | UART_ID3 0x0A /* ID #3 */ |
| #define | UART_REV 0x0B /* Revision */ |
| #define | UART_CSR 0x0C /* Channel Software Reset */ |
| #define | UART_NMR 0x0D /* Nine-bit Mode Register */ |
| #define | UART_CTR 0xFF |
| #define | UART_ACR_RXDIS 0x01 /* Receiver disable */ |
| #define | UART_ACR_TXDIS 0x02 /* Transmitter disable */ |
| #define | UART_ACR_DSRFC 0x04 /* DSR Flow Control */ |
| #define | UART_ACR_TLENB 0x20 /* 950 trigger levels enable */ |
| #define | UART_ACR_ICRRD 0x40 /* ICR Read enable */ |
| #define | UART_ACR_ASREN 0x80 /* Additional status enable */ |
| #define | UART_RSA_BASE (-8) |
| #define | UART_RSA_MSR ((UART_RSA_BASE) + 0) /* I/O: Mode Select Register */ |
| #define | UART_RSA_MSR_SWAP (1 << 0) /* Swap low/high 8 bytes in I/O port addr */ |
| #define | UART_RSA_MSR_FIFO (1 << 2) /* Enable the external FIFO */ |
| #define | UART_RSA_MSR_FLOW (1 << 3) /* Enable the auto RTS/CTS flow control */ |
| #define | UART_RSA_MSR_ITYP (1 << 4) /* Level (1) / Edge triger (0) */ |
| #define | UART_RSA_IER ((UART_RSA_BASE) + 1) /* I/O: Interrupt Enable Register */ |
| #define | UART_RSA_IER_Rx_FIFO_H (1 << 0) /* Enable Rx FIFO half full int. */ |
| #define | UART_RSA_IER_Tx_FIFO_H (1 << 1) /* Enable Tx FIFO half full int. */ |
| #define | UART_RSA_IER_Tx_FIFO_E (1 << 2) /* Enable Tx FIFO empty int. */ |
| #define | UART_RSA_IER_Rx_TOUT (1 << 3) /* Enable char receive timeout int */ |
| #define | UART_RSA_IER_TIMER (1 << 4) /* Enable timer interrupt */ |
| #define | UART_RSA_SRR ((UART_RSA_BASE) + 2) /* IN: Status Read Register */ |
| #define | UART_RSA_SRR_Tx_FIFO_NEMP (1 << 0) /* Tx FIFO is not empty (1) */ |
| #define | UART_RSA_SRR_Tx_FIFO_NHFL (1 << 1) /* Tx FIFO is not half full (1) */ |
| #define | UART_RSA_SRR_Tx_FIFO_NFUL (1 << 2) /* Tx FIFO is not full (1) */ |
| #define | UART_RSA_SRR_Rx_FIFO_NEMP (1 << 3) /* Rx FIFO is not empty (1) */ |
| #define | UART_RSA_SRR_Rx_FIFO_NHFL (1 << 4) /* Rx FIFO is not half full (1) */ |
| #define | UART_RSA_SRR_Rx_FIFO_NFUL (1 << 5) /* Rx FIFO is not full (1) */ |
| #define | UART_RSA_SRR_Rx_TOUT (1 << 6) /* Character reception timeout occurred (1) */ |
| #define | UART_RSA_SRR_TIMER (1 << 7) /* Timer interrupt occurred */ |
| #define | UART_RSA_FRR ((UART_RSA_BASE) + 2) /* OUT: FIFO Reset Register */ |
| #define | UART_RSA_TIVSR ((UART_RSA_BASE) + 3) /* I/O: Timer Interval Value Set Register */ |
| #define | UART_RSA_TCR ((UART_RSA_BASE) + 4) /* OUT: Timer Control Register */ |
| #define | UART_RSA_TCR_SWITCH (1 << 0) /* Timer on */ |
| #define | SERIAL_RSA_BAUD_BASE (921600) |
| #define | SERIAL_RSA_BAUD_BASE_LO (SERIAL_RSA_BAUD_BASE / 8) |
| #define | UART_OMAP_MDR1 0x08 /* Mode definition register */ |
| #define | UART_OMAP_MDR2 0x09 /* Mode definition register 2 */ |
| #define | UART_OMAP_SCR 0x10 /* Supplementary control register */ |
| #define | UART_OMAP_SSR 0x11 /* Supplementary status register */ |
| #define | UART_OMAP_EBLR 0x12 /* BOF length register */ |
| #define | UART_OMAP_OSC_12M_SEL 0x13 /* OMAP1510 12MHz osc select */ |
| #define | UART_OMAP_MVER 0x14 /* Module version register */ |
| #define | UART_OMAP_SYSC 0x15 /* System configuration register */ |
| #define | UART_OMAP_SYSS 0x16 /* System status register */ |
| #define | UART_OMAP_WER 0x17 /* Wake-up enable register */ |
| #define | UART_OMAP_MDR1_16X_MODE 0x00 /* UART 16x mode */ |
| #define | UART_OMAP_MDR1_SIR_MODE 0x01 /* SIR mode */ |
| #define | UART_OMAP_MDR1_16X_ABAUD_MODE 0x02 /* UART 16x auto-baud */ |
| #define | UART_OMAP_MDR1_13X_MODE 0x03 /* UART 13x mode */ |
| #define | UART_OMAP_MDR1_MIR_MODE 0x04 /* MIR mode */ |
| #define | UART_OMAP_MDR1_FIR_MODE 0x05 /* FIR mode */ |
| #define | UART_OMAP_MDR1_CIR_MODE 0x06 /* CIR mode */ |
| #define | UART_OMAP_MDR1_DISABLE 0x07 /* Disable (default state) */ |
| #define SERIAL_RSA_BAUD_BASE (921600) |
Definition at line 338 of file serial_reg.h.
| #define SERIAL_RSA_BAUD_BASE_LO (SERIAL_RSA_BAUD_BASE / 8) |
Definition at line 339 of file serial_reg.h.
| #define UART_ACR 0x00 /* Additional Control Register */ |
Definition at line 264 of file serial_reg.h.
| #define UART_ACR_ASREN 0x80 /* Additional status enable */ |
Definition at line 288 of file serial_reg.h.
| #define UART_ACR_DSRFC 0x04 /* DSR Flow Control */ |
Definition at line 285 of file serial_reg.h.
| #define UART_ACR_ICRRD 0x40 /* ICR Read enable */ |
Definition at line 287 of file serial_reg.h.
| #define UART_ACR_RXDIS 0x01 /* Receiver disable */ |
Definition at line 283 of file serial_reg.h.
| #define UART_ACR_TLENB 0x20 /* 950 trigger levels enable */ |
Definition at line 286 of file serial_reg.h.
| #define UART_ACR_TXDIS 0x02 /* Transmitter disable */ |
Definition at line 284 of file serial_reg.h.
| #define UART_ASR 0x01 /* Additional Status Register */ |
Definition at line 258 of file serial_reg.h.
| #define UART_CKS 0x03 /* Clock Select Register */ |
Definition at line 267 of file serial_reg.h.
| #define UART_CPR 0x01 /* Clock Prescalar Register */ |
Definition at line 265 of file serial_reg.h.
| #define UART_CSR 0x0C /* Channel Software Reset */ |
Definition at line 276 of file serial_reg.h.
| #define UART_CTR 0xFF |
Definition at line 278 of file serial_reg.h.
| #define UART_DLL 0 /* Out: Divisor Latch Low */ |
Definition at line 152 of file serial_reg.h.
| #define UART_DLM 1 /* Out: Divisor Latch High */ |
Definition at line 153 of file serial_reg.h.
Definition at line 158 of file serial_reg.h.
| #define UART_EFR_CTS 0x80 /* CTS flow control */ |
Definition at line 160 of file serial_reg.h.
| #define UART_EFR_ECB 0x10 /* Enhanced control bit */ |
Definition at line 163 of file serial_reg.h.
| #define UART_EFR_RTS 0x40 /* RTS flow control */ |
Definition at line 161 of file serial_reg.h.
| #define UART_EFR_SCD 0x20 /* Special character detect */ |
Definition at line 162 of file serial_reg.h.
Definition at line 217 of file serial_reg.h.
| #define UART_EMSR_ALT_COUNT 0x02 /* Alternating count select */ |
Definition at line 219 of file serial_reg.h.
| #define UART_EMSR_FIFO_COUNT 0x01 /* Rx/Tx select */ |
Definition at line 218 of file serial_reg.h.
| #define UART_FCH 0x07 /* Flow Control Level Higher */ |
Definition at line 271 of file serial_reg.h.
| #define UART_FCL 0x06 /* Flow Control Level Lower */ |
Definition at line 270 of file serial_reg.h.
Definition at line 47 of file serial_reg.h.
| #define UART_FCR6_R_TRIGGER_16 0x40 /* Mask for receive trigger set at 4 */ |
Definition at line 82 of file serial_reg.h.
| #define UART_FCR6_R_TRIGGER_24 0x80 /* Mask for receive trigger set at 8 */ |
Definition at line 83 of file serial_reg.h.
| #define UART_FCR6_R_TRIGGER_28 0xC0 /* Mask for receive trigger set at 14 */ |
Definition at line 84 of file serial_reg.h.
| #define UART_FCR6_R_TRIGGER_8 0x00 /* Mask for receive trigger set at 1 */ |
Definition at line 81 of file serial_reg.h.
| #define UART_FCR6_T_TRIGGER_16 0x00 /* Mask for transmit trigger set at 16 */ |
Definition at line 85 of file serial_reg.h.
| #define UART_FCR6_T_TRIGGER_24 0x20 /* Mask for transmit trigger set at 24 */ |
Definition at line 87 of file serial_reg.h.
| #define UART_FCR6_T_TRIGGER_30 0x30 /* Mask for transmit trigger set at 30 */ |
Definition at line 88 of file serial_reg.h.
| #define UART_FCR6_T_TRIGGER_8 0x10 /* Mask for transmit trigger set at 8 */ |
Definition at line 86 of file serial_reg.h.
| #define UART_FCR7_64BYTE 0x20 /* Go into 64 byte mode (TI16C750) */ |
Definition at line 89 of file serial_reg.h.
| #define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */ |
Definition at line 49 of file serial_reg.h.
| #define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */ |
Definition at line 50 of file serial_reg.h.
| #define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */ |
Definition at line 51 of file serial_reg.h.
| #define UART_FCR_ENABLE_FIFO 0x01 /* Enable the FIFO */ |
Definition at line 48 of file serial_reg.h.
| #define UART_FCR_FULL_EMPT_TXI 0x08 /* trigger TX_EMPT IRQ for full empty */ |
Definition at line 253 of file serial_reg.h.
| #define UART_FCR_HALF_EMPT_TXI 0x00 /* trigger TX_EMPT IRQ for half empty */ |
Definition at line 252 of file serial_reg.h.
| #define UART_FCR_HSU_16_14B 0xc0 /* receive FIFO treshold = 14 */ |
Definition at line 247 of file serial_reg.h.
| #define UART_FCR_HSU_16_1B 0x00 /* receive FIFO treshold = 1 */ |
Definition at line 244 of file serial_reg.h.
| #define UART_FCR_HSU_16_4B 0x40 /* receive FIFO treshold = 4 */ |
Definition at line 245 of file serial_reg.h.
| #define UART_FCR_HSU_16_8B 0x80 /* receive FIFO treshold = 8 */ |
Definition at line 246 of file serial_reg.h.
| #define UART_FCR_HSU_16B_FIFO 0x00 /* chose 16 bytes FIFO */ |
Definition at line 250 of file serial_reg.h.
| #define UART_FCR_HSU_64_16B 0x40 /* receive FIFO treshold = 16 */ |
Definition at line 240 of file serial_reg.h.
| #define UART_FCR_HSU_64_1B 0x00 /* receive FIFO treshold = 1 */ |
Definition at line 239 of file serial_reg.h.
| #define UART_FCR_HSU_64_32B 0x80 /* receive FIFO treshold = 32 */ |
Definition at line 241 of file serial_reg.h.
| #define UART_FCR_HSU_64_56B 0xc0 /* receive FIFO treshold = 56 */ |
Definition at line 242 of file serial_reg.h.
| #define UART_FCR_HSU_64B_FIFO 0x20 /* chose 64 bytes FIFO */ |
Definition at line 249 of file serial_reg.h.
| #define UART_FCR_PXAR1 0x00 /* receive FIFO threshold = 1 */ |
Definition at line 231 of file serial_reg.h.
| #define UART_FCR_PXAR16 0x80 /* receive FIFO threshold = 16 */ |
Definition at line 233 of file serial_reg.h.
| #define UART_FCR_PXAR32 0xc0 /* receive FIFO threshold = 32 */ |
Definition at line 234 of file serial_reg.h.
| #define UART_FCR_PXAR8 0x40 /* receive FIFO threshold = 8 */ |
Definition at line 232 of file serial_reg.h.
| #define UART_FCR_R_TRIG_00 0x00 |
Definition at line 66 of file serial_reg.h.
| #define UART_FCR_R_TRIG_01 0x40 |
Definition at line 67 of file serial_reg.h.
| #define UART_FCR_R_TRIG_10 0x80 |
Definition at line 68 of file serial_reg.h.
| #define UART_FCR_R_TRIG_11 0xc0 |
Definition at line 69 of file serial_reg.h.
| #define UART_FCR_T_TRIG_00 0x00 |
Definition at line 70 of file serial_reg.h.
| #define UART_FCR_T_TRIG_01 0x10 |
Definition at line 71 of file serial_reg.h.
| #define UART_FCR_T_TRIG_10 0x20 |
Definition at line 72 of file serial_reg.h.
| #define UART_FCR_T_TRIG_11 0x30 |
Definition at line 73 of file serial_reg.h.
| #define UART_FCR_TRIGGER_1 0x00 /* Mask for trigger set at 1 */ |
Definition at line 76 of file serial_reg.h.
| #define UART_FCR_TRIGGER_14 0xC0 /* Mask for trigger set at 14 */ |
Definition at line 79 of file serial_reg.h.
| #define UART_FCR_TRIGGER_4 0x40 /* Mask for trigger set at 4 */ |
Definition at line 77 of file serial_reg.h.
| #define UART_FCR_TRIGGER_8 0x80 /* Mask for trigger set at 8 */ |
Definition at line 78 of file serial_reg.h.
| #define UART_FCR_TRIGGER_MASK 0xC0 /* Mask for the FIFO trigger range */ |
Definition at line 75 of file serial_reg.h.
Definition at line 199 of file serial_reg.h.
| #define UART_FCTR_IRDA 0x04 /* IrDa data encode select */ |
Definition at line 204 of file serial_reg.h.
| #define UART_FCTR_RTS_4DELAY 0x01 |
Definition at line 201 of file serial_reg.h.
| #define UART_FCTR_RTS_6DELAY 0x02 |
Definition at line 202 of file serial_reg.h.
| #define UART_FCTR_RTS_8DELAY 0x03 |
Definition at line 203 of file serial_reg.h.
| #define UART_FCTR_RTS_NODELAY 0x00 /* RTS flow control delay */ |
Definition at line 200 of file serial_reg.h.
| #define UART_FCTR_RX 0x00 /* Programmable trigger mode select */ |
Definition at line 211 of file serial_reg.h.
| #define UART_FCTR_SCR_SWAP 0x40 /* Scratch pad register swap */ |
Definition at line 210 of file serial_reg.h.
| #define UART_FCTR_TRGA 0x00 /* Tx/Rx 550 trigger table select */ |
Definition at line 206 of file serial_reg.h.
| #define UART_FCTR_TRGB 0x10 /* Tx/Rx 650 trigger table select */ |
Definition at line 207 of file serial_reg.h.
| #define UART_FCTR_TRGC 0x20 /* Tx/Rx 654 trigger table select */ |
Definition at line 208 of file serial_reg.h.
| #define UART_FCTR_TRGD 0x30 /* Tx/Rx 850 programmable trigger select */ |
Definition at line 209 of file serial_reg.h.
| #define UART_FCTR_TX 0x80 /* Programmable trigger mode select */ |
Definition at line 212 of file serial_reg.h.
| #define UART_FCTR_TX_INT 0x08 /* Tx interrupt type select */ |
Definition at line 205 of file serial_reg.h.
| #define UART_ICR 0x05 /* Index Control Register */ |
Definition at line 261 of file serial_reg.h.
| #define UART_ID1 0x08 /* ID #1 */ |
Definition at line 272 of file serial_reg.h.
| #define UART_ID2 0x09 /* ID #2 */ |
Definition at line 273 of file serial_reg.h.
| #define UART_ID3 0x0A /* ID #3 */ |
Definition at line 274 of file serial_reg.h.
| #define UART_IER 1 /* Out: Interrupt Enable Register */ |
Definition at line 23 of file serial_reg.h.
| #define UART_IER_DMAE 0x80 /* DMA Requests Enable */ |
Definition at line 224 of file serial_reg.h.
| #define UART_IER_MSI 0x08 /* Enable Modem status interrupt */ |
Definition at line 24 of file serial_reg.h.
| #define UART_IER_NRZE 0x20 /* NRZ coding Enable */ |
Definition at line 226 of file serial_reg.h.
| #define UART_IER_RDI 0x01 /* Enable receiver data interrupt */ |
Definition at line 27 of file serial_reg.h.
| #define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */ |
Definition at line 25 of file serial_reg.h.
| #define UART_IER_RTOIE 0x10 /* Receiver Time Out Interrupt Enable */ |
Definition at line 227 of file serial_reg.h.
| #define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */ |
Definition at line 26 of file serial_reg.h.
| #define UART_IER_UUE 0x40 /* UART Unit Enable */ |
Definition at line 225 of file serial_reg.h.
| #define UART_IERX_SLEEP 0x10 /* Enable sleep mode */ |
Definition at line 31 of file serial_reg.h.
Definition at line 33 of file serial_reg.h.
| #define UART_IIR_BUSY 0x07 /* DesignWare APB Busy Detect */ |
Definition at line 41 of file serial_reg.h.
| #define UART_IIR_CTS_RTS_DSR 0x20 /* OMAP CTS/RTS/DSR Change */ |
Definition at line 45 of file serial_reg.h.
| #define UART_IIR_ID 0x06 /* Mask for the interrupt ID */ |
Definition at line 35 of file serial_reg.h.
| #define UART_IIR_MSI 0x00 /* Modem status interrupt */ |
Definition at line 36 of file serial_reg.h.
| #define UART_IIR_NO_INT 0x01 /* No interrupts pending */ |
Definition at line 34 of file serial_reg.h.
| #define UART_IIR_RDI 0x04 /* Receiver data interrupt */ |
Definition at line 38 of file serial_reg.h.
| #define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */ |
Definition at line 39 of file serial_reg.h.
| #define UART_IIR_RX_TIMEOUT 0x0c /* OMAP RX Timeout interrupt */ |
Definition at line 43 of file serial_reg.h.
| #define UART_IIR_THRI 0x02 /* Transmitter holding register empty */ |
Definition at line 37 of file serial_reg.h.
| #define UART_IIR_TOD 0x08 /* Character Timeout Indication Detected */ |
Definition at line 229 of file serial_reg.h.
| #define UART_IIR_XOFF 0x10 /* OMAP XOFF/Special Character */ |
Definition at line 44 of file serial_reg.h.
Definition at line 91 of file serial_reg.h.
| #define UART_LCR_CONF_MODE_A UART_LCR_DLAB /* Configutation mode A */ |
Definition at line 111 of file serial_reg.h.
| #define UART_LCR_CONF_MODE_B 0xBF /* Configutation mode B */ |
Definition at line 112 of file serial_reg.h.
| #define UART_LCR_DLAB 0x80 /* Divisor latch access bit */ |
Definition at line 96 of file serial_reg.h.
| #define UART_LCR_EPAR 0x10 /* Even parity select */ |
Definition at line 99 of file serial_reg.h.
| #define UART_LCR_PARITY 0x08 /* Parity Enable */ |
Definition at line 100 of file serial_reg.h.
| #define UART_LCR_SBC 0x40 /* Set break control */ |
Definition at line 97 of file serial_reg.h.
| #define UART_LCR_SPAR 0x20 /* Stick parity (?) */ |
Definition at line 98 of file serial_reg.h.
| #define UART_LCR_STOP 0x04 /* Stop bits: 0=1 bit, 1=2 bits */ |
Definition at line 101 of file serial_reg.h.
| #define UART_LCR_WLEN5 0x00 /* Wordlength: 5 bits */ |
Definition at line 102 of file serial_reg.h.
| #define UART_LCR_WLEN6 0x01 /* Wordlength: 6 bits */ |
Definition at line 103 of file serial_reg.h.
| #define UART_LCR_WLEN7 0x02 /* Wordlength: 7 bits */ |
Definition at line 104 of file serial_reg.h.
| #define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */ |
Definition at line 105 of file serial_reg.h.
Definition at line 125 of file serial_reg.h.
| #define UART_LSR_BI 0x10 /* Break interrupt indicator */ |
Definition at line 129 of file serial_reg.h.
| #define UART_LSR_BRK_ERROR_BITS 0x1E /* BI, FE, PE, OE bits */ |
Definition at line 134 of file serial_reg.h.
| #define UART_LSR_DR 0x01 /* Receiver data ready */ |
Definition at line 133 of file serial_reg.h.
| #define UART_LSR_FE 0x08 /* Frame error indicator */ |
Definition at line 130 of file serial_reg.h.
| #define UART_LSR_FIFOE 0x80 /* Fifo error */ |
Definition at line 126 of file serial_reg.h.
| #define UART_LSR_OE 0x02 /* Overrun error indicator */ |
Definition at line 132 of file serial_reg.h.
| #define UART_LSR_PE 0x04 /* Parity error indicator */ |
Definition at line 131 of file serial_reg.h.
| #define UART_LSR_TEMT 0x40 /* Transmitter empty */ |
Definition at line 127 of file serial_reg.h.
| #define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */ |
Definition at line 128 of file serial_reg.h.
Definition at line 114 of file serial_reg.h.
| #define UART_MCR_AFE 0x20 /* Enable auto-RTS/CTS (TI16C550C/TI16C750) */ |
Definition at line 118 of file serial_reg.h.
| #define UART_MCR_CLKSEL 0x80 /* Divide clock by 4 (TI16C752, EFR[4]=1) */ |
Definition at line 115 of file serial_reg.h.
| #define UART_MCR_DTR 0x01 /* DTR complement */ |
Definition at line 123 of file serial_reg.h.
| #define UART_MCR_LOOP 0x10 /* Enable loopback test mode */ |
Definition at line 119 of file serial_reg.h.
| #define UART_MCR_OUT1 0x04 /* Out1 complement */ |
Definition at line 121 of file serial_reg.h.
| #define UART_MCR_OUT2 0x08 /* Out2 complement */ |
Definition at line 120 of file serial_reg.h.
| #define UART_MCR_RTS 0x02 /* RTS complement */ |
Definition at line 122 of file serial_reg.h.
| #define UART_MCR_TCRTLR 0x40 /* Access TCR/TLR (TI16C752, EFR[4]=1) */ |
Definition at line 116 of file serial_reg.h.
| #define UART_MCR_XONANY 0x20 /* Enable Xon Any (TI16C752, EFR[4]=1) */ |
Definition at line 117 of file serial_reg.h.
Definition at line 136 of file serial_reg.h.
| #define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */ |
Definition at line 145 of file serial_reg.h.
| #define UART_MSR_CTS 0x10 /* Clear to Send */ |
Definition at line 140 of file serial_reg.h.
| #define UART_MSR_DCD 0x80 /* Data Carrier Detect */ |
Definition at line 137 of file serial_reg.h.
| #define UART_MSR_DCTS 0x01 /* Delta CTS */ |
Definition at line 144 of file serial_reg.h.
| #define UART_MSR_DDCD 0x08 /* Delta DCD */ |
Definition at line 141 of file serial_reg.h.
| #define UART_MSR_DDSR 0x02 /* Delta DSR */ |
Definition at line 143 of file serial_reg.h.
| #define UART_MSR_DSR 0x20 /* Data Set Ready */ |
Definition at line 139 of file serial_reg.h.
| #define UART_MSR_RI 0x40 /* Ring Indicator */ |
Definition at line 138 of file serial_reg.h.
| #define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */ |
Definition at line 142 of file serial_reg.h.
| #define UART_NMR 0x0D /* Nine-bit Mode Register */ |
Definition at line 277 of file serial_reg.h.
| #define UART_OMAP_EBLR 0x12 /* BOF length register */ |
Definition at line 349 of file serial_reg.h.
| #define UART_OMAP_MDR1 0x08 /* Mode definition register */ |
Definition at line 345 of file serial_reg.h.
| #define UART_OMAP_MDR1_13X_MODE 0x03 /* UART 13x mode */ |
Definition at line 362 of file serial_reg.h.
| #define UART_OMAP_MDR1_16X_ABAUD_MODE 0x02 /* UART 16x auto-baud */ |
Definition at line 361 of file serial_reg.h.
| #define UART_OMAP_MDR1_16X_MODE 0x00 /* UART 16x mode */ |
Definition at line 359 of file serial_reg.h.
| #define UART_OMAP_MDR1_CIR_MODE 0x06 /* CIR mode */ |
Definition at line 365 of file serial_reg.h.
| #define UART_OMAP_MDR1_DISABLE 0x07 /* Disable (default state) */ |
Definition at line 366 of file serial_reg.h.
| #define UART_OMAP_MDR1_FIR_MODE 0x05 /* FIR mode */ |
Definition at line 364 of file serial_reg.h.
| #define UART_OMAP_MDR1_MIR_MODE 0x04 /* MIR mode */ |
Definition at line 363 of file serial_reg.h.
| #define UART_OMAP_MDR1_SIR_MODE 0x01 /* SIR mode */ |
Definition at line 360 of file serial_reg.h.
| #define UART_OMAP_MDR2 0x09 /* Mode definition register 2 */ |
Definition at line 346 of file serial_reg.h.
| #define UART_OMAP_MVER 0x14 /* Module version register */ |
Definition at line 351 of file serial_reg.h.
| #define UART_OMAP_OSC_12M_SEL 0x13 /* OMAP1510 12MHz osc select */ |
Definition at line 350 of file serial_reg.h.
| #define UART_OMAP_SCR 0x10 /* Supplementary control register */ |
Definition at line 347 of file serial_reg.h.
| #define UART_OMAP_SSR 0x11 /* Supplementary status register */ |
Definition at line 348 of file serial_reg.h.
| #define UART_OMAP_SYSC 0x15 /* System configuration register */ |
Definition at line 352 of file serial_reg.h.
| #define UART_OMAP_SYSS 0x16 /* System status register */ |
Definition at line 353 of file serial_reg.h.
| #define UART_OMAP_WER 0x17 /* Wake-up enable register */ |
Definition at line 354 of file serial_reg.h.
| #define UART_REV 0x0B /* Revision */ |
Definition at line 275 of file serial_reg.h.
| #define UART_RFL 0x03 /* Receiver FIFO level */ |
Definition at line 259 of file serial_reg.h.
| #define UART_RSA_BASE (-8) |
Definition at line 298 of file serial_reg.h.
| #define UART_RSA_FRR ((UART_RSA_BASE) + 2) /* OUT: FIFO Reset Register */ |
Definition at line 326 of file serial_reg.h.
| #define UART_RSA_IER ((UART_RSA_BASE) + 1) /* I/O: Interrupt Enable Register */ |
Definition at line 307 of file serial_reg.h.
Definition at line 309 of file serial_reg.h.
Definition at line 312 of file serial_reg.h.
Definition at line 313 of file serial_reg.h.
Definition at line 311 of file serial_reg.h.
Definition at line 310 of file serial_reg.h.
| #define UART_RSA_MSR ((UART_RSA_BASE) + 0) /* I/O: Mode Select Register */ |
Definition at line 300 of file serial_reg.h.
Definition at line 303 of file serial_reg.h.
Definition at line 304 of file serial_reg.h.
| #define UART_RSA_MSR_ITYP (1 << 4) /* Level (1) / Edge triger (0) */ |
Definition at line 305 of file serial_reg.h.
Definition at line 302 of file serial_reg.h.
| #define UART_RSA_SRR ((UART_RSA_BASE) + 2) /* IN: Status Read Register */ |
Definition at line 315 of file serial_reg.h.
Definition at line 320 of file serial_reg.h.
Definition at line 322 of file serial_reg.h.
Definition at line 321 of file serial_reg.h.
| #define UART_RSA_SRR_Rx_TOUT (1 << 6) /* Character reception timeout occurred (1) */ |
Definition at line 323 of file serial_reg.h.
Definition at line 324 of file serial_reg.h.
Definition at line 317 of file serial_reg.h.
Definition at line 319 of file serial_reg.h.
Definition at line 318 of file serial_reg.h.
| #define UART_RSA_TCR ((UART_RSA_BASE) + 4) /* OUT: Timer Control Register */ |
Definition at line 330 of file serial_reg.h.
| #define UART_RSA_TCR_SWITCH (1 << 0) /* Timer on */ |
Definition at line 332 of file serial_reg.h.
| #define UART_RSA_TIVSR ((UART_RSA_BASE) + 3) /* I/O: Timer Interval Value Set Register */ |
Definition at line 328 of file serial_reg.h.
| #define UART_RTL 0x05 /* Receiver Interrupt Trigger Level */ |
Definition at line 269 of file serial_reg.h.
| #define UART_RX 0 /* In: Receive buffer */ |
Definition at line 20 of file serial_reg.h.
Definition at line 147 of file serial_reg.h.
| #define UART_TCR 0x02 /* Times Clock Register */ |
Definition at line 266 of file serial_reg.h.
| #define UART_TFL 0x04 /* Transmitter FIFO level */ |
Definition at line 260 of file serial_reg.h.
Definition at line 179 of file serial_reg.h.
Definition at line 180 of file serial_reg.h.
| #define UART_TRG |
Definition at line 185 of file serial_reg.h.
| #define UART_TRG_1 0x01 |
Definition at line 189 of file serial_reg.h.
| #define UART_TRG_120 0x78 |
Definition at line 196 of file serial_reg.h.
| #define UART_TRG_128 0x80 |
Definition at line 197 of file serial_reg.h.
| #define UART_TRG_16 0x10 |
Definition at line 192 of file serial_reg.h.
| #define UART_TRG_32 0x20 |
Definition at line 193 of file serial_reg.h.
| #define UART_TRG_4 0x04 |
Definition at line 190 of file serial_reg.h.
| #define UART_TRG_64 0x40 |
Definition at line 194 of file serial_reg.h.
| #define UART_TRG_8 0x08 |
Definition at line 191 of file serial_reg.h.
| #define UART_TRG_96 0x60 |
Definition at line 195 of file serial_reg.h.
| #define UART_TTL 0x04 /* Transmitter Interrupt Trigger Level */ |
Definition at line 268 of file serial_reg.h.
Definition at line 21 of file serial_reg.h.
Definition at line 173 of file serial_reg.h.
Definition at line 174 of file serial_reg.h.
Definition at line 171 of file serial_reg.h.
Definition at line 172 of file serial_reg.h.
Definition at line 159 of file serial_reg.h.
1.8.2