#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/mbus.h>
#include <asm/mach/pci.h>
#include <plat/pcie.h>
#include <plat/addr-map.h>
#include <linux/delay.h>
Go to the source code of this file.
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| u32 | orion_pcie_dev_id (void __iomem *base) |
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| u32 | orion_pcie_rev (void __iomem *base) |
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| int | orion_pcie_link_up (void __iomem *base) |
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| int __init | orion_pcie_x4_mode (void __iomem *base) |
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| int | orion_pcie_get_local_bus_nr (void __iomem *base) |
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| void __init | orion_pcie_set_local_bus_nr (void __iomem *base, int nr) |
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| void __init | orion_pcie_reset (void __iomem *base) |
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| void __init | orion_pcie_setup (void __iomem *base) |
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| int | orion_pcie_rd_conf (void __iomem *base, struct pci_bus *bus, u32 devfn, int where, int size, u32 *val) |
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| int | orion_pcie_rd_conf_tlp (void __iomem *base, struct pci_bus *bus, u32 devfn, int where, int size, u32 *val) |
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| int | orion_pcie_rd_conf_wa (void __iomem *wa_base, struct pci_bus *bus, u32 devfn, int where, int size, u32 *val) |
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| int | orion_pcie_wr_conf (void __iomem *base, struct pci_bus *bus, u32 devfn, int where, int size, u32 val) |
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| #define PCIE_BAR_CTRL_OFF |
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n | ) |
(0x1804 + ((n - 1) * 4)) |
| #define PCIE_BAR_HI_OFF |
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n | ) |
(0x0014 + ((n) << 3)) |
| #define PCIE_BAR_LO_OFF |
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n | ) |
(0x0010 + ((n) << 3)) |
| #define PCIE_CMD_OFF 0x0004 |
| #define PCIE_CONF_ADDR_EN 0x80000000 |
| #define PCIE_CONF_ADDR_OFF 0x18f8 |
| #define PCIE_CONF_BUS |
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b | ) |
(((b) & 0xff) << 16) |
| #define PCIE_CONF_DATA_OFF 0x18fc |
| #define PCIE_CONF_DEV |
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d | ) |
(((d) & 0x1f) << 11) |
| #define PCIE_CONF_FUNC |
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f | ) |
(((f) & 0x7) << 8) |
| #define PCIE_CONF_REG |
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r | ) |
((((r) & 0xf00) << 16) | ((r) & 0xfc)) |
| #define PCIE_CTRL_OFF 0x1a00 |
| #define PCIE_CTRL_X1_MODE 0x0001 |
| #define PCIE_DEBUG_CTRL 0x1a60 |
| #define PCIE_DEBUG_SOFT_RESET (1<<20) |
| #define PCIE_DEV_ID_OFF 0x0000 |
| #define PCIE_DEV_REV_OFF 0x0008 |
| #define PCIE_HEADER_LOG_4_OFF 0x0128 |
| #define PCIE_MASK_OFF 0x1910 |
| #define PCIE_STAT_BUS_MASK 0xff |
| #define PCIE_STAT_BUS_OFFS 8 |
| #define PCIE_STAT_DEV_MASK 0x1f |
| #define PCIE_STAT_DEV_OFFS 20 |
| #define PCIE_STAT_LINK_DOWN 1 |
| #define PCIE_STAT_OFF 0x1a04 |
| #define PCIE_WIN04_BASE_OFF |
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n | ) |
(0x1824 + ((n) << 4)) |
| #define PCIE_WIN04_CTRL_OFF |
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n | ) |
(0x1820 + ((n) << 4)) |
| #define PCIE_WIN04_REMAP_OFF |
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n | ) |
(0x182c + ((n) << 4)) |
| #define PCIE_WIN5_BASE_OFF 0x1884 |
| #define PCIE_WIN5_CTRL_OFF 0x1880 |
| #define PCIE_WIN5_REMAP_OFF 0x188c |