irq.h File Reference

#include <linux/irqdomain.h>
#include <linux/threads.h>
#include <linux/list.h>
#include <linux/radix-tree.h>
#include <asm/percpu.h>

Go to the source code of this file.

Macros
#define	irq_canonicalize(irq)   (irq)
#define	NR_PRIORITY_IRQS   16
#define	NR_IRQS   256
#define	NO_IRQ   0

Functions
void __init	init_pic_c64xplus (void)
void	init_IRQ (void)
asmlinkage void	c6x_do_IRQ (unsigned int prio, struct pt_regs *regs)

Variables
unsigned long	irq_err_count

Macro Definition Documentation

#define irq_canonicalize

(

irq

)

(irq)

Definition at line 22 of file irq.h.

#define NO_IRQ   0

Definition at line 41 of file irq.h.

#define NR_IRQS   256

Definition at line 38 of file irq.h.

#define NR_PRIORITY_IRQS   16

Definition at line 35 of file irq.h.

Function Documentation

asmlinkage void c6x_do_IRQ	(	unsigned int	prio,
		struct pt_regs *	regs
	)

Definition at line 62 of file irq.c.

void init_IRQ

(

void

)

The hexagon core comes with a first-level interrupt controller with 32 total possible interrupts. When the core is embedded into different systems/platforms, it is typically wrapped by macro cells that provide one or more second-level interrupt controllers that are cascaded into one or more of the first-level interrupts handled here. The precise wiring of these other irqs varies from platform to platform, and are set up & configured in the platform-specific files.

The first-level interrupt controller is wrapped by the VM, which virtualizes the interrupt controller for us. It provides a very simple, fast & efficient API, and so the fasteoi handler is appropriate for this case.

Definition at line 109 of file irq_alpha.c.

void __init init_pic_c64xplus

(

void

)

Variable Documentation

unsigned long irq_err_count

Definition at line 32 of file irq.c.