Data Structures
struct	reg_iop_sw_cfg_rw_crc_par0_owner

struct	reg_iop_sw_cfg_rw_crc_par1_owner

struct	reg_iop_sw_cfg_rw_dmc_in0_owner

struct	reg_iop_sw_cfg_rw_dmc_in1_owner

struct	reg_iop_sw_cfg_rw_dmc_out0_owner

struct	reg_iop_sw_cfg_rw_dmc_out1_owner

struct	reg_iop_sw_cfg_rw_fifo_in0_owner

struct	reg_iop_sw_cfg_rw_fifo_in0_extra_owner

struct	reg_iop_sw_cfg_rw_fifo_in1_owner

struct	reg_iop_sw_cfg_rw_fifo_in1_extra_owner

struct	reg_iop_sw_cfg_rw_fifo_out0_owner

struct	reg_iop_sw_cfg_rw_fifo_out0_extra_owner

struct	reg_iop_sw_cfg_rw_fifo_out1_owner

struct	reg_iop_sw_cfg_rw_fifo_out1_extra_owner

struct	reg_iop_sw_cfg_rw_sap_in_owner

struct	reg_iop_sw_cfg_rw_sap_out_owner

struct	reg_iop_sw_cfg_rw_scrc_in0_owner

struct	reg_iop_sw_cfg_rw_scrc_in1_owner

struct	reg_iop_sw_cfg_rw_scrc_out0_owner

struct	reg_iop_sw_cfg_rw_scrc_out1_owner

struct	reg_iop_sw_cfg_rw_spu0_owner

struct	reg_iop_sw_cfg_rw_spu1_owner

struct	reg_iop_sw_cfg_rw_timer_grp0_owner

struct	reg_iop_sw_cfg_rw_timer_grp1_owner

struct	reg_iop_sw_cfg_rw_timer_grp2_owner

struct	reg_iop_sw_cfg_rw_timer_grp3_owner

struct	reg_iop_sw_cfg_rw_trigger_grp0_owner

struct	reg_iop_sw_cfg_rw_trigger_grp1_owner

struct	reg_iop_sw_cfg_rw_trigger_grp2_owner

struct	reg_iop_sw_cfg_rw_trigger_grp3_owner

struct	reg_iop_sw_cfg_rw_trigger_grp4_owner

struct	reg_iop_sw_cfg_rw_trigger_grp5_owner

struct	reg_iop_sw_cfg_rw_trigger_grp6_owner

struct	reg_iop_sw_cfg_rw_trigger_grp7_owner

struct	reg_iop_sw_cfg_rw_bus0_mask

struct	reg_iop_sw_cfg_rw_bus0_oe_mask

struct	reg_iop_sw_cfg_rw_bus1_mask

struct	reg_iop_sw_cfg_rw_bus1_oe_mask

struct	reg_iop_sw_cfg_rw_gio_mask

struct	reg_iop_sw_cfg_rw_gio_oe_mask

struct	reg_iop_sw_cfg_rw_pinmapping

struct	reg_iop_sw_cfg_rw_bus_out_cfg

struct	reg_iop_sw_cfg_rw_gio_out_grp0_cfg

struct	reg_iop_sw_cfg_rw_gio_out_grp1_cfg

struct	reg_iop_sw_cfg_rw_gio_out_grp2_cfg

struct	reg_iop_sw_cfg_rw_gio_out_grp3_cfg

struct	reg_iop_sw_cfg_rw_gio_out_grp4_cfg

struct	reg_iop_sw_cfg_rw_gio_out_grp5_cfg

struct	reg_iop_sw_cfg_rw_gio_out_grp6_cfg

struct	reg_iop_sw_cfg_rw_gio_out_grp7_cfg

struct	reg_iop_sw_cfg_rw_spu0_cfg

struct	reg_iop_sw_cfg_rw_spu1_cfg

struct	reg_iop_sw_cfg_rw_timer_grp0_cfg

struct	reg_iop_sw_cfg_rw_timer_grp1_cfg

struct	reg_iop_sw_cfg_rw_timer_grp2_cfg

struct	reg_iop_sw_cfg_rw_timer_grp3_cfg

struct	reg_iop_sw_cfg_rw_trigger_grps_cfg

struct	reg_iop_sw_cfg_rw_pdp0_cfg

struct	reg_iop_sw_cfg_rw_pdp1_cfg

struct	reg_iop_sw_cfg_rw_sdp_cfg

Macros
#define	REG_RD(scope, inst, reg)

#define	REG_WR(scope, inst, reg, val)

#define	REG_RD_VECT(scope, inst, reg, index)

#define	REG_WR_VECT(scope, inst, reg, index, val)

#define	REG_RD_INT(scope, inst, reg) REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )

#define	REG_WR_INT(scope, inst, reg, val) REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )

#define	REG_RD_INT_VECT(scope, inst, reg, index)

#define	REG_WR_INT_VECT(scope, inst, reg, index, val)

#define	REG_TYPE_CONV(type, orgtype, val) ( { union { orgtype o; type n; } r; r.o = val; r.n; } )

#define	reg_page_size 8192

#define	REG_ADDR(scope, inst, reg) ( (inst) + REG_RD_ADDR_##scope##_##reg )

#define	REG_ADDR_VECT(scope, inst, reg, index)

#define	REG_RD_ADDR_iop_sw_cfg_rw_crc_par0_owner 0

#define	REG_WR_ADDR_iop_sw_cfg_rw_crc_par0_owner 0

#define	REG_RD_ADDR_iop_sw_cfg_rw_crc_par1_owner 4

#define	REG_WR_ADDR_iop_sw_cfg_rw_crc_par1_owner 4

#define	REG_RD_ADDR_iop_sw_cfg_rw_dmc_in0_owner 8

#define	REG_WR_ADDR_iop_sw_cfg_rw_dmc_in0_owner 8

#define	REG_RD_ADDR_iop_sw_cfg_rw_dmc_in1_owner 12

#define	REG_WR_ADDR_iop_sw_cfg_rw_dmc_in1_owner 12

#define	REG_RD_ADDR_iop_sw_cfg_rw_dmc_out0_owner 16

#define	REG_WR_ADDR_iop_sw_cfg_rw_dmc_out0_owner 16

#define	REG_RD_ADDR_iop_sw_cfg_rw_dmc_out1_owner 20

#define	REG_WR_ADDR_iop_sw_cfg_rw_dmc_out1_owner 20

#define	REG_RD_ADDR_iop_sw_cfg_rw_fifo_in0_owner 24

#define	REG_WR_ADDR_iop_sw_cfg_rw_fifo_in0_owner 24

#define	REG_RD_ADDR_iop_sw_cfg_rw_fifo_in0_extra_owner 28

#define	REG_WR_ADDR_iop_sw_cfg_rw_fifo_in0_extra_owner 28

#define	REG_RD_ADDR_iop_sw_cfg_rw_fifo_in1_owner 32

#define	REG_WR_ADDR_iop_sw_cfg_rw_fifo_in1_owner 32

#define	REG_RD_ADDR_iop_sw_cfg_rw_fifo_in1_extra_owner 36

#define	REG_WR_ADDR_iop_sw_cfg_rw_fifo_in1_extra_owner 36

#define	REG_RD_ADDR_iop_sw_cfg_rw_fifo_out0_owner 40

#define	REG_WR_ADDR_iop_sw_cfg_rw_fifo_out0_owner 40

#define	REG_RD_ADDR_iop_sw_cfg_rw_fifo_out0_extra_owner 44

#define	REG_WR_ADDR_iop_sw_cfg_rw_fifo_out0_extra_owner 44

#define	REG_RD_ADDR_iop_sw_cfg_rw_fifo_out1_owner 48

#define	REG_WR_ADDR_iop_sw_cfg_rw_fifo_out1_owner 48

#define	REG_RD_ADDR_iop_sw_cfg_rw_fifo_out1_extra_owner 52

#define	REG_WR_ADDR_iop_sw_cfg_rw_fifo_out1_extra_owner 52

#define	REG_RD_ADDR_iop_sw_cfg_rw_sap_in_owner 56

#define	REG_WR_ADDR_iop_sw_cfg_rw_sap_in_owner 56

#define	REG_RD_ADDR_iop_sw_cfg_rw_sap_out_owner 60

#define	REG_WR_ADDR_iop_sw_cfg_rw_sap_out_owner 60

#define	REG_RD_ADDR_iop_sw_cfg_rw_scrc_in0_owner 64

#define	REG_WR_ADDR_iop_sw_cfg_rw_scrc_in0_owner 64

#define	REG_RD_ADDR_iop_sw_cfg_rw_scrc_in1_owner 68

#define	REG_WR_ADDR_iop_sw_cfg_rw_scrc_in1_owner 68

#define	REG_RD_ADDR_iop_sw_cfg_rw_scrc_out0_owner 72

#define	REG_WR_ADDR_iop_sw_cfg_rw_scrc_out0_owner 72

#define	REG_RD_ADDR_iop_sw_cfg_rw_scrc_out1_owner 76

#define	REG_WR_ADDR_iop_sw_cfg_rw_scrc_out1_owner 76

#define	REG_RD_ADDR_iop_sw_cfg_rw_spu0_owner 80

#define	REG_WR_ADDR_iop_sw_cfg_rw_spu0_owner 80

#define	REG_RD_ADDR_iop_sw_cfg_rw_spu1_owner 84

#define	REG_WR_ADDR_iop_sw_cfg_rw_spu1_owner 84

#define	REG_RD_ADDR_iop_sw_cfg_rw_timer_grp0_owner 88

#define	REG_WR_ADDR_iop_sw_cfg_rw_timer_grp0_owner 88

#define	REG_RD_ADDR_iop_sw_cfg_rw_timer_grp1_owner 92

#define	REG_WR_ADDR_iop_sw_cfg_rw_timer_grp1_owner 92

#define	REG_RD_ADDR_iop_sw_cfg_rw_timer_grp2_owner 96

#define	REG_WR_ADDR_iop_sw_cfg_rw_timer_grp2_owner 96

#define	REG_RD_ADDR_iop_sw_cfg_rw_timer_grp3_owner 100

#define	REG_WR_ADDR_iop_sw_cfg_rw_timer_grp3_owner 100

#define	REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp0_owner 104

#define	REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp0_owner 104

#define	REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp1_owner 108

#define	REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp1_owner 108

#define	REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp2_owner 112

#define	REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp2_owner 112

#define	REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp3_owner 116

#define	REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp3_owner 116

#define	REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp4_owner 120

#define	REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp4_owner 120

#define	REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp5_owner 124

#define	REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp5_owner 124

#define	REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp6_owner 128

#define	REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp6_owner 128

#define	REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp7_owner 132

#define	REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp7_owner 132

#define	REG_RD_ADDR_iop_sw_cfg_rw_bus0_mask 136

#define	REG_WR_ADDR_iop_sw_cfg_rw_bus0_mask 136

#define	REG_RD_ADDR_iop_sw_cfg_rw_bus0_oe_mask 140

#define	REG_WR_ADDR_iop_sw_cfg_rw_bus0_oe_mask 140

#define	REG_RD_ADDR_iop_sw_cfg_rw_bus1_mask 144

#define	REG_WR_ADDR_iop_sw_cfg_rw_bus1_mask 144

#define	REG_RD_ADDR_iop_sw_cfg_rw_bus1_oe_mask 148

#define	REG_WR_ADDR_iop_sw_cfg_rw_bus1_oe_mask 148

#define	REG_RD_ADDR_iop_sw_cfg_rw_gio_mask 152

#define	REG_WR_ADDR_iop_sw_cfg_rw_gio_mask 152

#define	REG_RD_ADDR_iop_sw_cfg_rw_gio_oe_mask 156

#define	REG_WR_ADDR_iop_sw_cfg_rw_gio_oe_mask 156

#define	REG_RD_ADDR_iop_sw_cfg_rw_pinmapping 160

#define	REG_WR_ADDR_iop_sw_cfg_rw_pinmapping 160

#define	REG_RD_ADDR_iop_sw_cfg_rw_bus_out_cfg 164

#define	REG_WR_ADDR_iop_sw_cfg_rw_bus_out_cfg 164

#define	REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp0_cfg 168

#define	REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp0_cfg 168

#define	REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp1_cfg 172

#define	REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp1_cfg 172

#define	REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp2_cfg 176

#define	REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp2_cfg 176

#define	REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp3_cfg 180

#define	REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp3_cfg 180

#define	REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp4_cfg 184

#define	REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp4_cfg 184

#define	REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp5_cfg 188

#define	REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp5_cfg 188

#define	REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp6_cfg 192

#define	REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp6_cfg 192

#define	REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp7_cfg 196

#define	REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp7_cfg 196

#define	REG_RD_ADDR_iop_sw_cfg_rw_spu0_cfg 200

#define	REG_WR_ADDR_iop_sw_cfg_rw_spu0_cfg 200

#define	REG_RD_ADDR_iop_sw_cfg_rw_spu1_cfg 204

#define	REG_WR_ADDR_iop_sw_cfg_rw_spu1_cfg 204

#define	REG_RD_ADDR_iop_sw_cfg_rw_timer_grp0_cfg 208

#define	REG_WR_ADDR_iop_sw_cfg_rw_timer_grp0_cfg 208

#define	REG_RD_ADDR_iop_sw_cfg_rw_timer_grp1_cfg 212

#define	REG_WR_ADDR_iop_sw_cfg_rw_timer_grp1_cfg 212

#define	REG_RD_ADDR_iop_sw_cfg_rw_timer_grp2_cfg 216

#define	REG_WR_ADDR_iop_sw_cfg_rw_timer_grp2_cfg 216

#define	REG_RD_ADDR_iop_sw_cfg_rw_timer_grp3_cfg 220

#define	REG_WR_ADDR_iop_sw_cfg_rw_timer_grp3_cfg 220

#define	REG_RD_ADDR_iop_sw_cfg_rw_trigger_grps_cfg 224

#define	REG_WR_ADDR_iop_sw_cfg_rw_trigger_grps_cfg 224

#define	REG_RD_ADDR_iop_sw_cfg_rw_pdp0_cfg 228

#define	REG_WR_ADDR_iop_sw_cfg_rw_pdp0_cfg 228

#define	REG_RD_ADDR_iop_sw_cfg_rw_pdp1_cfg 232

#define	REG_WR_ADDR_iop_sw_cfg_rw_pdp1_cfg 232

#define	REG_RD_ADDR_iop_sw_cfg_rw_sdp_cfg 236

#define	REG_WR_ADDR_iop_sw_cfg_rw_sdp_cfg 236

Enumerations
enum	{ regk_iop_sw_cfg_a = 0x00000001, regk_iop_sw_cfg_b = 0x00000002, regk_iop_sw_cfg_bus0 = 0x00000000, regk_iop_sw_cfg_bus0_rot16 = 0x00000004, regk_iop_sw_cfg_bus0_rot24 = 0x00000006, regk_iop_sw_cfg_bus0_rot8 = 0x00000002, regk_iop_sw_cfg_bus1 = 0x00000001, regk_iop_sw_cfg_bus1_rot16 = 0x00000005, regk_iop_sw_cfg_bus1_rot24 = 0x00000007, regk_iop_sw_cfg_bus1_rot8 = 0x00000003, regk_iop_sw_cfg_clk12 = 0x00000000, regk_iop_sw_cfg_cpu = 0x00000000, regk_iop_sw_cfg_dmc0 = 0x00000000, regk_iop_sw_cfg_dmc1 = 0x00000001, regk_iop_sw_cfg_gated_clk0 = 0x00000010, regk_iop_sw_cfg_gated_clk1 = 0x00000011, regk_iop_sw_cfg_gated_clk2 = 0x00000012, regk_iop_sw_cfg_gated_clk3 = 0x00000013, regk_iop_sw_cfg_gio0 = 0x00000004, regk_iop_sw_cfg_gio1 = 0x00000001, regk_iop_sw_cfg_gio2 = 0x00000005, regk_iop_sw_cfg_gio3 = 0x00000002, regk_iop_sw_cfg_gio4 = 0x00000006, regk_iop_sw_cfg_gio5 = 0x00000003, regk_iop_sw_cfg_gio6 = 0x00000007, regk_iop_sw_cfg_gio7 = 0x00000004, regk_iop_sw_cfg_gio_in0 = 0x00000000, regk_iop_sw_cfg_gio_in1 = 0x00000001, regk_iop_sw_cfg_gio_in10 = 0x00000002, regk_iop_sw_cfg_gio_in11 = 0x00000003, regk_iop_sw_cfg_gio_in14 = 0x00000004, regk_iop_sw_cfg_gio_in15 = 0x00000005, regk_iop_sw_cfg_gio_in18 = 0x00000002, regk_iop_sw_cfg_gio_in19 = 0x00000003, regk_iop_sw_cfg_gio_in20 = 0x00000004, regk_iop_sw_cfg_gio_in21 = 0x00000005, regk_iop_sw_cfg_gio_in26 = 0x00000006, regk_iop_sw_cfg_gio_in27 = 0x00000007, regk_iop_sw_cfg_gio_in28 = 0x00000006, regk_iop_sw_cfg_gio_in29 = 0x00000007, regk_iop_sw_cfg_gio_in4 = 0x00000000, regk_iop_sw_cfg_gio_in5 = 0x00000001, regk_iop_sw_cfg_last_timer_grp0_tmr2 = 0x00000001, regk_iop_sw_cfg_last_timer_grp1_tmr2 = 0x00000001, regk_iop_sw_cfg_last_timer_grp2_tmr2 = 0x00000002, regk_iop_sw_cfg_last_timer_grp2_tmr3 = 0x00000003, regk_iop_sw_cfg_last_timer_grp3_tmr2 = 0x00000002, regk_iop_sw_cfg_last_timer_grp3_tmr3 = 0x00000003, regk_iop_sw_cfg_mpu = 0x00000001, regk_iop_sw_cfg_none = 0x00000000, regk_iop_sw_cfg_par0 = 0x00000000, regk_iop_sw_cfg_par1 = 0x00000001, regk_iop_sw_cfg_pdp_out0 = 0x00000002, regk_iop_sw_cfg_pdp_out0_hi = 0x00000001, regk_iop_sw_cfg_pdp_out0_hi_rot8 = 0x00000005, regk_iop_sw_cfg_pdp_out0_lo = 0x00000000, regk_iop_sw_cfg_pdp_out0_lo_rot8 = 0x00000004, regk_iop_sw_cfg_pdp_out1 = 0x00000003, regk_iop_sw_cfg_pdp_out1_hi = 0x00000003, regk_iop_sw_cfg_pdp_out1_hi_rot8 = 0x00000005, regk_iop_sw_cfg_pdp_out1_lo = 0x00000002, regk_iop_sw_cfg_pdp_out1_lo_rot8 = 0x00000004, regk_iop_sw_cfg_rw_bus0_mask_default = 0x00000000, regk_iop_sw_cfg_rw_bus0_oe_mask_default = 0x00000000, regk_iop_sw_cfg_rw_bus1_mask_default = 0x00000000, regk_iop_sw_cfg_rw_bus1_oe_mask_default = 0x00000000, regk_iop_sw_cfg_rw_bus_out_cfg_default = 0x00000000, regk_iop_sw_cfg_rw_crc_par0_owner_default = 0x00000000, regk_iop_sw_cfg_rw_crc_par1_owner_default = 0x00000000, regk_iop_sw_cfg_rw_dmc_in0_owner_default = 0x00000000, regk_iop_sw_cfg_rw_dmc_in1_owner_default = 0x00000000, regk_iop_sw_cfg_rw_dmc_out0_owner_default = 0x00000000, regk_iop_sw_cfg_rw_dmc_out1_owner_default = 0x00000000, regk_iop_sw_cfg_rw_fifo_in0_extra_owner_default = 0x00000000, regk_iop_sw_cfg_rw_fifo_in0_owner_default = 0x00000000, regk_iop_sw_cfg_rw_fifo_in1_extra_owner_default = 0x00000000, regk_iop_sw_cfg_rw_fifo_in1_owner_default = 0x00000000, regk_iop_sw_cfg_rw_fifo_out0_extra_owner_default = 0x00000000, regk_iop_sw_cfg_rw_fifo_out0_owner_default = 0x00000000, regk_iop_sw_cfg_rw_fifo_out1_extra_owner_default = 0x00000000, regk_iop_sw_cfg_rw_fifo_out1_owner_default = 0x00000000, regk_iop_sw_cfg_rw_gio_mask_default = 0x00000000, regk_iop_sw_cfg_rw_gio_oe_mask_default = 0x00000000, regk_iop_sw_cfg_rw_gio_out_grp0_cfg_default = 0x00000000, regk_iop_sw_cfg_rw_gio_out_grp1_cfg_default = 0x00000000, regk_iop_sw_cfg_rw_gio_out_grp2_cfg_default = 0x00000000, regk_iop_sw_cfg_rw_gio_out_grp3_cfg_default = 0x00000000, regk_iop_sw_cfg_rw_gio_out_grp4_cfg_default = 0x00000000, regk_iop_sw_cfg_rw_gio_out_grp5_cfg_default = 0x00000000, regk_iop_sw_cfg_rw_gio_out_grp6_cfg_default = 0x00000000, regk_iop_sw_cfg_rw_gio_out_grp7_cfg_default = 0x00000000, regk_iop_sw_cfg_rw_pdp0_cfg_default = 0x00000000, regk_iop_sw_cfg_rw_pdp1_cfg_default = 0x00000000, regk_iop_sw_cfg_rw_pinmapping_default = 0x55555555, regk_iop_sw_cfg_rw_sap_in_owner_default = 0x00000000, regk_iop_sw_cfg_rw_sap_out_owner_default = 0x00000000, regk_iop_sw_cfg_rw_scrc_in0_owner_default = 0x00000000, regk_iop_sw_cfg_rw_scrc_in1_owner_default = 0x00000000, regk_iop_sw_cfg_rw_scrc_out0_owner_default = 0x00000000, regk_iop_sw_cfg_rw_scrc_out1_owner_default = 0x00000000, regk_iop_sw_cfg_rw_sdp_cfg_default = 0x00000000, regk_iop_sw_cfg_rw_spu0_cfg_default = 0x00000000, regk_iop_sw_cfg_rw_spu0_owner_default = 0x00000000, regk_iop_sw_cfg_rw_spu1_cfg_default = 0x00000000, regk_iop_sw_cfg_rw_spu1_owner_default = 0x00000000, regk_iop_sw_cfg_rw_timer_grp0_cfg_default = 0x00000000, regk_iop_sw_cfg_rw_timer_grp0_owner_default = 0x00000000, regk_iop_sw_cfg_rw_timer_grp1_cfg_default = 0x00000000, regk_iop_sw_cfg_rw_timer_grp1_owner_default = 0x00000000, regk_iop_sw_cfg_rw_timer_grp2_cfg_default = 0x00000000, regk_iop_sw_cfg_rw_timer_grp2_owner_default = 0x00000000, regk_iop_sw_cfg_rw_timer_grp3_cfg_default = 0x00000000, regk_iop_sw_cfg_rw_timer_grp3_owner_default = 0x00000000, regk_iop_sw_cfg_rw_trigger_grp0_owner_default = 0x00000000, regk_iop_sw_cfg_rw_trigger_grp1_owner_default = 0x00000000, regk_iop_sw_cfg_rw_trigger_grp2_owner_default = 0x00000000, regk_iop_sw_cfg_rw_trigger_grp3_owner_default = 0x00000000, regk_iop_sw_cfg_rw_trigger_grp4_owner_default = 0x00000000, regk_iop_sw_cfg_rw_trigger_grp5_owner_default = 0x00000000, regk_iop_sw_cfg_rw_trigger_grp6_owner_default = 0x00000000, regk_iop_sw_cfg_rw_trigger_grp7_owner_default = 0x00000000, regk_iop_sw_cfg_rw_trigger_grps_cfg_default = 0x00000000, regk_iop_sw_cfg_sdp_out0 = 0x00000008, regk_iop_sw_cfg_sdp_out1 = 0x00000009, regk_iop_sw_cfg_size16 = 0x00000002, regk_iop_sw_cfg_size24 = 0x00000003, regk_iop_sw_cfg_size32 = 0x00000004, regk_iop_sw_cfg_size8 = 0x00000001, regk_iop_sw_cfg_spu0 = 0x00000002, regk_iop_sw_cfg_spu0_bus_out0_hi = 0x00000006, regk_iop_sw_cfg_spu0_bus_out0_lo = 0x00000006, regk_iop_sw_cfg_spu0_bus_out1_hi = 0x00000007, regk_iop_sw_cfg_spu0_bus_out1_lo = 0x00000007, regk_iop_sw_cfg_spu0_g0 = 0x0000000e, regk_iop_sw_cfg_spu0_g1 = 0x0000000e, regk_iop_sw_cfg_spu0_g2 = 0x0000000e, regk_iop_sw_cfg_spu0_g3 = 0x0000000e, regk_iop_sw_cfg_spu0_g4 = 0x0000000e, regk_iop_sw_cfg_spu0_g5 = 0x0000000e, regk_iop_sw_cfg_spu0_g6 = 0x0000000e, regk_iop_sw_cfg_spu0_g7 = 0x0000000e, regk_iop_sw_cfg_spu0_gio0 = 0x00000000, regk_iop_sw_cfg_spu0_gio1 = 0x00000001, regk_iop_sw_cfg_spu0_gio2 = 0x00000000, regk_iop_sw_cfg_spu0_gio5 = 0x00000005, regk_iop_sw_cfg_spu0_gio6 = 0x00000006, regk_iop_sw_cfg_spu0_gio7 = 0x00000007, regk_iop_sw_cfg_spu0_gio_out0 = 0x00000008, regk_iop_sw_cfg_spu0_gio_out1 = 0x00000009, regk_iop_sw_cfg_spu0_gio_out2 = 0x0000000a, regk_iop_sw_cfg_spu0_gio_out3 = 0x0000000b, regk_iop_sw_cfg_spu0_gio_out4 = 0x0000000c, regk_iop_sw_cfg_spu0_gio_out5 = 0x0000000d, regk_iop_sw_cfg_spu0_gio_out6 = 0x0000000e, regk_iop_sw_cfg_spu0_gio_out7 = 0x0000000f, regk_iop_sw_cfg_spu0_gioout0 = 0x00000000, regk_iop_sw_cfg_spu0_gioout1 = 0x00000000, regk_iop_sw_cfg_spu0_gioout10 = 0x0000000e, regk_iop_sw_cfg_spu0_gioout11 = 0x0000000e, regk_iop_sw_cfg_spu0_gioout12 = 0x0000000e, regk_iop_sw_cfg_spu0_gioout13 = 0x0000000e, regk_iop_sw_cfg_spu0_gioout14 = 0x0000000e, regk_iop_sw_cfg_spu0_gioout15 = 0x0000000e, regk_iop_sw_cfg_spu0_gioout16 = 0x0000000e, regk_iop_sw_cfg_spu0_gioout17 = 0x0000000e, regk_iop_sw_cfg_spu0_gioout18 = 0x0000000e, regk_iop_sw_cfg_spu0_gioout19 = 0x0000000e, regk_iop_sw_cfg_spu0_gioout2 = 0x00000002, regk_iop_sw_cfg_spu0_gioout20 = 0x0000000e, regk_iop_sw_cfg_spu0_gioout21 = 0x0000000e, regk_iop_sw_cfg_spu0_gioout22 = 0x0000000e, regk_iop_sw_cfg_spu0_gioout23 = 0x0000000e, regk_iop_sw_cfg_spu0_gioout24 = 0x0000000e, regk_iop_sw_cfg_spu0_gioout25 = 0x0000000e, regk_iop_sw_cfg_spu0_gioout26 = 0x0000000e, regk_iop_sw_cfg_spu0_gioout27 = 0x0000000e, regk_iop_sw_cfg_spu0_gioout28 = 0x0000000e, regk_iop_sw_cfg_spu0_gioout29 = 0x0000000e, regk_iop_sw_cfg_spu0_gioout3 = 0x00000002, regk_iop_sw_cfg_spu0_gioout30 = 0x0000000e, regk_iop_sw_cfg_spu0_gioout31 = 0x0000000e, regk_iop_sw_cfg_spu0_gioout4 = 0x00000004, regk_iop_sw_cfg_spu0_gioout5 = 0x00000004, regk_iop_sw_cfg_spu0_gioout6 = 0x00000006, regk_iop_sw_cfg_spu0_gioout7 = 0x00000006, regk_iop_sw_cfg_spu0_gioout8 = 0x0000000e, regk_iop_sw_cfg_spu0_gioout9 = 0x0000000e, regk_iop_sw_cfg_spu1 = 0x00000003, regk_iop_sw_cfg_spu1_bus_out0_hi = 0x00000006, regk_iop_sw_cfg_spu1_bus_out0_lo = 0x00000006, regk_iop_sw_cfg_spu1_bus_out1_hi = 0x00000007, regk_iop_sw_cfg_spu1_bus_out1_lo = 0x00000007, regk_iop_sw_cfg_spu1_g0 = 0x0000000f, regk_iop_sw_cfg_spu1_g1 = 0x0000000f, regk_iop_sw_cfg_spu1_g2 = 0x0000000f, regk_iop_sw_cfg_spu1_g3 = 0x0000000f, regk_iop_sw_cfg_spu1_g4 = 0x0000000f, regk_iop_sw_cfg_spu1_g5 = 0x0000000f, regk_iop_sw_cfg_spu1_g6 = 0x0000000f, regk_iop_sw_cfg_spu1_g7 = 0x0000000f, regk_iop_sw_cfg_spu1_gio0 = 0x00000002, regk_iop_sw_cfg_spu1_gio1 = 0x00000003, regk_iop_sw_cfg_spu1_gio2 = 0x00000002, regk_iop_sw_cfg_spu1_gio5 = 0x00000005, regk_iop_sw_cfg_spu1_gio6 = 0x00000006, regk_iop_sw_cfg_spu1_gio7 = 0x00000007, regk_iop_sw_cfg_spu1_gio_out0 = 0x00000008, regk_iop_sw_cfg_spu1_gio_out1 = 0x00000009, regk_iop_sw_cfg_spu1_gio_out2 = 0x0000000a, regk_iop_sw_cfg_spu1_gio_out3 = 0x0000000b, regk_iop_sw_cfg_spu1_gio_out4 = 0x0000000c, regk_iop_sw_cfg_spu1_gio_out5 = 0x0000000d, regk_iop_sw_cfg_spu1_gio_out6 = 0x0000000e, regk_iop_sw_cfg_spu1_gio_out7 = 0x0000000f, regk_iop_sw_cfg_spu1_gioout0 = 0x00000001, regk_iop_sw_cfg_spu1_gioout1 = 0x00000001, regk_iop_sw_cfg_spu1_gioout10 = 0x0000000f, regk_iop_sw_cfg_spu1_gioout11 = 0x0000000f, regk_iop_sw_cfg_spu1_gioout12 = 0x0000000f, regk_iop_sw_cfg_spu1_gioout13 = 0x0000000f, regk_iop_sw_cfg_spu1_gioout14 = 0x0000000f, regk_iop_sw_cfg_spu1_gioout15 = 0x0000000f, regk_iop_sw_cfg_spu1_gioout16 = 0x0000000f, regk_iop_sw_cfg_spu1_gioout17 = 0x0000000f, regk_iop_sw_cfg_spu1_gioout18 = 0x0000000f, regk_iop_sw_cfg_spu1_gioout19 = 0x0000000f, regk_iop_sw_cfg_spu1_gioout2 = 0x00000003, regk_iop_sw_cfg_spu1_gioout20 = 0x0000000f, regk_iop_sw_cfg_spu1_gioout21 = 0x0000000f, regk_iop_sw_cfg_spu1_gioout22 = 0x0000000f, regk_iop_sw_cfg_spu1_gioout23 = 0x0000000f, regk_iop_sw_cfg_spu1_gioout24 = 0x0000000f, regk_iop_sw_cfg_spu1_gioout25 = 0x0000000f, regk_iop_sw_cfg_spu1_gioout26 = 0x0000000f, regk_iop_sw_cfg_spu1_gioout27 = 0x0000000f, regk_iop_sw_cfg_spu1_gioout28 = 0x0000000f, regk_iop_sw_cfg_spu1_gioout29 = 0x0000000f, regk_iop_sw_cfg_spu1_gioout3 = 0x00000003, regk_iop_sw_cfg_spu1_gioout30 = 0x0000000f, regk_iop_sw_cfg_spu1_gioout31 = 0x0000000f, regk_iop_sw_cfg_spu1_gioout4 = 0x00000005, regk_iop_sw_cfg_spu1_gioout5 = 0x00000005, regk_iop_sw_cfg_spu1_gioout6 = 0x00000007, regk_iop_sw_cfg_spu1_gioout7 = 0x00000007, regk_iop_sw_cfg_spu1_gioout8 = 0x0000000f, regk_iop_sw_cfg_spu1_gioout9 = 0x0000000f, regk_iop_sw_cfg_strb_timer_grp0_tmr0 = 0x00000001, regk_iop_sw_cfg_strb_timer_grp0_tmr1 = 0x00000002, regk_iop_sw_cfg_strb_timer_grp1_tmr0 = 0x00000001, regk_iop_sw_cfg_strb_timer_grp1_tmr1 = 0x00000002, regk_iop_sw_cfg_strb_timer_grp2_tmr0 = 0x00000003, regk_iop_sw_cfg_strb_timer_grp2_tmr1 = 0x00000002, regk_iop_sw_cfg_strb_timer_grp3_tmr0 = 0x00000003, regk_iop_sw_cfg_strb_timer_grp3_tmr1 = 0x00000002, regk_iop_sw_cfg_timer_grp0 = 0x00000000, regk_iop_sw_cfg_timer_grp0_rot = 0x00000001, regk_iop_sw_cfg_timer_grp0_strb0 = 0x0000000a, regk_iop_sw_cfg_timer_grp0_strb1 = 0x0000000a, regk_iop_sw_cfg_timer_grp0_strb2 = 0x0000000a, regk_iop_sw_cfg_timer_grp0_strb3 = 0x0000000a, regk_iop_sw_cfg_timer_grp0_tmr0 = 0x00000004, regk_iop_sw_cfg_timer_grp0_tmr1 = 0x00000004, regk_iop_sw_cfg_timer_grp1 = 0x00000000, regk_iop_sw_cfg_timer_grp1_rot = 0x00000001, regk_iop_sw_cfg_timer_grp1_strb0 = 0x0000000b, regk_iop_sw_cfg_timer_grp1_strb1 = 0x0000000b, regk_iop_sw_cfg_timer_grp1_strb2 = 0x0000000b, regk_iop_sw_cfg_timer_grp1_strb3 = 0x0000000b, regk_iop_sw_cfg_timer_grp1_tmr0 = 0x00000005, regk_iop_sw_cfg_timer_grp1_tmr1 = 0x00000005, regk_iop_sw_cfg_timer_grp2 = 0x00000000, regk_iop_sw_cfg_timer_grp2_rot = 0x00000001, regk_iop_sw_cfg_timer_grp2_strb0 = 0x0000000c, regk_iop_sw_cfg_timer_grp2_strb1 = 0x0000000c, regk_iop_sw_cfg_timer_grp2_strb2 = 0x0000000c, regk_iop_sw_cfg_timer_grp2_strb3 = 0x0000000c, regk_iop_sw_cfg_timer_grp2_tmr0 = 0x00000006, regk_iop_sw_cfg_timer_grp2_tmr1 = 0x00000006, regk_iop_sw_cfg_timer_grp3 = 0x00000000, regk_iop_sw_cfg_timer_grp3_rot = 0x00000001, regk_iop_sw_cfg_timer_grp3_strb0 = 0x0000000d, regk_iop_sw_cfg_timer_grp3_strb1 = 0x0000000d, regk_iop_sw_cfg_timer_grp3_strb2 = 0x0000000d, regk_iop_sw_cfg_timer_grp3_strb3 = 0x0000000d, regk_iop_sw_cfg_timer_grp3_tmr0 = 0x00000007, regk_iop_sw_cfg_timer_grp3_tmr1 = 0x00000007, regk_iop_sw_cfg_trig0_0 = 0x00000000, regk_iop_sw_cfg_trig0_1 = 0x00000000, regk_iop_sw_cfg_trig0_2 = 0x00000000, regk_iop_sw_cfg_trig0_3 = 0x00000000, regk_iop_sw_cfg_trig1_0 = 0x00000000, regk_iop_sw_cfg_trig1_1 = 0x00000000, regk_iop_sw_cfg_trig1_2 = 0x00000000, regk_iop_sw_cfg_trig1_3 = 0x00000000, regk_iop_sw_cfg_trig2_0 = 0x00000000, regk_iop_sw_cfg_trig2_1 = 0x00000000, regk_iop_sw_cfg_trig2_2 = 0x00000000, regk_iop_sw_cfg_trig2_3 = 0x00000000, regk_iop_sw_cfg_trig3_0 = 0x00000000, regk_iop_sw_cfg_trig3_1 = 0x00000000, regk_iop_sw_cfg_trig3_2 = 0x00000000, regk_iop_sw_cfg_trig3_3 = 0x00000000, regk_iop_sw_cfg_trig4_0 = 0x00000001, regk_iop_sw_cfg_trig4_1 = 0x00000001, regk_iop_sw_cfg_trig4_2 = 0x00000001, regk_iop_sw_cfg_trig4_3 = 0x00000001, regk_iop_sw_cfg_trig5_0 = 0x00000001, regk_iop_sw_cfg_trig5_1 = 0x00000001, regk_iop_sw_cfg_trig5_2 = 0x00000001, regk_iop_sw_cfg_trig5_3 = 0x00000001, regk_iop_sw_cfg_trig6_0 = 0x00000001, regk_iop_sw_cfg_trig6_1 = 0x00000001, regk_iop_sw_cfg_trig6_2 = 0x00000001, regk_iop_sw_cfg_trig6_3 = 0x00000001, regk_iop_sw_cfg_trig7_0 = 0x00000001, regk_iop_sw_cfg_trig7_1 = 0x00000001, regk_iop_sw_cfg_trig7_2 = 0x00000001, regk_iop_sw_cfg_trig7_3 = 0x00000001 }

Macro Definition Documentation

#define REG_ADDR	(	scope,
		inst,
		reg
	)	( (inst) + REG_RD_ADDR_##scope##_##reg )

Definition at line 75 of file iop_sw_cfg_defs.h.

#define REG_ADDR_VECT	(	scope,
		inst,
		reg,
		index
	)

Value:

( (inst) + REG_RD_ADDR_##scope##_##reg + \

(index) * STRIDE_##scope##_##reg )

Definition at line 80 of file iop_sw_cfg_defs.h.

#define reg_page_size 8192

Definition at line 71 of file iop_sw_cfg_defs.h.

#define REG_RD	(	scope,
		inst,
		reg
	)

Value:

REG_READ( reg_##scope##_##reg, \

(inst) + REG_RD_ADDR_##scope##_##reg )

Definition at line 18 of file iop_sw_cfg_defs.h.

#define REG_RD_ADDR_iop_sw_cfg_rw_bus0_mask 136

Definition at line 366 of file iop_sw_cfg_defs.h.

#define REG_RD_ADDR_iop_sw_cfg_rw_bus0_oe_mask 140

Definition at line 377 of file iop_sw_cfg_defs.h.

#define REG_RD_ADDR_iop_sw_cfg_rw_bus1_mask 144

Definition at line 387 of file iop_sw_cfg_defs.h.

#define REG_RD_ADDR_iop_sw_cfg_rw_bus1_oe_mask 148

Definition at line 398 of file iop_sw_cfg_defs.h.

#define REG_RD_ADDR_iop_sw_cfg_rw_bus_out_cfg 164

Definition at line 449 of file iop_sw_cfg_defs.h.

#define REG_RD_ADDR_iop_sw_cfg_rw_crc_par0_owner 0

Definition at line 92 of file iop_sw_cfg_defs.h.

#define REG_RD_ADDR_iop_sw_cfg_rw_crc_par1_owner 4

Definition at line 100 of file iop_sw_cfg_defs.h.

#define REG_RD_ADDR_iop_sw_cfg_rw_dmc_in0_owner 8

Definition at line 108 of file iop_sw_cfg_defs.h.

#define REG_RD_ADDR_iop_sw_cfg_rw_dmc_in1_owner 12

Definition at line 116 of file iop_sw_cfg_defs.h.

#define REG_RD_ADDR_iop_sw_cfg_rw_dmc_out0_owner 16

Definition at line 124 of file iop_sw_cfg_defs.h.

#define REG_RD_ADDR_iop_sw_cfg_rw_dmc_out1_owner 20

Definition at line 132 of file iop_sw_cfg_defs.h.

#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_in0_extra_owner 28

Definition at line 148 of file iop_sw_cfg_defs.h.

#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_in0_owner 24

Definition at line 140 of file iop_sw_cfg_defs.h.

#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_in1_extra_owner 36

Definition at line 164 of file iop_sw_cfg_defs.h.

#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_in1_owner 32

Definition at line 156 of file iop_sw_cfg_defs.h.

#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_out0_extra_owner 44

Definition at line 180 of file iop_sw_cfg_defs.h.

#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_out0_owner 40

Definition at line 172 of file iop_sw_cfg_defs.h.

#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_out1_extra_owner 52

Definition at line 196 of file iop_sw_cfg_defs.h.

#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_out1_owner 48

Definition at line 188 of file iop_sw_cfg_defs.h.

#define REG_RD_ADDR_iop_sw_cfg_rw_gio_mask 152

Definition at line 405 of file iop_sw_cfg_defs.h.

#define REG_RD_ADDR_iop_sw_cfg_rw_gio_oe_mask 156

Definition at line 412 of file iop_sw_cfg_defs.h.

#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp0_cfg 168

Definition at line 464 of file iop_sw_cfg_defs.h.

#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp1_cfg 172

Definition at line 479 of file iop_sw_cfg_defs.h.

#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp2_cfg 176

Definition at line 494 of file iop_sw_cfg_defs.h.

#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp3_cfg 180

Definition at line 509 of file iop_sw_cfg_defs.h.

#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp4_cfg 184

Definition at line 524 of file iop_sw_cfg_defs.h.

#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp5_cfg 188

Definition at line 539 of file iop_sw_cfg_defs.h.

#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp6_cfg 192

Definition at line 554 of file iop_sw_cfg_defs.h.

#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp7_cfg 196

Definition at line 569 of file iop_sw_cfg_defs.h.

#define REG_RD_ADDR_iop_sw_cfg_rw_pdp0_cfg 228

Definition at line 688 of file iop_sw_cfg_defs.h.

#define REG_RD_ADDR_iop_sw_cfg_rw_pdp1_cfg 232

Definition at line 702 of file iop_sw_cfg_defs.h.

#define REG_RD_ADDR_iop_sw_cfg_rw_pinmapping 160

Definition at line 434 of file iop_sw_cfg_defs.h.

#define REG_RD_ADDR_iop_sw_cfg_rw_sap_in_owner 56

Definition at line 204 of file iop_sw_cfg_defs.h.

#define REG_RD_ADDR_iop_sw_cfg_rw_sap_out_owner 60

Definition at line 212 of file iop_sw_cfg_defs.h.

#define REG_RD_ADDR_iop_sw_cfg_rw_scrc_in0_owner 64

Definition at line 220 of file iop_sw_cfg_defs.h.

#define REG_RD_ADDR_iop_sw_cfg_rw_scrc_in1_owner 68

Definition at line 228 of file iop_sw_cfg_defs.h.

#define REG_RD_ADDR_iop_sw_cfg_rw_scrc_out0_owner 72

Definition at line 236 of file iop_sw_cfg_defs.h.

#define REG_RD_ADDR_iop_sw_cfg_rw_scrc_out1_owner 76

Definition at line 244 of file iop_sw_cfg_defs.h.

#define REG_RD_ADDR_iop_sw_cfg_rw_sdp_cfg 236

Definition at line 717 of file iop_sw_cfg_defs.h.

#define REG_RD_ADDR_iop_sw_cfg_rw_spu0_cfg 200

Definition at line 578 of file iop_sw_cfg_defs.h.

#define REG_RD_ADDR_iop_sw_cfg_rw_spu0_owner 80

Definition at line 252 of file iop_sw_cfg_defs.h.

#define REG_RD_ADDR_iop_sw_cfg_rw_spu1_cfg 204

Definition at line 587 of file iop_sw_cfg_defs.h.

#define REG_RD_ADDR_iop_sw_cfg_rw_spu1_owner 84

Definition at line 260 of file iop_sw_cfg_defs.h.

#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp0_cfg 208

Definition at line 603 of file iop_sw_cfg_defs.h.

#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp0_owner 88

Definition at line 268 of file iop_sw_cfg_defs.h.

#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp1_cfg 212

Definition at line 619 of file iop_sw_cfg_defs.h.

#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp1_owner 92

Definition at line 276 of file iop_sw_cfg_defs.h.

#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp2_cfg 216

Definition at line 635 of file iop_sw_cfg_defs.h.

#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp2_owner 96

Definition at line 284 of file iop_sw_cfg_defs.h.

#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp3_cfg 220

Definition at line 651 of file iop_sw_cfg_defs.h.

#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp3_owner 100

Definition at line 292 of file iop_sw_cfg_defs.h.

#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp0_owner 104

Definition at line 300 of file iop_sw_cfg_defs.h.

#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp1_owner 108

Definition at line 308 of file iop_sw_cfg_defs.h.

#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp2_owner 112

Definition at line 316 of file iop_sw_cfg_defs.h.

#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp3_owner 116

Definition at line 324 of file iop_sw_cfg_defs.h.

#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp4_owner 120

Definition at line 332 of file iop_sw_cfg_defs.h.

#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp5_owner 124

Definition at line 340 of file iop_sw_cfg_defs.h.

#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp6_owner 128

Definition at line 348 of file iop_sw_cfg_defs.h.

#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp7_owner 132

Definition at line 356 of file iop_sw_cfg_defs.h.

#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grps_cfg 224

Definition at line 674 of file iop_sw_cfg_defs.h.

#define REG_RD_INT	(	scope,
		inst,
		reg
	)	REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )

Definition at line 44 of file iop_sw_cfg_defs.h.

#define REG_RD_INT_VECT	(	scope,
		inst,
		reg,
		index
	)

Value:

REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \

(index) * STRIDE_##scope##_##reg )

Definition at line 54 of file iop_sw_cfg_defs.h.

#define REG_RD_VECT	(	scope,
		inst,
		reg,
		index
	)

Value:

REG_READ( reg_##scope##_##reg, \
            (inst) + REG_RD_ADDR_##scope##_##reg + \
        (index) * STRIDE_##scope##_##reg )

Definition at line 30 of file iop_sw_cfg_defs.h.

#define REG_TYPE_CONV	(	type,
		orgtype,
		val
	)	( { union { orgtype o; type n; } r; r.o = val; r.n; } )

Definition at line 66 of file iop_sw_cfg_defs.h.

#define REG_WR	(	scope,
		inst,
		reg,
		val
	)

Value:

REG_WRITE( reg_##scope##_##reg, \

(inst) + REG_WR_ADDR_##scope##_##reg, (val) )

Definition at line 24 of file iop_sw_cfg_defs.h.

#define REG_WR_ADDR_iop_sw_cfg_rw_bus0_mask 136

Definition at line 367 of file iop_sw_cfg_defs.h.

#define REG_WR_ADDR_iop_sw_cfg_rw_bus0_oe_mask 140

Definition at line 378 of file iop_sw_cfg_defs.h.

#define REG_WR_ADDR_iop_sw_cfg_rw_bus1_mask 144

Definition at line 388 of file iop_sw_cfg_defs.h.

#define REG_WR_ADDR_iop_sw_cfg_rw_bus1_oe_mask 148

Definition at line 399 of file iop_sw_cfg_defs.h.

#define REG_WR_ADDR_iop_sw_cfg_rw_bus_out_cfg 164

Definition at line 450 of file iop_sw_cfg_defs.h.

#define REG_WR_ADDR_iop_sw_cfg_rw_crc_par0_owner 0

Definition at line 93 of file iop_sw_cfg_defs.h.

#define REG_WR_ADDR_iop_sw_cfg_rw_crc_par1_owner 4

Definition at line 101 of file iop_sw_cfg_defs.h.

#define REG_WR_ADDR_iop_sw_cfg_rw_dmc_in0_owner 8

Definition at line 109 of file iop_sw_cfg_defs.h.

#define REG_WR_ADDR_iop_sw_cfg_rw_dmc_in1_owner 12

Definition at line 117 of file iop_sw_cfg_defs.h.

#define REG_WR_ADDR_iop_sw_cfg_rw_dmc_out0_owner 16

Definition at line 125 of file iop_sw_cfg_defs.h.

#define REG_WR_ADDR_iop_sw_cfg_rw_dmc_out1_owner 20

Definition at line 133 of file iop_sw_cfg_defs.h.

#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_in0_extra_owner 28

Definition at line 149 of file iop_sw_cfg_defs.h.

#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_in0_owner 24

Definition at line 141 of file iop_sw_cfg_defs.h.

#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_in1_extra_owner 36

Definition at line 165 of file iop_sw_cfg_defs.h.

#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_in1_owner 32

Definition at line 157 of file iop_sw_cfg_defs.h.

#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_out0_extra_owner 44

Definition at line 181 of file iop_sw_cfg_defs.h.

#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_out0_owner 40

Definition at line 173 of file iop_sw_cfg_defs.h.

#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_out1_extra_owner 52

Definition at line 197 of file iop_sw_cfg_defs.h.

#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_out1_owner 48

Definition at line 189 of file iop_sw_cfg_defs.h.

#define REG_WR_ADDR_iop_sw_cfg_rw_gio_mask 152

Definition at line 406 of file iop_sw_cfg_defs.h.

#define REG_WR_ADDR_iop_sw_cfg_rw_gio_oe_mask 156

Definition at line 413 of file iop_sw_cfg_defs.h.

#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp0_cfg 168

Definition at line 465 of file iop_sw_cfg_defs.h.

#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp1_cfg 172

Definition at line 480 of file iop_sw_cfg_defs.h.

#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp2_cfg 176

Definition at line 495 of file iop_sw_cfg_defs.h.

#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp3_cfg 180

Definition at line 510 of file iop_sw_cfg_defs.h.

#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp4_cfg 184

Definition at line 525 of file iop_sw_cfg_defs.h.

#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp5_cfg 188

Definition at line 540 of file iop_sw_cfg_defs.h.

#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp6_cfg 192

Definition at line 555 of file iop_sw_cfg_defs.h.

#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp7_cfg 196

Definition at line 570 of file iop_sw_cfg_defs.h.

#define REG_WR_ADDR_iop_sw_cfg_rw_pdp0_cfg 228

Definition at line 689 of file iop_sw_cfg_defs.h.

#define REG_WR_ADDR_iop_sw_cfg_rw_pdp1_cfg 232

Definition at line 703 of file iop_sw_cfg_defs.h.

#define REG_WR_ADDR_iop_sw_cfg_rw_pinmapping 160

Definition at line 435 of file iop_sw_cfg_defs.h.

#define REG_WR_ADDR_iop_sw_cfg_rw_sap_in_owner 56

Definition at line 205 of file iop_sw_cfg_defs.h.

#define REG_WR_ADDR_iop_sw_cfg_rw_sap_out_owner 60

Definition at line 213 of file iop_sw_cfg_defs.h.

#define REG_WR_ADDR_iop_sw_cfg_rw_scrc_in0_owner 64

Definition at line 221 of file iop_sw_cfg_defs.h.

#define REG_WR_ADDR_iop_sw_cfg_rw_scrc_in1_owner 68

Definition at line 229 of file iop_sw_cfg_defs.h.

#define REG_WR_ADDR_iop_sw_cfg_rw_scrc_out0_owner 72

Definition at line 237 of file iop_sw_cfg_defs.h.

#define REG_WR_ADDR_iop_sw_cfg_rw_scrc_out1_owner 76

Definition at line 245 of file iop_sw_cfg_defs.h.

#define REG_WR_ADDR_iop_sw_cfg_rw_sdp_cfg 236

Definition at line 718 of file iop_sw_cfg_defs.h.

#define REG_WR_ADDR_iop_sw_cfg_rw_spu0_cfg 200

Definition at line 579 of file iop_sw_cfg_defs.h.

#define REG_WR_ADDR_iop_sw_cfg_rw_spu0_owner 80

Definition at line 253 of file iop_sw_cfg_defs.h.

#define REG_WR_ADDR_iop_sw_cfg_rw_spu1_cfg 204

Definition at line 588 of file iop_sw_cfg_defs.h.

#define REG_WR_ADDR_iop_sw_cfg_rw_spu1_owner 84

Definition at line 261 of file iop_sw_cfg_defs.h.

#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp0_cfg 208

Definition at line 604 of file iop_sw_cfg_defs.h.

#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp0_owner 88

Definition at line 269 of file iop_sw_cfg_defs.h.

#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp1_cfg 212

Definition at line 620 of file iop_sw_cfg_defs.h.

#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp1_owner 92

Definition at line 277 of file iop_sw_cfg_defs.h.

#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp2_cfg 216

Definition at line 636 of file iop_sw_cfg_defs.h.

#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp2_owner 96

Definition at line 285 of file iop_sw_cfg_defs.h.

#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp3_cfg 220

Definition at line 652 of file iop_sw_cfg_defs.h.

#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp3_owner 100

Definition at line 293 of file iop_sw_cfg_defs.h.

#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp0_owner 104

Definition at line 301 of file iop_sw_cfg_defs.h.

#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp1_owner 108

Definition at line 309 of file iop_sw_cfg_defs.h.

#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp2_owner 112

Definition at line 317 of file iop_sw_cfg_defs.h.

#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp3_owner 116

Definition at line 325 of file iop_sw_cfg_defs.h.

#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp4_owner 120

Definition at line 333 of file iop_sw_cfg_defs.h.

#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp5_owner 124

Definition at line 341 of file iop_sw_cfg_defs.h.

#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp6_owner 128

Definition at line 349 of file iop_sw_cfg_defs.h.

#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp7_owner 132

Definition at line 357 of file iop_sw_cfg_defs.h.

#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grps_cfg 224

Definition at line 675 of file iop_sw_cfg_defs.h.

#define REG_WR_INT	(	scope,
		inst,
		reg,
		val
	)	REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )

Definition at line 49 of file iop_sw_cfg_defs.h.

#define REG_WR_INT_VECT	(	scope,
		inst,
		reg,
		index,
		val
	)

Value:

REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \

(index) * STRIDE_##scope##_##reg, (val) )

Definition at line 60 of file iop_sw_cfg_defs.h.

#define REG_WR_VECT	(	scope,
		inst,
		reg,
		index,
		val
	)

Value:

REG_WRITE( reg_##scope##_##reg, \
             (inst) + REG_WR_ADDR_##scope##_##reg + \
         (index) * STRIDE_##scope##_##reg, (val) )

Definition at line 37 of file iop_sw_cfg_defs.h.

Enumeration Type Documentation

anonymous enum

Enumerator:

regk_iop_sw_cfg_a
regk_iop_sw_cfg_b
regk_iop_sw_cfg_bus0
regk_iop_sw_cfg_bus0_rot16
regk_iop_sw_cfg_bus0_rot24
regk_iop_sw_cfg_bus0_rot8
regk_iop_sw_cfg_bus1
regk_iop_sw_cfg_bus1_rot16
regk_iop_sw_cfg_bus1_rot24
regk_iop_sw_cfg_bus1_rot8
regk_iop_sw_cfg_clk12
regk_iop_sw_cfg_cpu
regk_iop_sw_cfg_dmc0
regk_iop_sw_cfg_dmc1
regk_iop_sw_cfg_gated_clk0
regk_iop_sw_cfg_gated_clk1
regk_iop_sw_cfg_gated_clk2
regk_iop_sw_cfg_gated_clk3
regk_iop_sw_cfg_gio0
regk_iop_sw_cfg_gio1
regk_iop_sw_cfg_gio2
regk_iop_sw_cfg_gio3
regk_iop_sw_cfg_gio4
regk_iop_sw_cfg_gio5
regk_iop_sw_cfg_gio6
regk_iop_sw_cfg_gio7
regk_iop_sw_cfg_gio_in0
regk_iop_sw_cfg_gio_in1
regk_iop_sw_cfg_gio_in10
regk_iop_sw_cfg_gio_in11
regk_iop_sw_cfg_gio_in14
regk_iop_sw_cfg_gio_in15
regk_iop_sw_cfg_gio_in18
regk_iop_sw_cfg_gio_in19
regk_iop_sw_cfg_gio_in20
regk_iop_sw_cfg_gio_in21
regk_iop_sw_cfg_gio_in26
regk_iop_sw_cfg_gio_in27
regk_iop_sw_cfg_gio_in28
regk_iop_sw_cfg_gio_in29
regk_iop_sw_cfg_gio_in4
regk_iop_sw_cfg_gio_in5
regk_iop_sw_cfg_last_timer_grp0_tmr2
regk_iop_sw_cfg_last_timer_grp1_tmr2
regk_iop_sw_cfg_last_timer_grp2_tmr2
regk_iop_sw_cfg_last_timer_grp2_tmr3
regk_iop_sw_cfg_last_timer_grp3_tmr2
regk_iop_sw_cfg_last_timer_grp3_tmr3
regk_iop_sw_cfg_mpu
regk_iop_sw_cfg_none
regk_iop_sw_cfg_par0
regk_iop_sw_cfg_par1
regk_iop_sw_cfg_pdp_out0
regk_iop_sw_cfg_pdp_out0_hi
regk_iop_sw_cfg_pdp_out0_hi_rot8
regk_iop_sw_cfg_pdp_out0_lo
regk_iop_sw_cfg_pdp_out0_lo_rot8
regk_iop_sw_cfg_pdp_out1
regk_iop_sw_cfg_pdp_out1_hi
regk_iop_sw_cfg_pdp_out1_hi_rot8
regk_iop_sw_cfg_pdp_out1_lo
regk_iop_sw_cfg_pdp_out1_lo_rot8
regk_iop_sw_cfg_rw_bus0_mask_default
regk_iop_sw_cfg_rw_bus0_oe_mask_default
regk_iop_sw_cfg_rw_bus1_mask_default
regk_iop_sw_cfg_rw_bus1_oe_mask_default
regk_iop_sw_cfg_rw_bus_out_cfg_default
regk_iop_sw_cfg_rw_crc_par0_owner_default
regk_iop_sw_cfg_rw_crc_par1_owner_default
regk_iop_sw_cfg_rw_dmc_in0_owner_default
regk_iop_sw_cfg_rw_dmc_in1_owner_default
regk_iop_sw_cfg_rw_dmc_out0_owner_default
regk_iop_sw_cfg_rw_dmc_out1_owner_default
regk_iop_sw_cfg_rw_fifo_in0_extra_owner_default
regk_iop_sw_cfg_rw_fifo_in0_owner_default
regk_iop_sw_cfg_rw_fifo_in1_extra_owner_default
regk_iop_sw_cfg_rw_fifo_in1_owner_default
regk_iop_sw_cfg_rw_fifo_out0_extra_owner_default
regk_iop_sw_cfg_rw_fifo_out0_owner_default
regk_iop_sw_cfg_rw_fifo_out1_extra_owner_default
regk_iop_sw_cfg_rw_fifo_out1_owner_default
regk_iop_sw_cfg_rw_gio_mask_default
regk_iop_sw_cfg_rw_gio_oe_mask_default
regk_iop_sw_cfg_rw_gio_out_grp0_cfg_default
regk_iop_sw_cfg_rw_gio_out_grp1_cfg_default
regk_iop_sw_cfg_rw_gio_out_grp2_cfg_default
regk_iop_sw_cfg_rw_gio_out_grp3_cfg_default
regk_iop_sw_cfg_rw_gio_out_grp4_cfg_default
regk_iop_sw_cfg_rw_gio_out_grp5_cfg_default
regk_iop_sw_cfg_rw_gio_out_grp6_cfg_default
regk_iop_sw_cfg_rw_gio_out_grp7_cfg_default
regk_iop_sw_cfg_rw_pdp0_cfg_default
regk_iop_sw_cfg_rw_pdp1_cfg_default
regk_iop_sw_cfg_rw_pinmapping_default
regk_iop_sw_cfg_rw_sap_in_owner_default
regk_iop_sw_cfg_rw_sap_out_owner_default
regk_iop_sw_cfg_rw_scrc_in0_owner_default
regk_iop_sw_cfg_rw_scrc_in1_owner_default
regk_iop_sw_cfg_rw_scrc_out0_owner_default
regk_iop_sw_cfg_rw_scrc_out1_owner_default
regk_iop_sw_cfg_rw_sdp_cfg_default
regk_iop_sw_cfg_rw_spu0_cfg_default
regk_iop_sw_cfg_rw_spu0_owner_default
regk_iop_sw_cfg_rw_spu1_cfg_default
regk_iop_sw_cfg_rw_spu1_owner_default
regk_iop_sw_cfg_rw_timer_grp0_cfg_default
regk_iop_sw_cfg_rw_timer_grp0_owner_default
regk_iop_sw_cfg_rw_timer_grp1_cfg_default
regk_iop_sw_cfg_rw_timer_grp1_owner_default
regk_iop_sw_cfg_rw_timer_grp2_cfg_default
regk_iop_sw_cfg_rw_timer_grp2_owner_default
regk_iop_sw_cfg_rw_timer_grp3_cfg_default
regk_iop_sw_cfg_rw_timer_grp3_owner_default
regk_iop_sw_cfg_rw_trigger_grp0_owner_default
regk_iop_sw_cfg_rw_trigger_grp1_owner_default
regk_iop_sw_cfg_rw_trigger_grp2_owner_default
regk_iop_sw_cfg_rw_trigger_grp3_owner_default
regk_iop_sw_cfg_rw_trigger_grp4_owner_default
regk_iop_sw_cfg_rw_trigger_grp5_owner_default
regk_iop_sw_cfg_rw_trigger_grp6_owner_default
regk_iop_sw_cfg_rw_trigger_grp7_owner_default
regk_iop_sw_cfg_rw_trigger_grps_cfg_default
regk_iop_sw_cfg_sdp_out0
regk_iop_sw_cfg_sdp_out1
regk_iop_sw_cfg_size16
regk_iop_sw_cfg_size24
regk_iop_sw_cfg_size32
regk_iop_sw_cfg_size8
regk_iop_sw_cfg_spu0
regk_iop_sw_cfg_spu0_bus_out0_hi
regk_iop_sw_cfg_spu0_bus_out0_lo
regk_iop_sw_cfg_spu0_bus_out1_hi
regk_iop_sw_cfg_spu0_bus_out1_lo
regk_iop_sw_cfg_spu0_g0
regk_iop_sw_cfg_spu0_g1
regk_iop_sw_cfg_spu0_g2
regk_iop_sw_cfg_spu0_g3
regk_iop_sw_cfg_spu0_g4
regk_iop_sw_cfg_spu0_g5
regk_iop_sw_cfg_spu0_g6
regk_iop_sw_cfg_spu0_g7
regk_iop_sw_cfg_spu0_gio0
regk_iop_sw_cfg_spu0_gio1
regk_iop_sw_cfg_spu0_gio2
regk_iop_sw_cfg_spu0_gio5
regk_iop_sw_cfg_spu0_gio6
regk_iop_sw_cfg_spu0_gio7
regk_iop_sw_cfg_spu0_gio_out0
regk_iop_sw_cfg_spu0_gio_out1
regk_iop_sw_cfg_spu0_gio_out2
regk_iop_sw_cfg_spu0_gio_out3
regk_iop_sw_cfg_spu0_gio_out4
regk_iop_sw_cfg_spu0_gio_out5
regk_iop_sw_cfg_spu0_gio_out6
regk_iop_sw_cfg_spu0_gio_out7
regk_iop_sw_cfg_spu0_gioout0
regk_iop_sw_cfg_spu0_gioout1
regk_iop_sw_cfg_spu0_gioout10
regk_iop_sw_cfg_spu0_gioout11
regk_iop_sw_cfg_spu0_gioout12
regk_iop_sw_cfg_spu0_gioout13
regk_iop_sw_cfg_spu0_gioout14
regk_iop_sw_cfg_spu0_gioout15
regk_iop_sw_cfg_spu0_gioout16
regk_iop_sw_cfg_spu0_gioout17
regk_iop_sw_cfg_spu0_gioout18
regk_iop_sw_cfg_spu0_gioout19
regk_iop_sw_cfg_spu0_gioout2
regk_iop_sw_cfg_spu0_gioout20
regk_iop_sw_cfg_spu0_gioout21
regk_iop_sw_cfg_spu0_gioout22
regk_iop_sw_cfg_spu0_gioout23
regk_iop_sw_cfg_spu0_gioout24
regk_iop_sw_cfg_spu0_gioout25
regk_iop_sw_cfg_spu0_gioout26
regk_iop_sw_cfg_spu0_gioout27
regk_iop_sw_cfg_spu0_gioout28
regk_iop_sw_cfg_spu0_gioout29
regk_iop_sw_cfg_spu0_gioout3
regk_iop_sw_cfg_spu0_gioout30
regk_iop_sw_cfg_spu0_gioout31
regk_iop_sw_cfg_spu0_gioout4
regk_iop_sw_cfg_spu0_gioout5
regk_iop_sw_cfg_spu0_gioout6
regk_iop_sw_cfg_spu0_gioout7
regk_iop_sw_cfg_spu0_gioout8
regk_iop_sw_cfg_spu0_gioout9
regk_iop_sw_cfg_spu1
regk_iop_sw_cfg_spu1_bus_out0_hi
regk_iop_sw_cfg_spu1_bus_out0_lo
regk_iop_sw_cfg_spu1_bus_out1_hi
regk_iop_sw_cfg_spu1_bus_out1_lo
regk_iop_sw_cfg_spu1_g0
regk_iop_sw_cfg_spu1_g1
regk_iop_sw_cfg_spu1_g2
regk_iop_sw_cfg_spu1_g3
regk_iop_sw_cfg_spu1_g4
regk_iop_sw_cfg_spu1_g5
regk_iop_sw_cfg_spu1_g6
regk_iop_sw_cfg_spu1_g7
regk_iop_sw_cfg_spu1_gio0
regk_iop_sw_cfg_spu1_gio1
regk_iop_sw_cfg_spu1_gio2
regk_iop_sw_cfg_spu1_gio5
regk_iop_sw_cfg_spu1_gio6
regk_iop_sw_cfg_spu1_gio7
regk_iop_sw_cfg_spu1_gio_out0
regk_iop_sw_cfg_spu1_gio_out1
regk_iop_sw_cfg_spu1_gio_out2
regk_iop_sw_cfg_spu1_gio_out3
regk_iop_sw_cfg_spu1_gio_out4
regk_iop_sw_cfg_spu1_gio_out5
regk_iop_sw_cfg_spu1_gio_out6
regk_iop_sw_cfg_spu1_gio_out7
regk_iop_sw_cfg_spu1_gioout0
regk_iop_sw_cfg_spu1_gioout1
regk_iop_sw_cfg_spu1_gioout10
regk_iop_sw_cfg_spu1_gioout11
regk_iop_sw_cfg_spu1_gioout12
regk_iop_sw_cfg_spu1_gioout13
regk_iop_sw_cfg_spu1_gioout14
regk_iop_sw_cfg_spu1_gioout15
regk_iop_sw_cfg_spu1_gioout16
regk_iop_sw_cfg_spu1_gioout17
regk_iop_sw_cfg_spu1_gioout18
regk_iop_sw_cfg_spu1_gioout19
regk_iop_sw_cfg_spu1_gioout2
regk_iop_sw_cfg_spu1_gioout20
regk_iop_sw_cfg_spu1_gioout21
regk_iop_sw_cfg_spu1_gioout22
regk_iop_sw_cfg_spu1_gioout23
regk_iop_sw_cfg_spu1_gioout24
regk_iop_sw_cfg_spu1_gioout25
regk_iop_sw_cfg_spu1_gioout26
regk_iop_sw_cfg_spu1_gioout27
regk_iop_sw_cfg_spu1_gioout28
regk_iop_sw_cfg_spu1_gioout29
regk_iop_sw_cfg_spu1_gioout3
regk_iop_sw_cfg_spu1_gioout30
regk_iop_sw_cfg_spu1_gioout31
regk_iop_sw_cfg_spu1_gioout4
regk_iop_sw_cfg_spu1_gioout5
regk_iop_sw_cfg_spu1_gioout6
regk_iop_sw_cfg_spu1_gioout7
regk_iop_sw_cfg_spu1_gioout8
regk_iop_sw_cfg_spu1_gioout9
regk_iop_sw_cfg_strb_timer_grp0_tmr0
regk_iop_sw_cfg_strb_timer_grp0_tmr1
regk_iop_sw_cfg_strb_timer_grp1_tmr0
regk_iop_sw_cfg_strb_timer_grp1_tmr1
regk_iop_sw_cfg_strb_timer_grp2_tmr0
regk_iop_sw_cfg_strb_timer_grp2_tmr1
regk_iop_sw_cfg_strb_timer_grp3_tmr0
regk_iop_sw_cfg_strb_timer_grp3_tmr1
regk_iop_sw_cfg_timer_grp0
regk_iop_sw_cfg_timer_grp0_rot
regk_iop_sw_cfg_timer_grp0_strb0
regk_iop_sw_cfg_timer_grp0_strb1
regk_iop_sw_cfg_timer_grp0_strb2
regk_iop_sw_cfg_timer_grp0_strb3
regk_iop_sw_cfg_timer_grp0_tmr0
regk_iop_sw_cfg_timer_grp0_tmr1
regk_iop_sw_cfg_timer_grp1
regk_iop_sw_cfg_timer_grp1_rot
regk_iop_sw_cfg_timer_grp1_strb0
regk_iop_sw_cfg_timer_grp1_strb1
regk_iop_sw_cfg_timer_grp1_strb2
regk_iop_sw_cfg_timer_grp1_strb3
regk_iop_sw_cfg_timer_grp1_tmr0
regk_iop_sw_cfg_timer_grp1_tmr1
regk_iop_sw_cfg_timer_grp2
regk_iop_sw_cfg_timer_grp2_rot
regk_iop_sw_cfg_timer_grp2_strb0
regk_iop_sw_cfg_timer_grp2_strb1
regk_iop_sw_cfg_timer_grp2_strb2
regk_iop_sw_cfg_timer_grp2_strb3
regk_iop_sw_cfg_timer_grp2_tmr0
regk_iop_sw_cfg_timer_grp2_tmr1
regk_iop_sw_cfg_timer_grp3
regk_iop_sw_cfg_timer_grp3_rot
regk_iop_sw_cfg_timer_grp3_strb0
regk_iop_sw_cfg_timer_grp3_strb1
regk_iop_sw_cfg_timer_grp3_strb2
regk_iop_sw_cfg_timer_grp3_strb3
regk_iop_sw_cfg_timer_grp3_tmr0
regk_iop_sw_cfg_timer_grp3_tmr1
regk_iop_sw_cfg_trig0_0
regk_iop_sw_cfg_trig0_1
regk_iop_sw_cfg_trig0_2
regk_iop_sw_cfg_trig0_3
regk_iop_sw_cfg_trig1_0
regk_iop_sw_cfg_trig1_1
regk_iop_sw_cfg_trig1_2
regk_iop_sw_cfg_trig1_3
regk_iop_sw_cfg_trig2_0
regk_iop_sw_cfg_trig2_1
regk_iop_sw_cfg_trig2_2
regk_iop_sw_cfg_trig2_3
regk_iop_sw_cfg_trig3_0
regk_iop_sw_cfg_trig3_1
regk_iop_sw_cfg_trig3_2
regk_iop_sw_cfg_trig3_3
regk_iop_sw_cfg_trig4_0
regk_iop_sw_cfg_trig4_1
regk_iop_sw_cfg_trig4_2
regk_iop_sw_cfg_trig4_3
regk_iop_sw_cfg_trig5_0
regk_iop_sw_cfg_trig5_1
regk_iop_sw_cfg_trig5_2
regk_iop_sw_cfg_trig5_3
regk_iop_sw_cfg_trig6_0
regk_iop_sw_cfg_trig6_1
regk_iop_sw_cfg_trig6_2
regk_iop_sw_cfg_trig6_3
regk_iop_sw_cfg_trig7_0
regk_iop_sw_cfg_trig7_1
regk_iop_sw_cfg_trig7_2
regk_iop_sw_cfg_trig7_3

Definition at line 722 of file iop_sw_cfg_defs.h.

Data Structures

Macros

Enumerations

Macro Definition Documentation

Enumeration Type Documentation