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iop_sw_cpu_defs.h
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1 #ifndef __iop_sw_cpu_defs_h
2 #define __iop_sw_cpu_defs_h
3 
4 /*
5  * This file is autogenerated from
6  * file: ../../inst/io_proc/rtl/guinness/iop_sw_cpu.r
7  * id: <not found>
8  * last modfied: Mon Apr 11 16:10:19 2005
9  *
10  * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_sw_cpu_defs.h ../../inst/io_proc/rtl/guinness/iop_sw_cpu.r
11  * id: $Id: iop_sw_cpu_defs.h,v 1.4 2005/04/24 18:31:05 starvik Exp $
12  * Any changes here will be lost.
13  *
14  * -*- buffer-read-only: t -*-
15  */
16 /* Main access macros */
17 #ifndef REG_RD
18 #define REG_RD( scope, inst, reg ) \
19  REG_READ( reg_##scope##_##reg, \
20  (inst) + REG_RD_ADDR_##scope##_##reg )
21 #endif
22 
23 #ifndef REG_WR
24 #define REG_WR( scope, inst, reg, val ) \
25  REG_WRITE( reg_##scope##_##reg, \
26  (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
27 #endif
28 
29 #ifndef REG_RD_VECT
30 #define REG_RD_VECT( scope, inst, reg, index ) \
31  REG_READ( reg_##scope##_##reg, \
32  (inst) + REG_RD_ADDR_##scope##_##reg + \
33  (index) * STRIDE_##scope##_##reg )
34 #endif
35 
36 #ifndef REG_WR_VECT
37 #define REG_WR_VECT( scope, inst, reg, index, val ) \
38  REG_WRITE( reg_##scope##_##reg, \
39  (inst) + REG_WR_ADDR_##scope##_##reg + \
40  (index) * STRIDE_##scope##_##reg, (val) )
41 #endif
42 
43 #ifndef REG_RD_INT
44 #define REG_RD_INT( scope, inst, reg ) \
45  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
46 #endif
47 
48 #ifndef REG_WR_INT
49 #define REG_WR_INT( scope, inst, reg, val ) \
50  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
51 #endif
52 
53 #ifndef REG_RD_INT_VECT
54 #define REG_RD_INT_VECT( scope, inst, reg, index ) \
55  REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
56  (index) * STRIDE_##scope##_##reg )
57 #endif
58 
59 #ifndef REG_WR_INT_VECT
60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
61  REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
62  (index) * STRIDE_##scope##_##reg, (val) )
63 #endif
64 
65 #ifndef REG_TYPE_CONV
66 #define REG_TYPE_CONV( type, orgtype, val ) \
67  ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
68 #endif
69 
70 #ifndef reg_page_size
71 #define reg_page_size 8192
72 #endif
73 
74 #ifndef REG_ADDR
75 #define REG_ADDR( scope, inst, reg ) \
76  ( (inst) + REG_RD_ADDR_##scope##_##reg )
77 #endif
78 
79 #ifndef REG_ADDR_VECT
80 #define REG_ADDR_VECT( scope, inst, reg, index ) \
81  ( (inst) + REG_RD_ADDR_##scope##_##reg + \
82  (index) * STRIDE_##scope##_##reg )
83 #endif
84 
85 /* C-code for register scope iop_sw_cpu */
86 
87 /* Register rw_mc_ctrl, scope iop_sw_cpu, type rw */
88 typedef struct {
89  unsigned int keep_owner : 1;
90  unsigned int cmd : 2;
91  unsigned int size : 3;
92  unsigned int wr_spu0_mem : 1;
93  unsigned int wr_spu1_mem : 1;
94  unsigned int dummy1 : 24;
95 } reg_iop_sw_cpu_rw_mc_ctrl;
96 #define REG_RD_ADDR_iop_sw_cpu_rw_mc_ctrl 0
97 #define REG_WR_ADDR_iop_sw_cpu_rw_mc_ctrl 0
98 
99 /* Register rw_mc_data, scope iop_sw_cpu, type rw */
100 typedef struct {
101  unsigned int val : 32;
102 } reg_iop_sw_cpu_rw_mc_data;
103 #define REG_RD_ADDR_iop_sw_cpu_rw_mc_data 4
104 #define REG_WR_ADDR_iop_sw_cpu_rw_mc_data 4
105 
106 /* Register rw_mc_addr, scope iop_sw_cpu, type rw */
107 typedef unsigned int reg_iop_sw_cpu_rw_mc_addr;
108 #define REG_RD_ADDR_iop_sw_cpu_rw_mc_addr 8
109 #define REG_WR_ADDR_iop_sw_cpu_rw_mc_addr 8
110 
111 /* Register rs_mc_data, scope iop_sw_cpu, type rs */
112 typedef unsigned int reg_iop_sw_cpu_rs_mc_data;
113 #define REG_RD_ADDR_iop_sw_cpu_rs_mc_data 12
114 
115 /* Register r_mc_data, scope iop_sw_cpu, type r */
116 typedef unsigned int reg_iop_sw_cpu_r_mc_data;
117 #define REG_RD_ADDR_iop_sw_cpu_r_mc_data 16
118 
119 /* Register r_mc_stat, scope iop_sw_cpu, type r */
120 typedef struct {
121  unsigned int busy_cpu : 1;
122  unsigned int busy_mpu : 1;
123  unsigned int busy_spu0 : 1;
124  unsigned int busy_spu1 : 1;
125  unsigned int owned_by_cpu : 1;
126  unsigned int owned_by_mpu : 1;
127  unsigned int owned_by_spu0 : 1;
128  unsigned int owned_by_spu1 : 1;
129  unsigned int dummy1 : 24;
130 } reg_iop_sw_cpu_r_mc_stat;
131 #define REG_RD_ADDR_iop_sw_cpu_r_mc_stat 20
132 
133 /* Register rw_bus0_clr_mask, scope iop_sw_cpu, type rw */
134 typedef struct {
135  unsigned int byte0 : 8;
136  unsigned int byte1 : 8;
137  unsigned int byte2 : 8;
138  unsigned int byte3 : 8;
139 } reg_iop_sw_cpu_rw_bus0_clr_mask;
140 #define REG_RD_ADDR_iop_sw_cpu_rw_bus0_clr_mask 24
141 #define REG_WR_ADDR_iop_sw_cpu_rw_bus0_clr_mask 24
142 
143 /* Register rw_bus0_set_mask, scope iop_sw_cpu, type rw */
144 typedef struct {
145  unsigned int byte0 : 8;
146  unsigned int byte1 : 8;
147  unsigned int byte2 : 8;
148  unsigned int byte3 : 8;
149 } reg_iop_sw_cpu_rw_bus0_set_mask;
150 #define REG_RD_ADDR_iop_sw_cpu_rw_bus0_set_mask 28
151 #define REG_WR_ADDR_iop_sw_cpu_rw_bus0_set_mask 28
152 
153 /* Register rw_bus0_oe_clr_mask, scope iop_sw_cpu, type rw */
154 typedef struct {
155  unsigned int byte0 : 1;
156  unsigned int byte1 : 1;
157  unsigned int byte2 : 1;
158  unsigned int byte3 : 1;
159  unsigned int dummy1 : 28;
160 } reg_iop_sw_cpu_rw_bus0_oe_clr_mask;
161 #define REG_RD_ADDR_iop_sw_cpu_rw_bus0_oe_clr_mask 32
162 #define REG_WR_ADDR_iop_sw_cpu_rw_bus0_oe_clr_mask 32
163 
164 /* Register rw_bus0_oe_set_mask, scope iop_sw_cpu, type rw */
165 typedef struct {
166  unsigned int byte0 : 1;
167  unsigned int byte1 : 1;
168  unsigned int byte2 : 1;
169  unsigned int byte3 : 1;
170  unsigned int dummy1 : 28;
171 } reg_iop_sw_cpu_rw_bus0_oe_set_mask;
172 #define REG_RD_ADDR_iop_sw_cpu_rw_bus0_oe_set_mask 36
173 #define REG_WR_ADDR_iop_sw_cpu_rw_bus0_oe_set_mask 36
174 
175 /* Register r_bus0_in, scope iop_sw_cpu, type r */
176 typedef unsigned int reg_iop_sw_cpu_r_bus0_in;
177 #define REG_RD_ADDR_iop_sw_cpu_r_bus0_in 40
178 
179 /* Register rw_bus1_clr_mask, scope iop_sw_cpu, type rw */
180 typedef struct {
181  unsigned int byte0 : 8;
182  unsigned int byte1 : 8;
183  unsigned int byte2 : 8;
184  unsigned int byte3 : 8;
185 } reg_iop_sw_cpu_rw_bus1_clr_mask;
186 #define REG_RD_ADDR_iop_sw_cpu_rw_bus1_clr_mask 44
187 #define REG_WR_ADDR_iop_sw_cpu_rw_bus1_clr_mask 44
188 
189 /* Register rw_bus1_set_mask, scope iop_sw_cpu, type rw */
190 typedef struct {
191  unsigned int byte0 : 8;
192  unsigned int byte1 : 8;
193  unsigned int byte2 : 8;
194  unsigned int byte3 : 8;
195 } reg_iop_sw_cpu_rw_bus1_set_mask;
196 #define REG_RD_ADDR_iop_sw_cpu_rw_bus1_set_mask 48
197 #define REG_WR_ADDR_iop_sw_cpu_rw_bus1_set_mask 48
198 
199 /* Register rw_bus1_oe_clr_mask, scope iop_sw_cpu, type rw */
200 typedef struct {
201  unsigned int byte0 : 1;
202  unsigned int byte1 : 1;
203  unsigned int byte2 : 1;
204  unsigned int byte3 : 1;
205  unsigned int dummy1 : 28;
206 } reg_iop_sw_cpu_rw_bus1_oe_clr_mask;
207 #define REG_RD_ADDR_iop_sw_cpu_rw_bus1_oe_clr_mask 52
208 #define REG_WR_ADDR_iop_sw_cpu_rw_bus1_oe_clr_mask 52
209 
210 /* Register rw_bus1_oe_set_mask, scope iop_sw_cpu, type rw */
211 typedef struct {
212  unsigned int byte0 : 1;
213  unsigned int byte1 : 1;
214  unsigned int byte2 : 1;
215  unsigned int byte3 : 1;
216  unsigned int dummy1 : 28;
217 } reg_iop_sw_cpu_rw_bus1_oe_set_mask;
218 #define REG_RD_ADDR_iop_sw_cpu_rw_bus1_oe_set_mask 56
219 #define REG_WR_ADDR_iop_sw_cpu_rw_bus1_oe_set_mask 56
220 
221 /* Register r_bus1_in, scope iop_sw_cpu, type r */
222 typedef unsigned int reg_iop_sw_cpu_r_bus1_in;
223 #define REG_RD_ADDR_iop_sw_cpu_r_bus1_in 60
224 
225 /* Register rw_gio_clr_mask, scope iop_sw_cpu, type rw */
226 typedef struct {
227  unsigned int val : 32;
228 } reg_iop_sw_cpu_rw_gio_clr_mask;
229 #define REG_RD_ADDR_iop_sw_cpu_rw_gio_clr_mask 64
230 #define REG_WR_ADDR_iop_sw_cpu_rw_gio_clr_mask 64
231 
232 /* Register rw_gio_set_mask, scope iop_sw_cpu, type rw */
233 typedef struct {
234  unsigned int val : 32;
235 } reg_iop_sw_cpu_rw_gio_set_mask;
236 #define REG_RD_ADDR_iop_sw_cpu_rw_gio_set_mask 68
237 #define REG_WR_ADDR_iop_sw_cpu_rw_gio_set_mask 68
238 
239 /* Register rw_gio_oe_clr_mask, scope iop_sw_cpu, type rw */
240 typedef struct {
241  unsigned int val : 32;
242 } reg_iop_sw_cpu_rw_gio_oe_clr_mask;
243 #define REG_RD_ADDR_iop_sw_cpu_rw_gio_oe_clr_mask 72
244 #define REG_WR_ADDR_iop_sw_cpu_rw_gio_oe_clr_mask 72
245 
246 /* Register rw_gio_oe_set_mask, scope iop_sw_cpu, type rw */
247 typedef struct {
248  unsigned int val : 32;
249 } reg_iop_sw_cpu_rw_gio_oe_set_mask;
250 #define REG_RD_ADDR_iop_sw_cpu_rw_gio_oe_set_mask 76
251 #define REG_WR_ADDR_iop_sw_cpu_rw_gio_oe_set_mask 76
252 
253 /* Register r_gio_in, scope iop_sw_cpu, type r */
254 typedef unsigned int reg_iop_sw_cpu_r_gio_in;
255 #define REG_RD_ADDR_iop_sw_cpu_r_gio_in 80
256 
257 /* Register rw_intr0_mask, scope iop_sw_cpu, type rw */
258 typedef struct {
259  unsigned int mpu_0 : 1;
260  unsigned int mpu_1 : 1;
261  unsigned int mpu_2 : 1;
262  unsigned int mpu_3 : 1;
263  unsigned int mpu_4 : 1;
264  unsigned int mpu_5 : 1;
265  unsigned int mpu_6 : 1;
266  unsigned int mpu_7 : 1;
267  unsigned int mpu_8 : 1;
268  unsigned int mpu_9 : 1;
269  unsigned int mpu_10 : 1;
270  unsigned int mpu_11 : 1;
271  unsigned int mpu_12 : 1;
272  unsigned int mpu_13 : 1;
273  unsigned int mpu_14 : 1;
274  unsigned int mpu_15 : 1;
275  unsigned int spu0_0 : 1;
276  unsigned int spu0_1 : 1;
277  unsigned int spu0_2 : 1;
278  unsigned int spu0_3 : 1;
279  unsigned int spu0_4 : 1;
280  unsigned int spu0_5 : 1;
281  unsigned int spu0_6 : 1;
282  unsigned int spu0_7 : 1;
283  unsigned int spu1_8 : 1;
284  unsigned int spu1_9 : 1;
285  unsigned int spu1_10 : 1;
286  unsigned int spu1_11 : 1;
287  unsigned int spu1_12 : 1;
288  unsigned int spu1_13 : 1;
289  unsigned int spu1_14 : 1;
290  unsigned int spu1_15 : 1;
291 } reg_iop_sw_cpu_rw_intr0_mask;
292 #define REG_RD_ADDR_iop_sw_cpu_rw_intr0_mask 84
293 #define REG_WR_ADDR_iop_sw_cpu_rw_intr0_mask 84
294 
295 /* Register rw_ack_intr0, scope iop_sw_cpu, type rw */
296 typedef struct {
297  unsigned int mpu_0 : 1;
298  unsigned int mpu_1 : 1;
299  unsigned int mpu_2 : 1;
300  unsigned int mpu_3 : 1;
301  unsigned int mpu_4 : 1;
302  unsigned int mpu_5 : 1;
303  unsigned int mpu_6 : 1;
304  unsigned int mpu_7 : 1;
305  unsigned int mpu_8 : 1;
306  unsigned int mpu_9 : 1;
307  unsigned int mpu_10 : 1;
308  unsigned int mpu_11 : 1;
309  unsigned int mpu_12 : 1;
310  unsigned int mpu_13 : 1;
311  unsigned int mpu_14 : 1;
312  unsigned int mpu_15 : 1;
313  unsigned int spu0_0 : 1;
314  unsigned int spu0_1 : 1;
315  unsigned int spu0_2 : 1;
316  unsigned int spu0_3 : 1;
317  unsigned int spu0_4 : 1;
318  unsigned int spu0_5 : 1;
319  unsigned int spu0_6 : 1;
320  unsigned int spu0_7 : 1;
321  unsigned int spu1_8 : 1;
322  unsigned int spu1_9 : 1;
323  unsigned int spu1_10 : 1;
324  unsigned int spu1_11 : 1;
325  unsigned int spu1_12 : 1;
326  unsigned int spu1_13 : 1;
327  unsigned int spu1_14 : 1;
328  unsigned int spu1_15 : 1;
329 } reg_iop_sw_cpu_rw_ack_intr0;
330 #define REG_RD_ADDR_iop_sw_cpu_rw_ack_intr0 88
331 #define REG_WR_ADDR_iop_sw_cpu_rw_ack_intr0 88
332 
333 /* Register r_intr0, scope iop_sw_cpu, type r */
334 typedef struct {
335  unsigned int mpu_0 : 1;
336  unsigned int mpu_1 : 1;
337  unsigned int mpu_2 : 1;
338  unsigned int mpu_3 : 1;
339  unsigned int mpu_4 : 1;
340  unsigned int mpu_5 : 1;
341  unsigned int mpu_6 : 1;
342  unsigned int mpu_7 : 1;
343  unsigned int mpu_8 : 1;
344  unsigned int mpu_9 : 1;
345  unsigned int mpu_10 : 1;
346  unsigned int mpu_11 : 1;
347  unsigned int mpu_12 : 1;
348  unsigned int mpu_13 : 1;
349  unsigned int mpu_14 : 1;
350  unsigned int mpu_15 : 1;
351  unsigned int spu0_0 : 1;
352  unsigned int spu0_1 : 1;
353  unsigned int spu0_2 : 1;
354  unsigned int spu0_3 : 1;
355  unsigned int spu0_4 : 1;
356  unsigned int spu0_5 : 1;
357  unsigned int spu0_6 : 1;
358  unsigned int spu0_7 : 1;
359  unsigned int spu1_8 : 1;
360  unsigned int spu1_9 : 1;
361  unsigned int spu1_10 : 1;
362  unsigned int spu1_11 : 1;
363  unsigned int spu1_12 : 1;
364  unsigned int spu1_13 : 1;
365  unsigned int spu1_14 : 1;
366  unsigned int spu1_15 : 1;
367 } reg_iop_sw_cpu_r_intr0;
368 #define REG_RD_ADDR_iop_sw_cpu_r_intr0 92
369 
370 /* Register r_masked_intr0, scope iop_sw_cpu, type r */
371 typedef struct {
372  unsigned int mpu_0 : 1;
373  unsigned int mpu_1 : 1;
374  unsigned int mpu_2 : 1;
375  unsigned int mpu_3 : 1;
376  unsigned int mpu_4 : 1;
377  unsigned int mpu_5 : 1;
378  unsigned int mpu_6 : 1;
379  unsigned int mpu_7 : 1;
380  unsigned int mpu_8 : 1;
381  unsigned int mpu_9 : 1;
382  unsigned int mpu_10 : 1;
383  unsigned int mpu_11 : 1;
384  unsigned int mpu_12 : 1;
385  unsigned int mpu_13 : 1;
386  unsigned int mpu_14 : 1;
387  unsigned int mpu_15 : 1;
388  unsigned int spu0_0 : 1;
389  unsigned int spu0_1 : 1;
390  unsigned int spu0_2 : 1;
391  unsigned int spu0_3 : 1;
392  unsigned int spu0_4 : 1;
393  unsigned int spu0_5 : 1;
394  unsigned int spu0_6 : 1;
395  unsigned int spu0_7 : 1;
396  unsigned int spu1_8 : 1;
397  unsigned int spu1_9 : 1;
398  unsigned int spu1_10 : 1;
399  unsigned int spu1_11 : 1;
400  unsigned int spu1_12 : 1;
401  unsigned int spu1_13 : 1;
402  unsigned int spu1_14 : 1;
403  unsigned int spu1_15 : 1;
404 } reg_iop_sw_cpu_r_masked_intr0;
405 #define REG_RD_ADDR_iop_sw_cpu_r_masked_intr0 96
406 
407 /* Register rw_intr1_mask, scope iop_sw_cpu, type rw */
408 typedef struct {
409  unsigned int mpu_16 : 1;
410  unsigned int mpu_17 : 1;
411  unsigned int mpu_18 : 1;
412  unsigned int mpu_19 : 1;
413  unsigned int mpu_20 : 1;
414  unsigned int mpu_21 : 1;
415  unsigned int mpu_22 : 1;
416  unsigned int mpu_23 : 1;
417  unsigned int mpu_24 : 1;
418  unsigned int mpu_25 : 1;
419  unsigned int mpu_26 : 1;
420  unsigned int mpu_27 : 1;
421  unsigned int mpu_28 : 1;
422  unsigned int mpu_29 : 1;
423  unsigned int mpu_30 : 1;
424  unsigned int mpu_31 : 1;
425  unsigned int spu0_8 : 1;
426  unsigned int spu0_9 : 1;
427  unsigned int spu0_10 : 1;
428  unsigned int spu0_11 : 1;
429  unsigned int spu0_12 : 1;
430  unsigned int spu0_13 : 1;
431  unsigned int spu0_14 : 1;
432  unsigned int spu0_15 : 1;
433  unsigned int spu1_0 : 1;
434  unsigned int spu1_1 : 1;
435  unsigned int spu1_2 : 1;
436  unsigned int spu1_3 : 1;
437  unsigned int spu1_4 : 1;
438  unsigned int spu1_5 : 1;
439  unsigned int spu1_6 : 1;
440  unsigned int spu1_7 : 1;
441 } reg_iop_sw_cpu_rw_intr1_mask;
442 #define REG_RD_ADDR_iop_sw_cpu_rw_intr1_mask 100
443 #define REG_WR_ADDR_iop_sw_cpu_rw_intr1_mask 100
444 
445 /* Register rw_ack_intr1, scope iop_sw_cpu, type rw */
446 typedef struct {
447  unsigned int mpu_16 : 1;
448  unsigned int mpu_17 : 1;
449  unsigned int mpu_18 : 1;
450  unsigned int mpu_19 : 1;
451  unsigned int mpu_20 : 1;
452  unsigned int mpu_21 : 1;
453  unsigned int mpu_22 : 1;
454  unsigned int mpu_23 : 1;
455  unsigned int mpu_24 : 1;
456  unsigned int mpu_25 : 1;
457  unsigned int mpu_26 : 1;
458  unsigned int mpu_27 : 1;
459  unsigned int mpu_28 : 1;
460  unsigned int mpu_29 : 1;
461  unsigned int mpu_30 : 1;
462  unsigned int mpu_31 : 1;
463  unsigned int spu0_8 : 1;
464  unsigned int spu0_9 : 1;
465  unsigned int spu0_10 : 1;
466  unsigned int spu0_11 : 1;
467  unsigned int spu0_12 : 1;
468  unsigned int spu0_13 : 1;
469  unsigned int spu0_14 : 1;
470  unsigned int spu0_15 : 1;
471  unsigned int spu1_0 : 1;
472  unsigned int spu1_1 : 1;
473  unsigned int spu1_2 : 1;
474  unsigned int spu1_3 : 1;
475  unsigned int spu1_4 : 1;
476  unsigned int spu1_5 : 1;
477  unsigned int spu1_6 : 1;
478  unsigned int spu1_7 : 1;
479 } reg_iop_sw_cpu_rw_ack_intr1;
480 #define REG_RD_ADDR_iop_sw_cpu_rw_ack_intr1 104
481 #define REG_WR_ADDR_iop_sw_cpu_rw_ack_intr1 104
482 
483 /* Register r_intr1, scope iop_sw_cpu, type r */
484 typedef struct {
485  unsigned int mpu_16 : 1;
486  unsigned int mpu_17 : 1;
487  unsigned int mpu_18 : 1;
488  unsigned int mpu_19 : 1;
489  unsigned int mpu_20 : 1;
490  unsigned int mpu_21 : 1;
491  unsigned int mpu_22 : 1;
492  unsigned int mpu_23 : 1;
493  unsigned int mpu_24 : 1;
494  unsigned int mpu_25 : 1;
495  unsigned int mpu_26 : 1;
496  unsigned int mpu_27 : 1;
497  unsigned int mpu_28 : 1;
498  unsigned int mpu_29 : 1;
499  unsigned int mpu_30 : 1;
500  unsigned int mpu_31 : 1;
501  unsigned int spu0_8 : 1;
502  unsigned int spu0_9 : 1;
503  unsigned int spu0_10 : 1;
504  unsigned int spu0_11 : 1;
505  unsigned int spu0_12 : 1;
506  unsigned int spu0_13 : 1;
507  unsigned int spu0_14 : 1;
508  unsigned int spu0_15 : 1;
509  unsigned int spu1_0 : 1;
510  unsigned int spu1_1 : 1;
511  unsigned int spu1_2 : 1;
512  unsigned int spu1_3 : 1;
513  unsigned int spu1_4 : 1;
514  unsigned int spu1_5 : 1;
515  unsigned int spu1_6 : 1;
516  unsigned int spu1_7 : 1;
517 } reg_iop_sw_cpu_r_intr1;
518 #define REG_RD_ADDR_iop_sw_cpu_r_intr1 108
519 
520 /* Register r_masked_intr1, scope iop_sw_cpu, type r */
521 typedef struct {
522  unsigned int mpu_16 : 1;
523  unsigned int mpu_17 : 1;
524  unsigned int mpu_18 : 1;
525  unsigned int mpu_19 : 1;
526  unsigned int mpu_20 : 1;
527  unsigned int mpu_21 : 1;
528  unsigned int mpu_22 : 1;
529  unsigned int mpu_23 : 1;
530  unsigned int mpu_24 : 1;
531  unsigned int mpu_25 : 1;
532  unsigned int mpu_26 : 1;
533  unsigned int mpu_27 : 1;
534  unsigned int mpu_28 : 1;
535  unsigned int mpu_29 : 1;
536  unsigned int mpu_30 : 1;
537  unsigned int mpu_31 : 1;
538  unsigned int spu0_8 : 1;
539  unsigned int spu0_9 : 1;
540  unsigned int spu0_10 : 1;
541  unsigned int spu0_11 : 1;
542  unsigned int spu0_12 : 1;
543  unsigned int spu0_13 : 1;
544  unsigned int spu0_14 : 1;
545  unsigned int spu0_15 : 1;
546  unsigned int spu1_0 : 1;
547  unsigned int spu1_1 : 1;
548  unsigned int spu1_2 : 1;
549  unsigned int spu1_3 : 1;
550  unsigned int spu1_4 : 1;
551  unsigned int spu1_5 : 1;
552  unsigned int spu1_6 : 1;
553  unsigned int spu1_7 : 1;
554 } reg_iop_sw_cpu_r_masked_intr1;
555 #define REG_RD_ADDR_iop_sw_cpu_r_masked_intr1 112
556 
557 /* Register rw_intr2_mask, scope iop_sw_cpu, type rw */
558 typedef struct {
559  unsigned int mpu_0 : 1;
560  unsigned int mpu_1 : 1;
561  unsigned int mpu_2 : 1;
562  unsigned int mpu_3 : 1;
563  unsigned int mpu_4 : 1;
564  unsigned int mpu_5 : 1;
565  unsigned int mpu_6 : 1;
566  unsigned int mpu_7 : 1;
567  unsigned int spu0_0 : 1;
568  unsigned int spu0_1 : 1;
569  unsigned int spu0_2 : 1;
570  unsigned int spu0_3 : 1;
571  unsigned int spu0_4 : 1;
572  unsigned int spu0_5 : 1;
573  unsigned int spu0_6 : 1;
574  unsigned int spu0_7 : 1;
575  unsigned int dmc_in0 : 1;
576  unsigned int dmc_out0 : 1;
577  unsigned int fifo_in0 : 1;
578  unsigned int fifo_out0 : 1;
579  unsigned int fifo_in0_extra : 1;
580  unsigned int fifo_out0_extra : 1;
581  unsigned int trigger_grp0 : 1;
582  unsigned int trigger_grp1 : 1;
583  unsigned int trigger_grp2 : 1;
584  unsigned int trigger_grp3 : 1;
585  unsigned int trigger_grp4 : 1;
586  unsigned int trigger_grp5 : 1;
587  unsigned int trigger_grp6 : 1;
588  unsigned int trigger_grp7 : 1;
589  unsigned int timer_grp0 : 1;
590  unsigned int timer_grp1 : 1;
591 } reg_iop_sw_cpu_rw_intr2_mask;
592 #define REG_RD_ADDR_iop_sw_cpu_rw_intr2_mask 116
593 #define REG_WR_ADDR_iop_sw_cpu_rw_intr2_mask 116
594 
595 /* Register rw_ack_intr2, scope iop_sw_cpu, type rw */
596 typedef struct {
597  unsigned int mpu_0 : 1;
598  unsigned int mpu_1 : 1;
599  unsigned int mpu_2 : 1;
600  unsigned int mpu_3 : 1;
601  unsigned int mpu_4 : 1;
602  unsigned int mpu_5 : 1;
603  unsigned int mpu_6 : 1;
604  unsigned int mpu_7 : 1;
605  unsigned int spu0_0 : 1;
606  unsigned int spu0_1 : 1;
607  unsigned int spu0_2 : 1;
608  unsigned int spu0_3 : 1;
609  unsigned int spu0_4 : 1;
610  unsigned int spu0_5 : 1;
611  unsigned int spu0_6 : 1;
612  unsigned int spu0_7 : 1;
613  unsigned int dummy1 : 16;
614 } reg_iop_sw_cpu_rw_ack_intr2;
615 #define REG_RD_ADDR_iop_sw_cpu_rw_ack_intr2 120
616 #define REG_WR_ADDR_iop_sw_cpu_rw_ack_intr2 120
617 
618 /* Register r_intr2, scope iop_sw_cpu, type r */
619 typedef struct {
620  unsigned int mpu_0 : 1;
621  unsigned int mpu_1 : 1;
622  unsigned int mpu_2 : 1;
623  unsigned int mpu_3 : 1;
624  unsigned int mpu_4 : 1;
625  unsigned int mpu_5 : 1;
626  unsigned int mpu_6 : 1;
627  unsigned int mpu_7 : 1;
628  unsigned int spu0_0 : 1;
629  unsigned int spu0_1 : 1;
630  unsigned int spu0_2 : 1;
631  unsigned int spu0_3 : 1;
632  unsigned int spu0_4 : 1;
633  unsigned int spu0_5 : 1;
634  unsigned int spu0_6 : 1;
635  unsigned int spu0_7 : 1;
636  unsigned int dmc_in0 : 1;
637  unsigned int dmc_out0 : 1;
638  unsigned int fifo_in0 : 1;
639  unsigned int fifo_out0 : 1;
640  unsigned int fifo_in0_extra : 1;
641  unsigned int fifo_out0_extra : 1;
642  unsigned int trigger_grp0 : 1;
643  unsigned int trigger_grp1 : 1;
644  unsigned int trigger_grp2 : 1;
645  unsigned int trigger_grp3 : 1;
646  unsigned int trigger_grp4 : 1;
647  unsigned int trigger_grp5 : 1;
648  unsigned int trigger_grp6 : 1;
649  unsigned int trigger_grp7 : 1;
650  unsigned int timer_grp0 : 1;
651  unsigned int timer_grp1 : 1;
652 } reg_iop_sw_cpu_r_intr2;
653 #define REG_RD_ADDR_iop_sw_cpu_r_intr2 124
654 
655 /* Register r_masked_intr2, scope iop_sw_cpu, type r */
656 typedef struct {
657  unsigned int mpu_0 : 1;
658  unsigned int mpu_1 : 1;
659  unsigned int mpu_2 : 1;
660  unsigned int mpu_3 : 1;
661  unsigned int mpu_4 : 1;
662  unsigned int mpu_5 : 1;
663  unsigned int mpu_6 : 1;
664  unsigned int mpu_7 : 1;
665  unsigned int spu0_0 : 1;
666  unsigned int spu0_1 : 1;
667  unsigned int spu0_2 : 1;
668  unsigned int spu0_3 : 1;
669  unsigned int spu0_4 : 1;
670  unsigned int spu0_5 : 1;
671  unsigned int spu0_6 : 1;
672  unsigned int spu0_7 : 1;
673  unsigned int dmc_in0 : 1;
674  unsigned int dmc_out0 : 1;
675  unsigned int fifo_in0 : 1;
676  unsigned int fifo_out0 : 1;
677  unsigned int fifo_in0_extra : 1;
678  unsigned int fifo_out0_extra : 1;
679  unsigned int trigger_grp0 : 1;
680  unsigned int trigger_grp1 : 1;
681  unsigned int trigger_grp2 : 1;
682  unsigned int trigger_grp3 : 1;
683  unsigned int trigger_grp4 : 1;
684  unsigned int trigger_grp5 : 1;
685  unsigned int trigger_grp6 : 1;
686  unsigned int trigger_grp7 : 1;
687  unsigned int timer_grp0 : 1;
688  unsigned int timer_grp1 : 1;
689 } reg_iop_sw_cpu_r_masked_intr2;
690 #define REG_RD_ADDR_iop_sw_cpu_r_masked_intr2 128
691 
692 /* Register rw_intr3_mask, scope iop_sw_cpu, type rw */
693 typedef struct {
694  unsigned int mpu_16 : 1;
695  unsigned int mpu_17 : 1;
696  unsigned int mpu_18 : 1;
697  unsigned int mpu_19 : 1;
698  unsigned int mpu_20 : 1;
699  unsigned int mpu_21 : 1;
700  unsigned int mpu_22 : 1;
701  unsigned int mpu_23 : 1;
702  unsigned int spu1_0 : 1;
703  unsigned int spu1_1 : 1;
704  unsigned int spu1_2 : 1;
705  unsigned int spu1_3 : 1;
706  unsigned int spu1_4 : 1;
707  unsigned int spu1_5 : 1;
708  unsigned int spu1_6 : 1;
709  unsigned int spu1_7 : 1;
710  unsigned int dmc_in1 : 1;
711  unsigned int dmc_out1 : 1;
712  unsigned int fifo_in1 : 1;
713  unsigned int fifo_out1 : 1;
714  unsigned int fifo_in1_extra : 1;
715  unsigned int fifo_out1_extra : 1;
716  unsigned int trigger_grp0 : 1;
717  unsigned int trigger_grp1 : 1;
718  unsigned int trigger_grp2 : 1;
719  unsigned int trigger_grp3 : 1;
720  unsigned int trigger_grp4 : 1;
721  unsigned int trigger_grp5 : 1;
722  unsigned int trigger_grp6 : 1;
723  unsigned int trigger_grp7 : 1;
724  unsigned int timer_grp2 : 1;
725  unsigned int timer_grp3 : 1;
726 } reg_iop_sw_cpu_rw_intr3_mask;
727 #define REG_RD_ADDR_iop_sw_cpu_rw_intr3_mask 132
728 #define REG_WR_ADDR_iop_sw_cpu_rw_intr3_mask 132
729 
730 /* Register rw_ack_intr3, scope iop_sw_cpu, type rw */
731 typedef struct {
732  unsigned int mpu_16 : 1;
733  unsigned int mpu_17 : 1;
734  unsigned int mpu_18 : 1;
735  unsigned int mpu_19 : 1;
736  unsigned int mpu_20 : 1;
737  unsigned int mpu_21 : 1;
738  unsigned int mpu_22 : 1;
739  unsigned int mpu_23 : 1;
740  unsigned int spu1_0 : 1;
741  unsigned int spu1_1 : 1;
742  unsigned int spu1_2 : 1;
743  unsigned int spu1_3 : 1;
744  unsigned int spu1_4 : 1;
745  unsigned int spu1_5 : 1;
746  unsigned int spu1_6 : 1;
747  unsigned int spu1_7 : 1;
748  unsigned int dummy1 : 16;
749 } reg_iop_sw_cpu_rw_ack_intr3;
750 #define REG_RD_ADDR_iop_sw_cpu_rw_ack_intr3 136
751 #define REG_WR_ADDR_iop_sw_cpu_rw_ack_intr3 136
752 
753 /* Register r_intr3, scope iop_sw_cpu, type r */
754 typedef struct {
755  unsigned int mpu_16 : 1;
756  unsigned int mpu_17 : 1;
757  unsigned int mpu_18 : 1;
758  unsigned int mpu_19 : 1;
759  unsigned int mpu_20 : 1;
760  unsigned int mpu_21 : 1;
761  unsigned int mpu_22 : 1;
762  unsigned int mpu_23 : 1;
763  unsigned int spu1_0 : 1;
764  unsigned int spu1_1 : 1;
765  unsigned int spu1_2 : 1;
766  unsigned int spu1_3 : 1;
767  unsigned int spu1_4 : 1;
768  unsigned int spu1_5 : 1;
769  unsigned int spu1_6 : 1;
770  unsigned int spu1_7 : 1;
771  unsigned int dmc_in1 : 1;
772  unsigned int dmc_out1 : 1;
773  unsigned int fifo_in1 : 1;
774  unsigned int fifo_out1 : 1;
775  unsigned int fifo_in1_extra : 1;
776  unsigned int fifo_out1_extra : 1;
777  unsigned int trigger_grp0 : 1;
778  unsigned int trigger_grp1 : 1;
779  unsigned int trigger_grp2 : 1;
780  unsigned int trigger_grp3 : 1;
781  unsigned int trigger_grp4 : 1;
782  unsigned int trigger_grp5 : 1;
783  unsigned int trigger_grp6 : 1;
784  unsigned int trigger_grp7 : 1;
785  unsigned int timer_grp2 : 1;
786  unsigned int timer_grp3 : 1;
787 } reg_iop_sw_cpu_r_intr3;
788 #define REG_RD_ADDR_iop_sw_cpu_r_intr3 140
789 
790 /* Register r_masked_intr3, scope iop_sw_cpu, type r */
791 typedef struct {
792  unsigned int mpu_16 : 1;
793  unsigned int mpu_17 : 1;
794  unsigned int mpu_18 : 1;
795  unsigned int mpu_19 : 1;
796  unsigned int mpu_20 : 1;
797  unsigned int mpu_21 : 1;
798  unsigned int mpu_22 : 1;
799  unsigned int mpu_23 : 1;
800  unsigned int spu1_0 : 1;
801  unsigned int spu1_1 : 1;
802  unsigned int spu1_2 : 1;
803  unsigned int spu1_3 : 1;
804  unsigned int spu1_4 : 1;
805  unsigned int spu1_5 : 1;
806  unsigned int spu1_6 : 1;
807  unsigned int spu1_7 : 1;
808  unsigned int dmc_in1 : 1;
809  unsigned int dmc_out1 : 1;
810  unsigned int fifo_in1 : 1;
811  unsigned int fifo_out1 : 1;
812  unsigned int fifo_in1_extra : 1;
813  unsigned int fifo_out1_extra : 1;
814  unsigned int trigger_grp0 : 1;
815  unsigned int trigger_grp1 : 1;
816  unsigned int trigger_grp2 : 1;
817  unsigned int trigger_grp3 : 1;
818  unsigned int trigger_grp4 : 1;
819  unsigned int trigger_grp5 : 1;
820  unsigned int trigger_grp6 : 1;
821  unsigned int trigger_grp7 : 1;
822  unsigned int timer_grp2 : 1;
823  unsigned int timer_grp3 : 1;
824 } reg_iop_sw_cpu_r_masked_intr3;
825 #define REG_RD_ADDR_iop_sw_cpu_r_masked_intr3 144
826 
827 
828 /* Constants */
829 enum {
830  regk_iop_sw_cpu_copy = 0x00000000,
831  regk_iop_sw_cpu_no = 0x00000000,
832  regk_iop_sw_cpu_rd = 0x00000002,
833  regk_iop_sw_cpu_reg_copy = 0x00000001,
834  regk_iop_sw_cpu_rw_bus0_clr_mask_default = 0x00000000,
835  regk_iop_sw_cpu_rw_bus0_oe_clr_mask_default = 0x00000000,
836  regk_iop_sw_cpu_rw_bus0_oe_set_mask_default = 0x00000000,
837  regk_iop_sw_cpu_rw_bus0_set_mask_default = 0x00000000,
838  regk_iop_sw_cpu_rw_bus1_clr_mask_default = 0x00000000,
839  regk_iop_sw_cpu_rw_bus1_oe_clr_mask_default = 0x00000000,
840  regk_iop_sw_cpu_rw_bus1_oe_set_mask_default = 0x00000000,
841  regk_iop_sw_cpu_rw_bus1_set_mask_default = 0x00000000,
842  regk_iop_sw_cpu_rw_gio_clr_mask_default = 0x00000000,
843  regk_iop_sw_cpu_rw_gio_oe_clr_mask_default = 0x00000000,
844  regk_iop_sw_cpu_rw_gio_oe_set_mask_default = 0x00000000,
845  regk_iop_sw_cpu_rw_gio_set_mask_default = 0x00000000,
846  regk_iop_sw_cpu_rw_intr0_mask_default = 0x00000000,
847  regk_iop_sw_cpu_rw_intr1_mask_default = 0x00000000,
848  regk_iop_sw_cpu_rw_intr2_mask_default = 0x00000000,
849  regk_iop_sw_cpu_rw_intr3_mask_default = 0x00000000,
850  regk_iop_sw_cpu_wr = 0x00000003,
851  regk_iop_sw_cpu_yes = 0x00000001
852 };
853 #endif /* __iop_sw_cpu_defs_h */
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