iop_sw_cpu_defs.h File Reference

Go to the source code of this file.

Data Structures
struct	reg_iop_sw_cpu_rw_mc_ctrl
struct	reg_iop_sw_cpu_rw_mc_data
struct	reg_iop_sw_cpu_r_mc_stat
struct	reg_iop_sw_cpu_rw_bus0_clr_mask
struct	reg_iop_sw_cpu_rw_bus0_set_mask
struct	reg_iop_sw_cpu_rw_bus0_oe_clr_mask
struct	reg_iop_sw_cpu_rw_bus0_oe_set_mask
struct	reg_iop_sw_cpu_rw_bus1_clr_mask
struct	reg_iop_sw_cpu_rw_bus1_set_mask
struct	reg_iop_sw_cpu_rw_bus1_oe_clr_mask
struct	reg_iop_sw_cpu_rw_bus1_oe_set_mask
struct	reg_iop_sw_cpu_rw_gio_clr_mask
struct	reg_iop_sw_cpu_rw_gio_set_mask
struct	reg_iop_sw_cpu_rw_gio_oe_clr_mask
struct	reg_iop_sw_cpu_rw_gio_oe_set_mask
struct	reg_iop_sw_cpu_rw_intr0_mask
struct	reg_iop_sw_cpu_rw_ack_intr0
struct	reg_iop_sw_cpu_r_intr0
struct	reg_iop_sw_cpu_r_masked_intr0
struct	reg_iop_sw_cpu_rw_intr1_mask
struct	reg_iop_sw_cpu_rw_ack_intr1
struct	reg_iop_sw_cpu_r_intr1
struct	reg_iop_sw_cpu_r_masked_intr1
struct	reg_iop_sw_cpu_rw_intr2_mask
struct	reg_iop_sw_cpu_rw_ack_intr2
struct	reg_iop_sw_cpu_r_intr2
struct	reg_iop_sw_cpu_r_masked_intr2
struct	reg_iop_sw_cpu_rw_intr3_mask
struct	reg_iop_sw_cpu_rw_ack_intr3
struct	reg_iop_sw_cpu_r_intr3
struct	reg_iop_sw_cpu_r_masked_intr3

Macros
#define	REG_RD(scope, inst, reg)
#define	REG_WR(scope, inst, reg, val)
#define	REG_RD_VECT(scope, inst, reg, index)
#define	REG_WR_VECT(scope, inst, reg, index, val)
#define	REG_RD_INT(scope, inst, reg)   REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
#define	REG_WR_INT(scope, inst, reg, val)   REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#define	REG_RD_INT_VECT(scope, inst, reg, index)
#define	REG_WR_INT_VECT(scope, inst, reg, index, val)
#define	REG_TYPE_CONV(type, orgtype, val)   ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
#define	reg_page_size   8192
#define	REG_ADDR(scope, inst, reg)   ( (inst) + REG_RD_ADDR_##scope##_##reg )
#define	REG_ADDR_VECT(scope, inst, reg, index)
#define	REG_RD_ADDR_iop_sw_cpu_rw_mc_ctrl   0
#define	REG_WR_ADDR_iop_sw_cpu_rw_mc_ctrl   0
#define	REG_RD_ADDR_iop_sw_cpu_rw_mc_data   4
#define	REG_WR_ADDR_iop_sw_cpu_rw_mc_data   4
#define	REG_RD_ADDR_iop_sw_cpu_rw_mc_addr   8
#define	REG_WR_ADDR_iop_sw_cpu_rw_mc_addr   8
#define	REG_RD_ADDR_iop_sw_cpu_rs_mc_data   12
#define	REG_RD_ADDR_iop_sw_cpu_r_mc_data   16
#define	REG_RD_ADDR_iop_sw_cpu_r_mc_stat   20
#define	REG_RD_ADDR_iop_sw_cpu_rw_bus0_clr_mask   24
#define	REG_WR_ADDR_iop_sw_cpu_rw_bus0_clr_mask   24
#define	REG_RD_ADDR_iop_sw_cpu_rw_bus0_set_mask   28
#define	REG_WR_ADDR_iop_sw_cpu_rw_bus0_set_mask   28
#define	REG_RD_ADDR_iop_sw_cpu_rw_bus0_oe_clr_mask   32
#define	REG_WR_ADDR_iop_sw_cpu_rw_bus0_oe_clr_mask   32
#define	REG_RD_ADDR_iop_sw_cpu_rw_bus0_oe_set_mask   36
#define	REG_WR_ADDR_iop_sw_cpu_rw_bus0_oe_set_mask   36
#define	REG_RD_ADDR_iop_sw_cpu_r_bus0_in   40
#define	REG_RD_ADDR_iop_sw_cpu_rw_bus1_clr_mask   44
#define	REG_WR_ADDR_iop_sw_cpu_rw_bus1_clr_mask   44
#define	REG_RD_ADDR_iop_sw_cpu_rw_bus1_set_mask   48
#define	REG_WR_ADDR_iop_sw_cpu_rw_bus1_set_mask   48
#define	REG_RD_ADDR_iop_sw_cpu_rw_bus1_oe_clr_mask   52
#define	REG_WR_ADDR_iop_sw_cpu_rw_bus1_oe_clr_mask   52
#define	REG_RD_ADDR_iop_sw_cpu_rw_bus1_oe_set_mask   56
#define	REG_WR_ADDR_iop_sw_cpu_rw_bus1_oe_set_mask   56
#define	REG_RD_ADDR_iop_sw_cpu_r_bus1_in   60
#define	REG_RD_ADDR_iop_sw_cpu_rw_gio_clr_mask   64
#define	REG_WR_ADDR_iop_sw_cpu_rw_gio_clr_mask   64
#define	REG_RD_ADDR_iop_sw_cpu_rw_gio_set_mask   68
#define	REG_WR_ADDR_iop_sw_cpu_rw_gio_set_mask   68
#define	REG_RD_ADDR_iop_sw_cpu_rw_gio_oe_clr_mask   72
#define	REG_WR_ADDR_iop_sw_cpu_rw_gio_oe_clr_mask   72
#define	REG_RD_ADDR_iop_sw_cpu_rw_gio_oe_set_mask   76
#define	REG_WR_ADDR_iop_sw_cpu_rw_gio_oe_set_mask   76
#define	REG_RD_ADDR_iop_sw_cpu_r_gio_in   80
#define	REG_RD_ADDR_iop_sw_cpu_rw_intr0_mask   84
#define	REG_WR_ADDR_iop_sw_cpu_rw_intr0_mask   84
#define	REG_RD_ADDR_iop_sw_cpu_rw_ack_intr0   88
#define	REG_WR_ADDR_iop_sw_cpu_rw_ack_intr0   88
#define	REG_RD_ADDR_iop_sw_cpu_r_intr0   92
#define	REG_RD_ADDR_iop_sw_cpu_r_masked_intr0   96
#define	REG_RD_ADDR_iop_sw_cpu_rw_intr1_mask   100
#define	REG_WR_ADDR_iop_sw_cpu_rw_intr1_mask   100
#define	REG_RD_ADDR_iop_sw_cpu_rw_ack_intr1   104
#define	REG_WR_ADDR_iop_sw_cpu_rw_ack_intr1   104
#define	REG_RD_ADDR_iop_sw_cpu_r_intr1   108
#define	REG_RD_ADDR_iop_sw_cpu_r_masked_intr1   112
#define	REG_RD_ADDR_iop_sw_cpu_rw_intr2_mask   116
#define	REG_WR_ADDR_iop_sw_cpu_rw_intr2_mask   116
#define	REG_RD_ADDR_iop_sw_cpu_rw_ack_intr2   120
#define	REG_WR_ADDR_iop_sw_cpu_rw_ack_intr2   120
#define	REG_RD_ADDR_iop_sw_cpu_r_intr2   124
#define	REG_RD_ADDR_iop_sw_cpu_r_masked_intr2   128
#define	REG_RD_ADDR_iop_sw_cpu_rw_intr3_mask   132
#define	REG_WR_ADDR_iop_sw_cpu_rw_intr3_mask   132
#define	REG_RD_ADDR_iop_sw_cpu_rw_ack_intr3   136
#define	REG_WR_ADDR_iop_sw_cpu_rw_ack_intr3   136
#define	REG_RD_ADDR_iop_sw_cpu_r_intr3   140
#define	REG_RD_ADDR_iop_sw_cpu_r_masked_intr3   144

Typedefs
typedef unsigned int	reg_iop_sw_cpu_rw_mc_addr
typedef unsigned int	reg_iop_sw_cpu_rs_mc_data
typedef unsigned int	reg_iop_sw_cpu_r_mc_data
typedef unsigned int	reg_iop_sw_cpu_r_bus0_in
typedef unsigned int	reg_iop_sw_cpu_r_bus1_in
typedef unsigned int	reg_iop_sw_cpu_r_gio_in

Enumerations
enum	{   regk_iop_sw_cpu_copy = 0x00000000, regk_iop_sw_cpu_no = 0x00000000, regk_iop_sw_cpu_rd = 0x00000002, regk_iop_sw_cpu_reg_copy = 0x00000001,   regk_iop_sw_cpu_rw_bus0_clr_mask_default = 0x00000000, regk_iop_sw_cpu_rw_bus0_oe_clr_mask_default = 0x00000000, regk_iop_sw_cpu_rw_bus0_oe_set_mask_default = 0x00000000, regk_iop_sw_cpu_rw_bus0_set_mask_default = 0x00000000,   regk_iop_sw_cpu_rw_bus1_clr_mask_default = 0x00000000, regk_iop_sw_cpu_rw_bus1_oe_clr_mask_default = 0x00000000, regk_iop_sw_cpu_rw_bus1_oe_set_mask_default = 0x00000000, regk_iop_sw_cpu_rw_bus1_set_mask_default = 0x00000000,   regk_iop_sw_cpu_rw_gio_clr_mask_default = 0x00000000, regk_iop_sw_cpu_rw_gio_oe_clr_mask_default = 0x00000000, regk_iop_sw_cpu_rw_gio_oe_set_mask_default = 0x00000000, regk_iop_sw_cpu_rw_gio_set_mask_default = 0x00000000,   regk_iop_sw_cpu_rw_intr0_mask_default = 0x00000000, regk_iop_sw_cpu_rw_intr1_mask_default = 0x00000000, regk_iop_sw_cpu_rw_intr2_mask_default = 0x00000000, regk_iop_sw_cpu_rw_intr3_mask_default = 0x00000000,   regk_iop_sw_cpu_wr = 0x00000003, regk_iop_sw_cpu_yes = 0x00000001 }

Macro Definition Documentation

#define REG_ADDR	(		scope,
			inst,
			reg
	)		( (inst) + REG_RD_ADDR_##scope##_##reg )

Definition at line 75 of file iop_sw_cpu_defs.h.

#define REG_ADDR_VECT	(		scope,
			inst,
			reg,
			index
	)

Value:

( (inst) + REG_RD_ADDR_##scope##_##reg + \
    (index) * STRIDE_##scope##_##reg )

Definition at line 80 of file iop_sw_cpu_defs.h.

#define reg_page_size   8192

Definition at line 71 of file iop_sw_cpu_defs.h.

#define REG_RD	(		scope,
			inst,
			reg
	)

Value:

REG_READ( reg_##scope##_##reg, \
            (inst) + REG_RD_ADDR_##scope##_##reg )

Definition at line 18 of file iop_sw_cpu_defs.h.

#define REG_RD_ADDR_iop_sw_cpu_r_bus0_in   40

Definition at line 177 of file iop_sw_cpu_defs.h.

#define REG_RD_ADDR_iop_sw_cpu_r_bus1_in   60

Definition at line 223 of file iop_sw_cpu_defs.h.

#define REG_RD_ADDR_iop_sw_cpu_r_gio_in   80

Definition at line 255 of file iop_sw_cpu_defs.h.

#define REG_RD_ADDR_iop_sw_cpu_r_intr0   92

Definition at line 368 of file iop_sw_cpu_defs.h.

#define REG_RD_ADDR_iop_sw_cpu_r_intr1   108

Definition at line 518 of file iop_sw_cpu_defs.h.

#define REG_RD_ADDR_iop_sw_cpu_r_intr2   124

Definition at line 653 of file iop_sw_cpu_defs.h.

#define REG_RD_ADDR_iop_sw_cpu_r_intr3   140

Definition at line 788 of file iop_sw_cpu_defs.h.

#define REG_RD_ADDR_iop_sw_cpu_r_masked_intr0   96

Definition at line 405 of file iop_sw_cpu_defs.h.

#define REG_RD_ADDR_iop_sw_cpu_r_masked_intr1   112

Definition at line 555 of file iop_sw_cpu_defs.h.

#define REG_RD_ADDR_iop_sw_cpu_r_masked_intr2   128

Definition at line 690 of file iop_sw_cpu_defs.h.

#define REG_RD_ADDR_iop_sw_cpu_r_masked_intr3   144

Definition at line 825 of file iop_sw_cpu_defs.h.

#define REG_RD_ADDR_iop_sw_cpu_r_mc_data   16

Definition at line 117 of file iop_sw_cpu_defs.h.

#define REG_RD_ADDR_iop_sw_cpu_r_mc_stat   20

Definition at line 131 of file iop_sw_cpu_defs.h.

#define REG_RD_ADDR_iop_sw_cpu_rs_mc_data   12

Definition at line 113 of file iop_sw_cpu_defs.h.

#define REG_RD_ADDR_iop_sw_cpu_rw_ack_intr0   88

Definition at line 330 of file iop_sw_cpu_defs.h.

#define REG_RD_ADDR_iop_sw_cpu_rw_ack_intr1   104

Definition at line 480 of file iop_sw_cpu_defs.h.

#define REG_RD_ADDR_iop_sw_cpu_rw_ack_intr2   120

Definition at line 615 of file iop_sw_cpu_defs.h.

#define REG_RD_ADDR_iop_sw_cpu_rw_ack_intr3   136

Definition at line 750 of file iop_sw_cpu_defs.h.

#define REG_RD_ADDR_iop_sw_cpu_rw_bus0_clr_mask   24

Definition at line 140 of file iop_sw_cpu_defs.h.

#define REG_RD_ADDR_iop_sw_cpu_rw_bus0_oe_clr_mask   32

Definition at line 161 of file iop_sw_cpu_defs.h.

#define REG_RD_ADDR_iop_sw_cpu_rw_bus0_oe_set_mask   36

Definition at line 172 of file iop_sw_cpu_defs.h.

#define REG_RD_ADDR_iop_sw_cpu_rw_bus0_set_mask   28

Definition at line 150 of file iop_sw_cpu_defs.h.

#define REG_RD_ADDR_iop_sw_cpu_rw_bus1_clr_mask   44

Definition at line 186 of file iop_sw_cpu_defs.h.

#define REG_RD_ADDR_iop_sw_cpu_rw_bus1_oe_clr_mask   52

Definition at line 207 of file iop_sw_cpu_defs.h.

#define REG_RD_ADDR_iop_sw_cpu_rw_bus1_oe_set_mask   56

Definition at line 218 of file iop_sw_cpu_defs.h.

#define REG_RD_ADDR_iop_sw_cpu_rw_bus1_set_mask   48

Definition at line 196 of file iop_sw_cpu_defs.h.

#define REG_RD_ADDR_iop_sw_cpu_rw_gio_clr_mask   64

Definition at line 229 of file iop_sw_cpu_defs.h.

#define REG_RD_ADDR_iop_sw_cpu_rw_gio_oe_clr_mask   72

Definition at line 243 of file iop_sw_cpu_defs.h.

#define REG_RD_ADDR_iop_sw_cpu_rw_gio_oe_set_mask   76

Definition at line 250 of file iop_sw_cpu_defs.h.

#define REG_RD_ADDR_iop_sw_cpu_rw_gio_set_mask   68

Definition at line 236 of file iop_sw_cpu_defs.h.

#define REG_RD_ADDR_iop_sw_cpu_rw_intr0_mask   84

Definition at line 292 of file iop_sw_cpu_defs.h.

#define REG_RD_ADDR_iop_sw_cpu_rw_intr1_mask   100

Definition at line 442 of file iop_sw_cpu_defs.h.

#define REG_RD_ADDR_iop_sw_cpu_rw_intr2_mask   116

Definition at line 592 of file iop_sw_cpu_defs.h.

#define REG_RD_ADDR_iop_sw_cpu_rw_intr3_mask   132

Definition at line 727 of file iop_sw_cpu_defs.h.

#define REG_RD_ADDR_iop_sw_cpu_rw_mc_addr   8

Definition at line 108 of file iop_sw_cpu_defs.h.

#define REG_RD_ADDR_iop_sw_cpu_rw_mc_ctrl   0

Definition at line 96 of file iop_sw_cpu_defs.h.

#define REG_RD_ADDR_iop_sw_cpu_rw_mc_data   4

Definition at line 103 of file iop_sw_cpu_defs.h.

#define REG_RD_INT	(		scope,
			inst,
			reg
	)		REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )

Definition at line 44 of file iop_sw_cpu_defs.h.

#define REG_RD_INT_VECT	(		scope,
			inst,
			reg,
			index
	)

Value:

REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
        (index) * STRIDE_##scope##_##reg )

Definition at line 54 of file iop_sw_cpu_defs.h.

#define REG_RD_VECT	(		scope,
			inst,
			reg,
			index
	)

Value:

REG_READ( reg_##scope##_##reg, \
            (inst) + REG_RD_ADDR_##scope##_##reg + \
        (index) * STRIDE_##scope##_##reg )

Definition at line 30 of file iop_sw_cpu_defs.h.

#define REG_TYPE_CONV	(		type,
			orgtype,
			val
	)		( { union { orgtype o; type n; } r; r.o = val; r.n; } )

Definition at line 66 of file iop_sw_cpu_defs.h.

#define REG_WR	(		scope,
			inst,
			reg,
			val
	)

Value:

REG_WRITE( reg_##scope##_##reg, \
             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )

Definition at line 24 of file iop_sw_cpu_defs.h.

#define REG_WR_ADDR_iop_sw_cpu_rw_ack_intr0   88

Definition at line 331 of file iop_sw_cpu_defs.h.

#define REG_WR_ADDR_iop_sw_cpu_rw_ack_intr1   104

Definition at line 481 of file iop_sw_cpu_defs.h.

#define REG_WR_ADDR_iop_sw_cpu_rw_ack_intr2   120

Definition at line 616 of file iop_sw_cpu_defs.h.

#define REG_WR_ADDR_iop_sw_cpu_rw_ack_intr3   136

Definition at line 751 of file iop_sw_cpu_defs.h.

#define REG_WR_ADDR_iop_sw_cpu_rw_bus0_clr_mask   24

Definition at line 141 of file iop_sw_cpu_defs.h.

#define REG_WR_ADDR_iop_sw_cpu_rw_bus0_oe_clr_mask   32

Definition at line 162 of file iop_sw_cpu_defs.h.

#define REG_WR_ADDR_iop_sw_cpu_rw_bus0_oe_set_mask   36

Definition at line 173 of file iop_sw_cpu_defs.h.

#define REG_WR_ADDR_iop_sw_cpu_rw_bus0_set_mask   28

Definition at line 151 of file iop_sw_cpu_defs.h.

#define REG_WR_ADDR_iop_sw_cpu_rw_bus1_clr_mask   44

Definition at line 187 of file iop_sw_cpu_defs.h.

#define REG_WR_ADDR_iop_sw_cpu_rw_bus1_oe_clr_mask   52

Definition at line 208 of file iop_sw_cpu_defs.h.

#define REG_WR_ADDR_iop_sw_cpu_rw_bus1_oe_set_mask   56

Definition at line 219 of file iop_sw_cpu_defs.h.

#define REG_WR_ADDR_iop_sw_cpu_rw_bus1_set_mask   48

Definition at line 197 of file iop_sw_cpu_defs.h.

#define REG_WR_ADDR_iop_sw_cpu_rw_gio_clr_mask   64

Definition at line 230 of file iop_sw_cpu_defs.h.

#define REG_WR_ADDR_iop_sw_cpu_rw_gio_oe_clr_mask   72

Definition at line 244 of file iop_sw_cpu_defs.h.

#define REG_WR_ADDR_iop_sw_cpu_rw_gio_oe_set_mask   76

Definition at line 251 of file iop_sw_cpu_defs.h.

#define REG_WR_ADDR_iop_sw_cpu_rw_gio_set_mask   68

Definition at line 237 of file iop_sw_cpu_defs.h.

#define REG_WR_ADDR_iop_sw_cpu_rw_intr0_mask   84

Definition at line 293 of file iop_sw_cpu_defs.h.

#define REG_WR_ADDR_iop_sw_cpu_rw_intr1_mask   100

Definition at line 443 of file iop_sw_cpu_defs.h.

#define REG_WR_ADDR_iop_sw_cpu_rw_intr2_mask   116

Definition at line 593 of file iop_sw_cpu_defs.h.

#define REG_WR_ADDR_iop_sw_cpu_rw_intr3_mask   132

Definition at line 728 of file iop_sw_cpu_defs.h.

#define REG_WR_ADDR_iop_sw_cpu_rw_mc_addr   8

Definition at line 109 of file iop_sw_cpu_defs.h.

#define REG_WR_ADDR_iop_sw_cpu_rw_mc_ctrl   0

Definition at line 97 of file iop_sw_cpu_defs.h.

#define REG_WR_ADDR_iop_sw_cpu_rw_mc_data   4

Definition at line 104 of file iop_sw_cpu_defs.h.

#define REG_WR_INT	(		scope,
			inst,
			reg,
			val
	)		REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )

Definition at line 49 of file iop_sw_cpu_defs.h.

#define REG_WR_INT_VECT	(		scope,
			inst,
			reg,
			index,
			val
	)

Value:

REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
         (index) * STRIDE_##scope##_##reg, (val) )

Definition at line 60 of file iop_sw_cpu_defs.h.

#define REG_WR_VECT	(		scope,
			inst,
			reg,
			index,
			val
	)

Value:

REG_WRITE( reg_##scope##_##reg, \
             (inst) + REG_WR_ADDR_##scope##_##reg + \
         (index) * STRIDE_##scope##_##reg, (val) )

Definition at line 37 of file iop_sw_cpu_defs.h.

Typedef Documentation

typedef unsigned int reg_iop_sw_cpu_r_bus0_in

Definition at line 176 of file iop_sw_cpu_defs.h.

typedef unsigned int reg_iop_sw_cpu_r_bus1_in

Definition at line 222 of file iop_sw_cpu_defs.h.

typedef unsigned int reg_iop_sw_cpu_r_gio_in

Definition at line 254 of file iop_sw_cpu_defs.h.

typedef unsigned int reg_iop_sw_cpu_r_mc_data

Definition at line 116 of file iop_sw_cpu_defs.h.

typedef unsigned int reg_iop_sw_cpu_rs_mc_data

Definition at line 112 of file iop_sw_cpu_defs.h.

typedef unsigned int reg_iop_sw_cpu_rw_mc_addr

Definition at line 107 of file iop_sw_cpu_defs.h.

Enumeration Type Documentation

anonymous enum

Enumerator:

regk_iop_sw_cpu_copy
regk_iop_sw_cpu_no
regk_iop_sw_cpu_rd
regk_iop_sw_cpu_reg_copy
regk_iop_sw_cpu_rw_bus0_clr_mask_default
regk_iop_sw_cpu_rw_bus0_oe_clr_mask_default
regk_iop_sw_cpu_rw_bus0_oe_set_mask_default
regk_iop_sw_cpu_rw_bus0_set_mask_default
regk_iop_sw_cpu_rw_bus1_clr_mask_default
regk_iop_sw_cpu_rw_bus1_oe_clr_mask_default
regk_iop_sw_cpu_rw_bus1_oe_set_mask_default
regk_iop_sw_cpu_rw_bus1_set_mask_default
regk_iop_sw_cpu_rw_gio_clr_mask_default
regk_iop_sw_cpu_rw_gio_oe_clr_mask_default
regk_iop_sw_cpu_rw_gio_oe_set_mask_default
regk_iop_sw_cpu_rw_gio_set_mask_default
regk_iop_sw_cpu_rw_intr0_mask_default
regk_iop_sw_cpu_rw_intr1_mask_default
regk_iop_sw_cpu_rw_intr2_mask_default
regk_iop_sw_cpu_rw_intr3_mask_default
regk_iop_sw_cpu_wr
regk_iop_sw_cpu_yes

Definition at line 829 of file iop_sw_cpu_defs.h.