iop_sw_mpu_defs.h File Reference

Go to the source code of this file.

Data Structures
struct	reg_iop_sw_mpu_rw_sw_cfg_owner
struct	reg_iop_sw_mpu_rw_mc_ctrl
struct	reg_iop_sw_mpu_rw_mc_data
struct	reg_iop_sw_mpu_r_mc_stat
struct	reg_iop_sw_mpu_rw_bus0_clr_mask
struct	reg_iop_sw_mpu_rw_bus0_set_mask
struct	reg_iop_sw_mpu_rw_bus0_oe_clr_mask
struct	reg_iop_sw_mpu_rw_bus0_oe_set_mask
struct	reg_iop_sw_mpu_rw_bus1_clr_mask
struct	reg_iop_sw_mpu_rw_bus1_set_mask
struct	reg_iop_sw_mpu_rw_bus1_oe_clr_mask
struct	reg_iop_sw_mpu_rw_bus1_oe_set_mask
struct	reg_iop_sw_mpu_rw_gio_clr_mask
struct	reg_iop_sw_mpu_rw_gio_set_mask
struct	reg_iop_sw_mpu_rw_gio_oe_clr_mask
struct	reg_iop_sw_mpu_rw_gio_oe_set_mask
struct	reg_iop_sw_mpu_rw_cpu_intr
struct	reg_iop_sw_mpu_r_cpu_intr
struct	reg_iop_sw_mpu_rw_intr_grp0_mask
struct	reg_iop_sw_mpu_rw_ack_intr_grp0
struct	reg_iop_sw_mpu_r_intr_grp0
struct	reg_iop_sw_mpu_r_masked_intr_grp0
struct	reg_iop_sw_mpu_rw_intr_grp1_mask
struct	reg_iop_sw_mpu_rw_ack_intr_grp1
struct	reg_iop_sw_mpu_r_intr_grp1
struct	reg_iop_sw_mpu_r_masked_intr_grp1
struct	reg_iop_sw_mpu_rw_intr_grp2_mask
struct	reg_iop_sw_mpu_rw_ack_intr_grp2
struct	reg_iop_sw_mpu_r_intr_grp2
struct	reg_iop_sw_mpu_r_masked_intr_grp2
struct	reg_iop_sw_mpu_rw_intr_grp3_mask
struct	reg_iop_sw_mpu_rw_ack_intr_grp3
struct	reg_iop_sw_mpu_r_intr_grp3
struct	reg_iop_sw_mpu_r_masked_intr_grp3

Macros
#define	REG_RD(scope, inst, reg)
#define	REG_WR(scope, inst, reg, val)
#define	REG_RD_VECT(scope, inst, reg, index)
#define	REG_WR_VECT(scope, inst, reg, index, val)
#define	REG_RD_INT(scope, inst, reg)   REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
#define	REG_WR_INT(scope, inst, reg, val)   REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#define	REG_RD_INT_VECT(scope, inst, reg, index)
#define	REG_WR_INT_VECT(scope, inst, reg, index, val)
#define	REG_TYPE_CONV(type, orgtype, val)   ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
#define	reg_page_size   8192
#define	REG_ADDR(scope, inst, reg)   ( (inst) + REG_RD_ADDR_##scope##_##reg )
#define	REG_ADDR_VECT(scope, inst, reg, index)
#define	REG_RD_ADDR_iop_sw_mpu_rw_sw_cfg_owner   0
#define	REG_WR_ADDR_iop_sw_mpu_rw_sw_cfg_owner   0
#define	REG_RD_ADDR_iop_sw_mpu_rw_mc_ctrl   4
#define	REG_WR_ADDR_iop_sw_mpu_rw_mc_ctrl   4
#define	REG_RD_ADDR_iop_sw_mpu_rw_mc_data   8
#define	REG_WR_ADDR_iop_sw_mpu_rw_mc_data   8
#define	REG_RD_ADDR_iop_sw_mpu_rw_mc_addr   12
#define	REG_WR_ADDR_iop_sw_mpu_rw_mc_addr   12
#define	REG_RD_ADDR_iop_sw_mpu_rs_mc_data   16
#define	REG_RD_ADDR_iop_sw_mpu_r_mc_data   20
#define	REG_RD_ADDR_iop_sw_mpu_r_mc_stat   24
#define	REG_RD_ADDR_iop_sw_mpu_rw_bus0_clr_mask   28
#define	REG_WR_ADDR_iop_sw_mpu_rw_bus0_clr_mask   28
#define	REG_RD_ADDR_iop_sw_mpu_rw_bus0_set_mask   32
#define	REG_WR_ADDR_iop_sw_mpu_rw_bus0_set_mask   32
#define	REG_RD_ADDR_iop_sw_mpu_rw_bus0_oe_clr_mask   36
#define	REG_WR_ADDR_iop_sw_mpu_rw_bus0_oe_clr_mask   36
#define	REG_RD_ADDR_iop_sw_mpu_rw_bus0_oe_set_mask   40
#define	REG_WR_ADDR_iop_sw_mpu_rw_bus0_oe_set_mask   40
#define	REG_RD_ADDR_iop_sw_mpu_r_bus0_in   44
#define	REG_RD_ADDR_iop_sw_mpu_rw_bus1_clr_mask   48
#define	REG_WR_ADDR_iop_sw_mpu_rw_bus1_clr_mask   48
#define	REG_RD_ADDR_iop_sw_mpu_rw_bus1_set_mask   52
#define	REG_WR_ADDR_iop_sw_mpu_rw_bus1_set_mask   52
#define	REG_RD_ADDR_iop_sw_mpu_rw_bus1_oe_clr_mask   56
#define	REG_WR_ADDR_iop_sw_mpu_rw_bus1_oe_clr_mask   56
#define	REG_RD_ADDR_iop_sw_mpu_rw_bus1_oe_set_mask   60
#define	REG_WR_ADDR_iop_sw_mpu_rw_bus1_oe_set_mask   60
#define	REG_RD_ADDR_iop_sw_mpu_r_bus1_in   64
#define	REG_RD_ADDR_iop_sw_mpu_rw_gio_clr_mask   68
#define	REG_WR_ADDR_iop_sw_mpu_rw_gio_clr_mask   68
#define	REG_RD_ADDR_iop_sw_mpu_rw_gio_set_mask   72
#define	REG_WR_ADDR_iop_sw_mpu_rw_gio_set_mask   72
#define	REG_RD_ADDR_iop_sw_mpu_rw_gio_oe_clr_mask   76
#define	REG_WR_ADDR_iop_sw_mpu_rw_gio_oe_clr_mask   76
#define	REG_RD_ADDR_iop_sw_mpu_rw_gio_oe_set_mask   80
#define	REG_WR_ADDR_iop_sw_mpu_rw_gio_oe_set_mask   80
#define	REG_RD_ADDR_iop_sw_mpu_r_gio_in   84
#define	REG_RD_ADDR_iop_sw_mpu_rw_cpu_intr   88
#define	REG_WR_ADDR_iop_sw_mpu_rw_cpu_intr   88
#define	REG_RD_ADDR_iop_sw_mpu_r_cpu_intr   92
#define	REG_RD_ADDR_iop_sw_mpu_rw_intr_grp0_mask   96
#define	REG_WR_ADDR_iop_sw_mpu_rw_intr_grp0_mask   96
#define	REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp0   100
#define	REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp0   100
#define	REG_RD_ADDR_iop_sw_mpu_r_intr_grp0   104
#define	REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp0   108
#define	REG_RD_ADDR_iop_sw_mpu_rw_intr_grp1_mask   112
#define	REG_WR_ADDR_iop_sw_mpu_rw_intr_grp1_mask   112
#define	REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp1   116
#define	REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp1   116
#define	REG_RD_ADDR_iop_sw_mpu_r_intr_grp1   120
#define	REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp1   124
#define	REG_RD_ADDR_iop_sw_mpu_rw_intr_grp2_mask   128
#define	REG_WR_ADDR_iop_sw_mpu_rw_intr_grp2_mask   128
#define	REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp2   132
#define	REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp2   132
#define	REG_RD_ADDR_iop_sw_mpu_r_intr_grp2   136
#define	REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp2   140
#define	REG_RD_ADDR_iop_sw_mpu_rw_intr_grp3_mask   144
#define	REG_WR_ADDR_iop_sw_mpu_rw_intr_grp3_mask   144
#define	REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp3   148
#define	REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp3   148
#define	REG_RD_ADDR_iop_sw_mpu_r_intr_grp3   152
#define	REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp3   156

Typedefs
typedef unsigned int	reg_iop_sw_mpu_rw_mc_addr
typedef unsigned int	reg_iop_sw_mpu_rs_mc_data
typedef unsigned int	reg_iop_sw_mpu_r_mc_data
typedef unsigned int	reg_iop_sw_mpu_r_bus0_in
typedef unsigned int	reg_iop_sw_mpu_r_bus1_in
typedef unsigned int	reg_iop_sw_mpu_r_gio_in

Enumerations
enum	{   regk_iop_sw_mpu_copy = 0x00000000, regk_iop_sw_mpu_cpu = 0x00000000, regk_iop_sw_mpu_mpu = 0x00000001, regk_iop_sw_mpu_no = 0x00000000,   regk_iop_sw_mpu_nop = 0x00000000, regk_iop_sw_mpu_rd = 0x00000002, regk_iop_sw_mpu_reg_copy = 0x00000001, regk_iop_sw_mpu_rw_bus0_clr_mask_default = 0x00000000,   regk_iop_sw_mpu_rw_bus0_oe_clr_mask_default = 0x00000000, regk_iop_sw_mpu_rw_bus0_oe_set_mask_default = 0x00000000, regk_iop_sw_mpu_rw_bus0_set_mask_default = 0x00000000, regk_iop_sw_mpu_rw_bus1_clr_mask_default = 0x00000000,   regk_iop_sw_mpu_rw_bus1_oe_clr_mask_default = 0x00000000, regk_iop_sw_mpu_rw_bus1_oe_set_mask_default = 0x00000000, regk_iop_sw_mpu_rw_bus1_set_mask_default = 0x00000000, regk_iop_sw_mpu_rw_gio_clr_mask_default = 0x00000000,   regk_iop_sw_mpu_rw_gio_oe_clr_mask_default = 0x00000000, regk_iop_sw_mpu_rw_gio_oe_set_mask_default = 0x00000000, regk_iop_sw_mpu_rw_gio_set_mask_default = 0x00000000, regk_iop_sw_mpu_rw_intr_grp0_mask_default = 0x00000000,   regk_iop_sw_mpu_rw_intr_grp1_mask_default = 0x00000000, regk_iop_sw_mpu_rw_intr_grp2_mask_default = 0x00000000, regk_iop_sw_mpu_rw_intr_grp3_mask_default = 0x00000000, regk_iop_sw_mpu_rw_sw_cfg_owner_default = 0x00000000,   regk_iop_sw_mpu_set = 0x00000001, regk_iop_sw_mpu_spu0 = 0x00000002, regk_iop_sw_mpu_spu1 = 0x00000003, regk_iop_sw_mpu_wr = 0x00000003,   regk_iop_sw_mpu_yes = 0x00000001 }

Macro Definition Documentation

#define REG_ADDR	(		scope,
			inst,
			reg
	)		( (inst) + REG_RD_ADDR_##scope##_##reg )

Definition at line 75 of file iop_sw_mpu_defs.h.

#define REG_ADDR_VECT	(		scope,
			inst,
			reg,
			index
	)

Value:

( (inst) + REG_RD_ADDR_##scope##_##reg + \
    (index) * STRIDE_##scope##_##reg )

Definition at line 80 of file iop_sw_mpu_defs.h.

#define reg_page_size   8192

Definition at line 71 of file iop_sw_mpu_defs.h.

#define REG_RD	(		scope,
			inst,
			reg
	)

Value:

REG_READ( reg_##scope##_##reg, \
            (inst) + REG_RD_ADDR_##scope##_##reg )

Definition at line 18 of file iop_sw_mpu_defs.h.

#define REG_RD_ADDR_iop_sw_mpu_r_bus0_in   44

Definition at line 185 of file iop_sw_mpu_defs.h.

#define REG_RD_ADDR_iop_sw_mpu_r_bus1_in   64

Definition at line 231 of file iop_sw_mpu_defs.h.

#define REG_RD_ADDR_iop_sw_mpu_r_cpu_intr   92

Definition at line 338 of file iop_sw_mpu_defs.h.

#define REG_RD_ADDR_iop_sw_mpu_r_gio_in   84

Definition at line 263 of file iop_sw_mpu_defs.h.

#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp0   104

Definition at line 431 of file iop_sw_mpu_defs.h.

#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp1   120

Definition at line 561 of file iop_sw_mpu_defs.h.

#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp2   136

Definition at line 691 of file iop_sw_mpu_defs.h.

#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp3   152

Definition at line 821 of file iop_sw_mpu_defs.h.

#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp0   108

Definition at line 468 of file iop_sw_mpu_defs.h.

#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp1   124

Definition at line 598 of file iop_sw_mpu_defs.h.

#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp2   140

Definition at line 728 of file iop_sw_mpu_defs.h.

#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp3   156

Definition at line 858 of file iop_sw_mpu_defs.h.

#define REG_RD_ADDR_iop_sw_mpu_r_mc_data   20

Definition at line 125 of file iop_sw_mpu_defs.h.

#define REG_RD_ADDR_iop_sw_mpu_r_mc_stat   24

Definition at line 139 of file iop_sw_mpu_defs.h.

#define REG_RD_ADDR_iop_sw_mpu_rs_mc_data   16

Definition at line 121 of file iop_sw_mpu_defs.h.

#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp0   100

Definition at line 393 of file iop_sw_mpu_defs.h.

#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp1   116

Definition at line 523 of file iop_sw_mpu_defs.h.

#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp2   132

Definition at line 653 of file iop_sw_mpu_defs.h.

#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp3   148

Definition at line 783 of file iop_sw_mpu_defs.h.

#define REG_RD_ADDR_iop_sw_mpu_rw_bus0_clr_mask   28

Definition at line 148 of file iop_sw_mpu_defs.h.

#define REG_RD_ADDR_iop_sw_mpu_rw_bus0_oe_clr_mask   36

Definition at line 169 of file iop_sw_mpu_defs.h.

#define REG_RD_ADDR_iop_sw_mpu_rw_bus0_oe_set_mask   40

Definition at line 180 of file iop_sw_mpu_defs.h.

#define REG_RD_ADDR_iop_sw_mpu_rw_bus0_set_mask   32

Definition at line 158 of file iop_sw_mpu_defs.h.

#define REG_RD_ADDR_iop_sw_mpu_rw_bus1_clr_mask   48

Definition at line 194 of file iop_sw_mpu_defs.h.

#define REG_RD_ADDR_iop_sw_mpu_rw_bus1_oe_clr_mask   56

Definition at line 215 of file iop_sw_mpu_defs.h.

#define REG_RD_ADDR_iop_sw_mpu_rw_bus1_oe_set_mask   60

Definition at line 226 of file iop_sw_mpu_defs.h.

#define REG_RD_ADDR_iop_sw_mpu_rw_bus1_set_mask   52

Definition at line 204 of file iop_sw_mpu_defs.h.

#define REG_RD_ADDR_iop_sw_mpu_rw_cpu_intr   88

Definition at line 300 of file iop_sw_mpu_defs.h.

#define REG_RD_ADDR_iop_sw_mpu_rw_gio_clr_mask   68

Definition at line 237 of file iop_sw_mpu_defs.h.

#define REG_RD_ADDR_iop_sw_mpu_rw_gio_oe_clr_mask   76

Definition at line 251 of file iop_sw_mpu_defs.h.

#define REG_RD_ADDR_iop_sw_mpu_rw_gio_oe_set_mask   80

Definition at line 258 of file iop_sw_mpu_defs.h.

#define REG_RD_ADDR_iop_sw_mpu_rw_gio_set_mask   72

Definition at line 244 of file iop_sw_mpu_defs.h.

#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp0_mask   96

Definition at line 375 of file iop_sw_mpu_defs.h.

#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp1_mask   112

Definition at line 505 of file iop_sw_mpu_defs.h.

#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp2_mask   128

Definition at line 635 of file iop_sw_mpu_defs.h.

#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp3_mask   144

Definition at line 765 of file iop_sw_mpu_defs.h.

#define REG_RD_ADDR_iop_sw_mpu_rw_mc_addr   12

Definition at line 116 of file iop_sw_mpu_defs.h.

#define REG_RD_ADDR_iop_sw_mpu_rw_mc_ctrl   4

Definition at line 104 of file iop_sw_mpu_defs.h.

#define REG_RD_ADDR_iop_sw_mpu_rw_mc_data   8

Definition at line 111 of file iop_sw_mpu_defs.h.

#define REG_RD_ADDR_iop_sw_mpu_rw_sw_cfg_owner   0

Definition at line 92 of file iop_sw_mpu_defs.h.

#define REG_RD_INT	(		scope,
			inst,
			reg
	)		REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )

Definition at line 44 of file iop_sw_mpu_defs.h.

#define REG_RD_INT_VECT	(		scope,
			inst,
			reg,
			index
	)

Value:

REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
        (index) * STRIDE_##scope##_##reg )

Definition at line 54 of file iop_sw_mpu_defs.h.

#define REG_RD_VECT	(		scope,
			inst,
			reg,
			index
	)

Value:

REG_READ( reg_##scope##_##reg, \
            (inst) + REG_RD_ADDR_##scope##_##reg + \
        (index) * STRIDE_##scope##_##reg )

Definition at line 30 of file iop_sw_mpu_defs.h.

#define REG_TYPE_CONV	(		type,
			orgtype,
			val
	)		( { union { orgtype o; type n; } r; r.o = val; r.n; } )

Definition at line 66 of file iop_sw_mpu_defs.h.

#define REG_WR	(		scope,
			inst,
			reg,
			val
	)

Value:

REG_WRITE( reg_##scope##_##reg, \
             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )

Definition at line 24 of file iop_sw_mpu_defs.h.

#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp0   100

Definition at line 394 of file iop_sw_mpu_defs.h.

#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp1   116

Definition at line 524 of file iop_sw_mpu_defs.h.

#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp2   132

Definition at line 654 of file iop_sw_mpu_defs.h.

#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp3   148

Definition at line 784 of file iop_sw_mpu_defs.h.

#define REG_WR_ADDR_iop_sw_mpu_rw_bus0_clr_mask   28

Definition at line 149 of file iop_sw_mpu_defs.h.

#define REG_WR_ADDR_iop_sw_mpu_rw_bus0_oe_clr_mask   36

Definition at line 170 of file iop_sw_mpu_defs.h.

#define REG_WR_ADDR_iop_sw_mpu_rw_bus0_oe_set_mask   40

Definition at line 181 of file iop_sw_mpu_defs.h.

#define REG_WR_ADDR_iop_sw_mpu_rw_bus0_set_mask   32

Definition at line 159 of file iop_sw_mpu_defs.h.

#define REG_WR_ADDR_iop_sw_mpu_rw_bus1_clr_mask   48

Definition at line 195 of file iop_sw_mpu_defs.h.

#define REG_WR_ADDR_iop_sw_mpu_rw_bus1_oe_clr_mask   56

Definition at line 216 of file iop_sw_mpu_defs.h.

#define REG_WR_ADDR_iop_sw_mpu_rw_bus1_oe_set_mask   60

Definition at line 227 of file iop_sw_mpu_defs.h.

#define REG_WR_ADDR_iop_sw_mpu_rw_bus1_set_mask   52

Definition at line 205 of file iop_sw_mpu_defs.h.

#define REG_WR_ADDR_iop_sw_mpu_rw_cpu_intr   88

Definition at line 301 of file iop_sw_mpu_defs.h.

#define REG_WR_ADDR_iop_sw_mpu_rw_gio_clr_mask   68

Definition at line 238 of file iop_sw_mpu_defs.h.

#define REG_WR_ADDR_iop_sw_mpu_rw_gio_oe_clr_mask   76

Definition at line 252 of file iop_sw_mpu_defs.h.

#define REG_WR_ADDR_iop_sw_mpu_rw_gio_oe_set_mask   80

Definition at line 259 of file iop_sw_mpu_defs.h.

#define REG_WR_ADDR_iop_sw_mpu_rw_gio_set_mask   72

Definition at line 245 of file iop_sw_mpu_defs.h.

#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp0_mask   96

Definition at line 376 of file iop_sw_mpu_defs.h.

#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp1_mask   112

Definition at line 506 of file iop_sw_mpu_defs.h.

#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp2_mask   128

Definition at line 636 of file iop_sw_mpu_defs.h.

#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp3_mask   144

Definition at line 766 of file iop_sw_mpu_defs.h.

#define REG_WR_ADDR_iop_sw_mpu_rw_mc_addr   12

Definition at line 117 of file iop_sw_mpu_defs.h.

#define REG_WR_ADDR_iop_sw_mpu_rw_mc_ctrl   4

Definition at line 105 of file iop_sw_mpu_defs.h.

#define REG_WR_ADDR_iop_sw_mpu_rw_mc_data   8

Definition at line 112 of file iop_sw_mpu_defs.h.

#define REG_WR_ADDR_iop_sw_mpu_rw_sw_cfg_owner   0

Definition at line 93 of file iop_sw_mpu_defs.h.

#define REG_WR_INT	(		scope,
			inst,
			reg,
			val
	)		REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )

Definition at line 49 of file iop_sw_mpu_defs.h.

#define REG_WR_INT_VECT	(		scope,
			inst,
			reg,
			index,
			val
	)

Value:

REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
         (index) * STRIDE_##scope##_##reg, (val) )

Definition at line 60 of file iop_sw_mpu_defs.h.

#define REG_WR_VECT	(		scope,
			inst,
			reg,
			index,
			val
	)

Value:

REG_WRITE( reg_##scope##_##reg, \
             (inst) + REG_WR_ADDR_##scope##_##reg + \
         (index) * STRIDE_##scope##_##reg, (val) )

Definition at line 37 of file iop_sw_mpu_defs.h.

Typedef Documentation

typedef unsigned int reg_iop_sw_mpu_r_bus0_in

Definition at line 184 of file iop_sw_mpu_defs.h.

typedef unsigned int reg_iop_sw_mpu_r_bus1_in

Definition at line 230 of file iop_sw_mpu_defs.h.

typedef unsigned int reg_iop_sw_mpu_r_gio_in

Definition at line 262 of file iop_sw_mpu_defs.h.

typedef unsigned int reg_iop_sw_mpu_r_mc_data

Definition at line 124 of file iop_sw_mpu_defs.h.

typedef unsigned int reg_iop_sw_mpu_rs_mc_data

Definition at line 120 of file iop_sw_mpu_defs.h.

typedef unsigned int reg_iop_sw_mpu_rw_mc_addr

Definition at line 115 of file iop_sw_mpu_defs.h.

Enumeration Type Documentation

anonymous enum

Enumerator:

regk_iop_sw_mpu_copy
regk_iop_sw_mpu_cpu
regk_iop_sw_mpu_mpu
regk_iop_sw_mpu_no
regk_iop_sw_mpu_nop
regk_iop_sw_mpu_rd
regk_iop_sw_mpu_reg_copy
regk_iop_sw_mpu_rw_bus0_clr_mask_default
regk_iop_sw_mpu_rw_bus0_oe_clr_mask_default
regk_iop_sw_mpu_rw_bus0_oe_set_mask_default
regk_iop_sw_mpu_rw_bus0_set_mask_default
regk_iop_sw_mpu_rw_bus1_clr_mask_default
regk_iop_sw_mpu_rw_bus1_oe_clr_mask_default
regk_iop_sw_mpu_rw_bus1_oe_set_mask_default
regk_iop_sw_mpu_rw_bus1_set_mask_default
regk_iop_sw_mpu_rw_gio_clr_mask_default
regk_iop_sw_mpu_rw_gio_oe_clr_mask_default
regk_iop_sw_mpu_rw_gio_oe_set_mask_default
regk_iop_sw_mpu_rw_gio_set_mask_default
regk_iop_sw_mpu_rw_intr_grp0_mask_default
regk_iop_sw_mpu_rw_intr_grp1_mask_default
regk_iop_sw_mpu_rw_intr_grp2_mask_default
regk_iop_sw_mpu_rw_intr_grp3_mask_default
regk_iop_sw_mpu_rw_sw_cfg_owner_default
regk_iop_sw_mpu_set
regk_iop_sw_mpu_spu0
regk_iop_sw_mpu_spu1
regk_iop_sw_mpu_wr
regk_iop_sw_mpu_yes

Definition at line 862 of file iop_sw_mpu_defs.h.