iop_sw_spu_defs.h File Reference

Go to the source code of this file.

Data Structures
struct	reg_iop_sw_spu_rw_mc_ctrl
struct	reg_iop_sw_spu_rw_mc_data
struct	reg_iop_sw_spu_r_mc_stat
struct	reg_iop_sw_spu_rw_bus0_clr_mask
struct	reg_iop_sw_spu_rw_bus0_set_mask
struct	reg_iop_sw_spu_rw_bus0_oe_clr_mask
struct	reg_iop_sw_spu_rw_bus0_oe_set_mask
struct	reg_iop_sw_spu_rw_bus1_clr_mask
struct	reg_iop_sw_spu_rw_bus1_set_mask
struct	reg_iop_sw_spu_rw_bus1_oe_clr_mask
struct	reg_iop_sw_spu_rw_bus1_oe_set_mask
struct	reg_iop_sw_spu_rw_gio_clr_mask
struct	reg_iop_sw_spu_rw_gio_set_mask
struct	reg_iop_sw_spu_rw_gio_oe_clr_mask
struct	reg_iop_sw_spu_rw_gio_oe_set_mask
struct	reg_iop_sw_spu_rw_bus0_clr_mask_lo
struct	reg_iop_sw_spu_rw_bus0_clr_mask_hi
struct	reg_iop_sw_spu_rw_bus0_set_mask_lo
struct	reg_iop_sw_spu_rw_bus0_set_mask_hi
struct	reg_iop_sw_spu_rw_bus1_clr_mask_lo
struct	reg_iop_sw_spu_rw_bus1_clr_mask_hi
struct	reg_iop_sw_spu_rw_bus1_set_mask_lo
struct	reg_iop_sw_spu_rw_bus1_set_mask_hi
struct	reg_iop_sw_spu_rw_gio_clr_mask_lo
struct	reg_iop_sw_spu_rw_gio_clr_mask_hi
struct	reg_iop_sw_spu_rw_gio_set_mask_lo
struct	reg_iop_sw_spu_rw_gio_set_mask_hi
struct	reg_iop_sw_spu_rw_gio_oe_clr_mask_lo
struct	reg_iop_sw_spu_rw_gio_oe_clr_mask_hi
struct	reg_iop_sw_spu_rw_gio_oe_set_mask_lo
struct	reg_iop_sw_spu_rw_gio_oe_set_mask_hi
struct	reg_iop_sw_spu_rw_cpu_intr
struct	reg_iop_sw_spu_r_cpu_intr
struct	reg_iop_sw_spu_r_hw_intr
struct	reg_iop_sw_spu_rw_mpu_intr
struct	reg_iop_sw_spu_r_mpu_intr

Macros
#define	REG_RD(scope, inst, reg)
#define	REG_WR(scope, inst, reg, val)
#define	REG_RD_VECT(scope, inst, reg, index)
#define	REG_WR_VECT(scope, inst, reg, index, val)
#define	REG_RD_INT(scope, inst, reg)   REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
#define	REG_WR_INT(scope, inst, reg, val)   REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
#define	REG_RD_INT_VECT(scope, inst, reg, index)
#define	REG_WR_INT_VECT(scope, inst, reg, index, val)
#define	REG_TYPE_CONV(type, orgtype, val)   ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
#define	reg_page_size   8192
#define	REG_ADDR(scope, inst, reg)   ( (inst) + REG_RD_ADDR_##scope##_##reg )
#define	REG_ADDR_VECT(scope, inst, reg, index)
#define	REG_RD_ADDR_iop_sw_spu_rw_mc_ctrl   0
#define	REG_WR_ADDR_iop_sw_spu_rw_mc_ctrl   0
#define	REG_RD_ADDR_iop_sw_spu_rw_mc_data   4
#define	REG_WR_ADDR_iop_sw_spu_rw_mc_data   4
#define	REG_RD_ADDR_iop_sw_spu_rw_mc_addr   8
#define	REG_WR_ADDR_iop_sw_spu_rw_mc_addr   8
#define	REG_RD_ADDR_iop_sw_spu_rs_mc_data   12
#define	REG_RD_ADDR_iop_sw_spu_r_mc_data   16
#define	REG_RD_ADDR_iop_sw_spu_r_mc_stat   20
#define	REG_RD_ADDR_iop_sw_spu_rw_bus0_clr_mask   24
#define	REG_WR_ADDR_iop_sw_spu_rw_bus0_clr_mask   24
#define	REG_RD_ADDR_iop_sw_spu_rw_bus0_set_mask   28
#define	REG_WR_ADDR_iop_sw_spu_rw_bus0_set_mask   28
#define	REG_RD_ADDR_iop_sw_spu_rw_bus0_oe_clr_mask   32
#define	REG_WR_ADDR_iop_sw_spu_rw_bus0_oe_clr_mask   32
#define	REG_RD_ADDR_iop_sw_spu_rw_bus0_oe_set_mask   36
#define	REG_WR_ADDR_iop_sw_spu_rw_bus0_oe_set_mask   36
#define	REG_RD_ADDR_iop_sw_spu_r_bus0_in   40
#define	REG_RD_ADDR_iop_sw_spu_rw_bus1_clr_mask   44
#define	REG_WR_ADDR_iop_sw_spu_rw_bus1_clr_mask   44
#define	REG_RD_ADDR_iop_sw_spu_rw_bus1_set_mask   48
#define	REG_WR_ADDR_iop_sw_spu_rw_bus1_set_mask   48
#define	REG_RD_ADDR_iop_sw_spu_rw_bus1_oe_clr_mask   52
#define	REG_WR_ADDR_iop_sw_spu_rw_bus1_oe_clr_mask   52
#define	REG_RD_ADDR_iop_sw_spu_rw_bus1_oe_set_mask   56
#define	REG_WR_ADDR_iop_sw_spu_rw_bus1_oe_set_mask   56
#define	REG_RD_ADDR_iop_sw_spu_r_bus1_in   60
#define	REG_RD_ADDR_iop_sw_spu_rw_gio_clr_mask   64
#define	REG_WR_ADDR_iop_sw_spu_rw_gio_clr_mask   64
#define	REG_RD_ADDR_iop_sw_spu_rw_gio_set_mask   68
#define	REG_WR_ADDR_iop_sw_spu_rw_gio_set_mask   68
#define	REG_RD_ADDR_iop_sw_spu_rw_gio_oe_clr_mask   72
#define	REG_WR_ADDR_iop_sw_spu_rw_gio_oe_clr_mask   72
#define	REG_RD_ADDR_iop_sw_spu_rw_gio_oe_set_mask   76
#define	REG_WR_ADDR_iop_sw_spu_rw_gio_oe_set_mask   76
#define	REG_RD_ADDR_iop_sw_spu_r_gio_in   80
#define	REG_RD_ADDR_iop_sw_spu_rw_bus0_clr_mask_lo   84
#define	REG_WR_ADDR_iop_sw_spu_rw_bus0_clr_mask_lo   84
#define	REG_RD_ADDR_iop_sw_spu_rw_bus0_clr_mask_hi   88
#define	REG_WR_ADDR_iop_sw_spu_rw_bus0_clr_mask_hi   88
#define	REG_RD_ADDR_iop_sw_spu_rw_bus0_set_mask_lo   92
#define	REG_WR_ADDR_iop_sw_spu_rw_bus0_set_mask_lo   92
#define	REG_RD_ADDR_iop_sw_spu_rw_bus0_set_mask_hi   96
#define	REG_WR_ADDR_iop_sw_spu_rw_bus0_set_mask_hi   96
#define	REG_RD_ADDR_iop_sw_spu_rw_bus1_clr_mask_lo   100
#define	REG_WR_ADDR_iop_sw_spu_rw_bus1_clr_mask_lo   100
#define	REG_RD_ADDR_iop_sw_spu_rw_bus1_clr_mask_hi   104
#define	REG_WR_ADDR_iop_sw_spu_rw_bus1_clr_mask_hi   104
#define	REG_RD_ADDR_iop_sw_spu_rw_bus1_set_mask_lo   108
#define	REG_WR_ADDR_iop_sw_spu_rw_bus1_set_mask_lo   108
#define	REG_RD_ADDR_iop_sw_spu_rw_bus1_set_mask_hi   112
#define	REG_WR_ADDR_iop_sw_spu_rw_bus1_set_mask_hi   112
#define	REG_RD_ADDR_iop_sw_spu_rw_gio_clr_mask_lo   116
#define	REG_WR_ADDR_iop_sw_spu_rw_gio_clr_mask_lo   116
#define	REG_RD_ADDR_iop_sw_spu_rw_gio_clr_mask_hi   120
#define	REG_WR_ADDR_iop_sw_spu_rw_gio_clr_mask_hi   120
#define	REG_RD_ADDR_iop_sw_spu_rw_gio_set_mask_lo   124
#define	REG_WR_ADDR_iop_sw_spu_rw_gio_set_mask_lo   124
#define	REG_RD_ADDR_iop_sw_spu_rw_gio_set_mask_hi   128
#define	REG_WR_ADDR_iop_sw_spu_rw_gio_set_mask_hi   128
#define	REG_RD_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_lo   132
#define	REG_WR_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_lo   132
#define	REG_RD_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_hi   136
#define	REG_WR_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_hi   136
#define	REG_RD_ADDR_iop_sw_spu_rw_gio_oe_set_mask_lo   140
#define	REG_WR_ADDR_iop_sw_spu_rw_gio_oe_set_mask_lo   140
#define	REG_RD_ADDR_iop_sw_spu_rw_gio_oe_set_mask_hi   144
#define	REG_WR_ADDR_iop_sw_spu_rw_gio_oe_set_mask_hi   144
#define	REG_RD_ADDR_iop_sw_spu_rw_cpu_intr   148
#define	REG_WR_ADDR_iop_sw_spu_rw_cpu_intr   148
#define	REG_RD_ADDR_iop_sw_spu_r_cpu_intr   152
#define	REG_RD_ADDR_iop_sw_spu_r_hw_intr   156
#define	REG_RD_ADDR_iop_sw_spu_rw_mpu_intr   160
#define	REG_WR_ADDR_iop_sw_spu_rw_mpu_intr   160
#define	REG_RD_ADDR_iop_sw_spu_r_mpu_intr   164

Typedefs
typedef unsigned int	reg_iop_sw_spu_rw_mc_addr
typedef unsigned int	reg_iop_sw_spu_rs_mc_data
typedef unsigned int	reg_iop_sw_spu_r_mc_data
typedef unsigned int	reg_iop_sw_spu_r_bus0_in
typedef unsigned int	reg_iop_sw_spu_r_bus1_in
typedef unsigned int	reg_iop_sw_spu_r_gio_in

Enumerations
enum	{   regk_iop_sw_spu_copy = 0x00000000, regk_iop_sw_spu_no = 0x00000000, regk_iop_sw_spu_nop = 0x00000000, regk_iop_sw_spu_rd = 0x00000002,   regk_iop_sw_spu_reg_copy = 0x00000001, regk_iop_sw_spu_rw_bus0_clr_mask_default = 0x00000000, regk_iop_sw_spu_rw_bus0_oe_clr_mask_default = 0x00000000, regk_iop_sw_spu_rw_bus0_oe_set_mask_default = 0x00000000,   regk_iop_sw_spu_rw_bus0_set_mask_default = 0x00000000, regk_iop_sw_spu_rw_bus1_clr_mask_default = 0x00000000, regk_iop_sw_spu_rw_bus1_oe_clr_mask_default = 0x00000000, regk_iop_sw_spu_rw_bus1_oe_set_mask_default = 0x00000000,   regk_iop_sw_spu_rw_bus1_set_mask_default = 0x00000000, regk_iop_sw_spu_rw_gio_clr_mask_default = 0x00000000, regk_iop_sw_spu_rw_gio_oe_clr_mask_default = 0x00000000, regk_iop_sw_spu_rw_gio_oe_set_mask_default = 0x00000000,   regk_iop_sw_spu_rw_gio_set_mask_default = 0x00000000, regk_iop_sw_spu_set = 0x00000001, regk_iop_sw_spu_wr = 0x00000003, regk_iop_sw_spu_yes = 0x00000001 }

Macro Definition Documentation

#define REG_ADDR	(		scope,
			inst,
			reg
	)		( (inst) + REG_RD_ADDR_##scope##_##reg )

Definition at line 75 of file iop_sw_spu_defs.h.

#define REG_ADDR_VECT	(		scope,
			inst,
			reg,
			index
	)

Value:

( (inst) + REG_RD_ADDR_##scope##_##reg + \
    (index) * STRIDE_##scope##_##reg )

Definition at line 80 of file iop_sw_spu_defs.h.

#define reg_page_size   8192

Definition at line 71 of file iop_sw_spu_defs.h.

#define REG_RD	(		scope,
			inst,
			reg
	)

Value:

REG_READ( reg_##scope##_##reg, \
            (inst) + REG_RD_ADDR_##scope##_##reg )

Definition at line 18 of file iop_sw_spu_defs.h.

#define REG_RD_ADDR_iop_sw_spu_r_bus0_in   40

Definition at line 177 of file iop_sw_spu_defs.h.

#define REG_RD_ADDR_iop_sw_spu_r_bus1_in   60

Definition at line 223 of file iop_sw_spu_defs.h.

#define REG_RD_ADDR_iop_sw_spu_r_cpu_intr   152

Definition at line 436 of file iop_sw_spu_defs.h.

#define REG_RD_ADDR_iop_sw_spu_r_gio_in   80

Definition at line 255 of file iop_sw_spu_defs.h.

#define REG_RD_ADDR_iop_sw_spu_r_hw_intr   156

Definition at line 466 of file iop_sw_spu_defs.h.

#define REG_RD_ADDR_iop_sw_spu_r_mc_data   16

Definition at line 117 of file iop_sw_spu_defs.h.

#define REG_RD_ADDR_iop_sw_spu_r_mc_stat   20

Definition at line 131 of file iop_sw_spu_defs.h.

#define REG_RD_ADDR_iop_sw_spu_r_mpu_intr   164

Definition at line 526 of file iop_sw_spu_defs.h.

#define REG_RD_ADDR_iop_sw_spu_rs_mc_data   12

Definition at line 113 of file iop_sw_spu_defs.h.

#define REG_RD_ADDR_iop_sw_spu_rw_bus0_clr_mask   24

Definition at line 140 of file iop_sw_spu_defs.h.

#define REG_RD_ADDR_iop_sw_spu_rw_bus0_clr_mask_hi   88

Definition at line 272 of file iop_sw_spu_defs.h.

#define REG_RD_ADDR_iop_sw_spu_rw_bus0_clr_mask_lo   84

Definition at line 263 of file iop_sw_spu_defs.h.

#define REG_RD_ADDR_iop_sw_spu_rw_bus0_oe_clr_mask   32

Definition at line 161 of file iop_sw_spu_defs.h.

#define REG_RD_ADDR_iop_sw_spu_rw_bus0_oe_set_mask   36

Definition at line 172 of file iop_sw_spu_defs.h.

#define REG_RD_ADDR_iop_sw_spu_rw_bus0_set_mask   28

Definition at line 150 of file iop_sw_spu_defs.h.

#define REG_RD_ADDR_iop_sw_spu_rw_bus0_set_mask_hi   96

Definition at line 290 of file iop_sw_spu_defs.h.

#define REG_RD_ADDR_iop_sw_spu_rw_bus0_set_mask_lo   92

Definition at line 281 of file iop_sw_spu_defs.h.

#define REG_RD_ADDR_iop_sw_spu_rw_bus1_clr_mask   44

Definition at line 186 of file iop_sw_spu_defs.h.

#define REG_RD_ADDR_iop_sw_spu_rw_bus1_clr_mask_hi   104

Definition at line 308 of file iop_sw_spu_defs.h.

#define REG_RD_ADDR_iop_sw_spu_rw_bus1_clr_mask_lo   100

Definition at line 299 of file iop_sw_spu_defs.h.

#define REG_RD_ADDR_iop_sw_spu_rw_bus1_oe_clr_mask   52

Definition at line 207 of file iop_sw_spu_defs.h.

#define REG_RD_ADDR_iop_sw_spu_rw_bus1_oe_set_mask   56

Definition at line 218 of file iop_sw_spu_defs.h.

#define REG_RD_ADDR_iop_sw_spu_rw_bus1_set_mask   48

Definition at line 196 of file iop_sw_spu_defs.h.

#define REG_RD_ADDR_iop_sw_spu_rw_bus1_set_mask_hi   112

Definition at line 326 of file iop_sw_spu_defs.h.

#define REG_RD_ADDR_iop_sw_spu_rw_bus1_set_mask_lo   108

Definition at line 317 of file iop_sw_spu_defs.h.

#define REG_RD_ADDR_iop_sw_spu_rw_cpu_intr   148

Definition at line 413 of file iop_sw_spu_defs.h.

#define REG_RD_ADDR_iop_sw_spu_rw_gio_clr_mask   64

Definition at line 229 of file iop_sw_spu_defs.h.

#define REG_RD_ADDR_iop_sw_spu_rw_gio_clr_mask_hi   120

Definition at line 342 of file iop_sw_spu_defs.h.

#define REG_RD_ADDR_iop_sw_spu_rw_gio_clr_mask_lo   116

Definition at line 334 of file iop_sw_spu_defs.h.

#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_clr_mask   72

Definition at line 243 of file iop_sw_spu_defs.h.

#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_hi   136

Definition at line 374 of file iop_sw_spu_defs.h.

#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_lo   132

Definition at line 366 of file iop_sw_spu_defs.h.

#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_set_mask   76

Definition at line 250 of file iop_sw_spu_defs.h.

#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_set_mask_hi   144

Definition at line 390 of file iop_sw_spu_defs.h.

#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_set_mask_lo   140

Definition at line 382 of file iop_sw_spu_defs.h.

#define REG_RD_ADDR_iop_sw_spu_rw_gio_set_mask   68

Definition at line 236 of file iop_sw_spu_defs.h.

#define REG_RD_ADDR_iop_sw_spu_rw_gio_set_mask_hi   128

Definition at line 358 of file iop_sw_spu_defs.h.

#define REG_RD_ADDR_iop_sw_spu_rw_gio_set_mask_lo   124

Definition at line 350 of file iop_sw_spu_defs.h.

#define REG_RD_ADDR_iop_sw_spu_rw_mc_addr   8

Definition at line 108 of file iop_sw_spu_defs.h.

#define REG_RD_ADDR_iop_sw_spu_rw_mc_ctrl   0

Definition at line 96 of file iop_sw_spu_defs.h.

#define REG_RD_ADDR_iop_sw_spu_rw_mc_data   4

Definition at line 103 of file iop_sw_spu_defs.h.

#define REG_RD_ADDR_iop_sw_spu_rw_mpu_intr   160

Definition at line 488 of file iop_sw_spu_defs.h.

#define REG_RD_INT	(		scope,
			inst,
			reg
	)		REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )

Definition at line 44 of file iop_sw_spu_defs.h.

#define REG_RD_INT_VECT	(		scope,
			inst,
			reg,
			index
	)

Value:

REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
        (index) * STRIDE_##scope##_##reg )

Definition at line 54 of file iop_sw_spu_defs.h.

#define REG_RD_VECT	(		scope,
			inst,
			reg,
			index
	)

Value:

REG_READ( reg_##scope##_##reg, \
            (inst) + REG_RD_ADDR_##scope##_##reg + \
        (index) * STRIDE_##scope##_##reg )

Definition at line 30 of file iop_sw_spu_defs.h.

#define REG_TYPE_CONV	(		type,
			orgtype,
			val
	)		( { union { orgtype o; type n; } r; r.o = val; r.n; } )

Definition at line 66 of file iop_sw_spu_defs.h.

#define REG_WR	(		scope,
			inst,
			reg,
			val
	)

Value:

REG_WRITE( reg_##scope##_##reg, \
             (inst) + REG_WR_ADDR_##scope##_##reg, (val) )

Definition at line 24 of file iop_sw_spu_defs.h.

#define REG_WR_ADDR_iop_sw_spu_rw_bus0_clr_mask   24

Definition at line 141 of file iop_sw_spu_defs.h.

#define REG_WR_ADDR_iop_sw_spu_rw_bus0_clr_mask_hi   88

Definition at line 273 of file iop_sw_spu_defs.h.

#define REG_WR_ADDR_iop_sw_spu_rw_bus0_clr_mask_lo   84

Definition at line 264 of file iop_sw_spu_defs.h.

#define REG_WR_ADDR_iop_sw_spu_rw_bus0_oe_clr_mask   32

Definition at line 162 of file iop_sw_spu_defs.h.

#define REG_WR_ADDR_iop_sw_spu_rw_bus0_oe_set_mask   36

Definition at line 173 of file iop_sw_spu_defs.h.

#define REG_WR_ADDR_iop_sw_spu_rw_bus0_set_mask   28

Definition at line 151 of file iop_sw_spu_defs.h.

#define REG_WR_ADDR_iop_sw_spu_rw_bus0_set_mask_hi   96

Definition at line 291 of file iop_sw_spu_defs.h.

#define REG_WR_ADDR_iop_sw_spu_rw_bus0_set_mask_lo   92

Definition at line 282 of file iop_sw_spu_defs.h.

#define REG_WR_ADDR_iop_sw_spu_rw_bus1_clr_mask   44

Definition at line 187 of file iop_sw_spu_defs.h.

#define REG_WR_ADDR_iop_sw_spu_rw_bus1_clr_mask_hi   104

Definition at line 309 of file iop_sw_spu_defs.h.

#define REG_WR_ADDR_iop_sw_spu_rw_bus1_clr_mask_lo   100

Definition at line 300 of file iop_sw_spu_defs.h.

#define REG_WR_ADDR_iop_sw_spu_rw_bus1_oe_clr_mask   52

Definition at line 208 of file iop_sw_spu_defs.h.

#define REG_WR_ADDR_iop_sw_spu_rw_bus1_oe_set_mask   56

Definition at line 219 of file iop_sw_spu_defs.h.

#define REG_WR_ADDR_iop_sw_spu_rw_bus1_set_mask   48

Definition at line 197 of file iop_sw_spu_defs.h.

#define REG_WR_ADDR_iop_sw_spu_rw_bus1_set_mask_hi   112

Definition at line 327 of file iop_sw_spu_defs.h.

#define REG_WR_ADDR_iop_sw_spu_rw_bus1_set_mask_lo   108

Definition at line 318 of file iop_sw_spu_defs.h.

#define REG_WR_ADDR_iop_sw_spu_rw_cpu_intr   148

Definition at line 414 of file iop_sw_spu_defs.h.

#define REG_WR_ADDR_iop_sw_spu_rw_gio_clr_mask   64

Definition at line 230 of file iop_sw_spu_defs.h.

#define REG_WR_ADDR_iop_sw_spu_rw_gio_clr_mask_hi   120

Definition at line 343 of file iop_sw_spu_defs.h.

#define REG_WR_ADDR_iop_sw_spu_rw_gio_clr_mask_lo   116

Definition at line 335 of file iop_sw_spu_defs.h.

#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_clr_mask   72

Definition at line 244 of file iop_sw_spu_defs.h.

#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_hi   136

Definition at line 375 of file iop_sw_spu_defs.h.

#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_lo   132

Definition at line 367 of file iop_sw_spu_defs.h.

#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_set_mask   76

Definition at line 251 of file iop_sw_spu_defs.h.

#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_set_mask_hi   144

Definition at line 391 of file iop_sw_spu_defs.h.

#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_set_mask_lo   140

Definition at line 383 of file iop_sw_spu_defs.h.

#define REG_WR_ADDR_iop_sw_spu_rw_gio_set_mask   68

Definition at line 237 of file iop_sw_spu_defs.h.

#define REG_WR_ADDR_iop_sw_spu_rw_gio_set_mask_hi   128

Definition at line 359 of file iop_sw_spu_defs.h.

#define REG_WR_ADDR_iop_sw_spu_rw_gio_set_mask_lo   124

Definition at line 351 of file iop_sw_spu_defs.h.

#define REG_WR_ADDR_iop_sw_spu_rw_mc_addr   8

Definition at line 109 of file iop_sw_spu_defs.h.

#define REG_WR_ADDR_iop_sw_spu_rw_mc_ctrl   0

Definition at line 97 of file iop_sw_spu_defs.h.

#define REG_WR_ADDR_iop_sw_spu_rw_mc_data   4

Definition at line 104 of file iop_sw_spu_defs.h.

#define REG_WR_ADDR_iop_sw_spu_rw_mpu_intr   160

Definition at line 489 of file iop_sw_spu_defs.h.

#define REG_WR_INT	(		scope,
			inst,
			reg,
			val
	)		REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )

Definition at line 49 of file iop_sw_spu_defs.h.

#define REG_WR_INT_VECT	(		scope,
			inst,
			reg,
			index,
			val
	)

Value:

REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
         (index) * STRIDE_##scope##_##reg, (val) )

Definition at line 60 of file iop_sw_spu_defs.h.

#define REG_WR_VECT	(		scope,
			inst,
			reg,
			index,
			val
	)

Value:

REG_WRITE( reg_##scope##_##reg, \
             (inst) + REG_WR_ADDR_##scope##_##reg + \
         (index) * STRIDE_##scope##_##reg, (val) )

Definition at line 37 of file iop_sw_spu_defs.h.

Typedef Documentation

typedef unsigned int reg_iop_sw_spu_r_bus0_in

Definition at line 176 of file iop_sw_spu_defs.h.

typedef unsigned int reg_iop_sw_spu_r_bus1_in

Definition at line 222 of file iop_sw_spu_defs.h.

typedef unsigned int reg_iop_sw_spu_r_gio_in

Definition at line 254 of file iop_sw_spu_defs.h.

typedef unsigned int reg_iop_sw_spu_r_mc_data

Definition at line 116 of file iop_sw_spu_defs.h.

typedef unsigned int reg_iop_sw_spu_rs_mc_data

Definition at line 112 of file iop_sw_spu_defs.h.

typedef unsigned int reg_iop_sw_spu_rw_mc_addr

Definition at line 107 of file iop_sw_spu_defs.h.

Enumeration Type Documentation

anonymous enum

Enumerator:

regk_iop_sw_spu_copy
regk_iop_sw_spu_no
regk_iop_sw_spu_nop
regk_iop_sw_spu_rd
regk_iop_sw_spu_reg_copy
regk_iop_sw_spu_rw_bus0_clr_mask_default
regk_iop_sw_spu_rw_bus0_oe_clr_mask_default
regk_iop_sw_spu_rw_bus0_oe_set_mask_default
regk_iop_sw_spu_rw_bus0_set_mask_default
regk_iop_sw_spu_rw_bus1_clr_mask_default
regk_iop_sw_spu_rw_bus1_oe_clr_mask_default
regk_iop_sw_spu_rw_bus1_oe_set_mask_default
regk_iop_sw_spu_rw_bus1_set_mask_default
regk_iop_sw_spu_rw_gio_clr_mask_default
regk_iop_sw_spu_rw_gio_oe_clr_mask_default
regk_iop_sw_spu_rw_gio_oe_set_mask_default
regk_iop_sw_spu_rw_gio_set_mask_default
regk_iop_sw_spu_set
regk_iop_sw_spu_wr
regk_iop_sw_spu_yes

Definition at line 530 of file iop_sw_spu_defs.h.