39 #include <asm/processor.h>
44 #define CNTR_OK (SYS_CNTRL_E0 | SYS_CNTRL_32S)
51 static struct clocksource au1x_counter1_clocksource = {
52 .name =
"alchemy-counter1",
53 .read = au1x_counter1_read,
59 static int au1x_rtcmatch2_set_next_event(
unsigned long delta,
60 struct clock_event_device *
cd)
72 static void au1x_rtcmatch2_set_mode(
enum clock_event_mode
mode,
73 struct clock_event_device *cd)
79 struct clock_event_device *cd =
dev_id;
80 cd->event_handler(cd);
84 static struct clock_event_device au1x_rtcmatch2_clockdev = {
86 .features = CLOCK_EVT_FEAT_ONESHOT,
88 .set_next_event = au1x_rtcmatch2_set_next_event,
89 .set_mode = au1x_rtcmatch2_set_mode,
93 static struct irqaction au1x_rtcmatch2_irqaction = {
94 .handler = au1x_rtcmatch2_irq,
97 .dev_id = &au1x_rtcmatch2_clockdev,
100 static int __init alchemy_time_init(
unsigned int m2int)
102 struct clock_event_device *cd = &au1x_rtcmatch2_clockdev;
105 au1x_rtcmatch2_clockdev.irq = m2int;
122 asm volatile (
"nop");
131 asm volatile (
"nop");
139 asm volatile (
"nop");
144 clocksource_register_hz(&au1x_counter1_clocksource, 32768);
151 setup_irq(m2int, &au1x_rtcmatch2_irqaction);
161 static void __init alchemy_setup_c0timer(
void)
188 t = alchemy_get_cputype();
190 alchemy_setup_c0timer();
191 else if (alchemy_time_init(alchemy_m2inttab[t]))
192 alchemy_setup_c0timer();