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au1000.h File Reference
#include <linux/delay.h>
#include <linux/types.h>
#include <linux/io.h>
#include <linux/irq.h>

Go to the source code of this file.

Data Structures

struct  alchemy_pci_platdata
 
struct  au1k_irda_platform_data
 

Macros

#define ALCHEMY_CPU_UNKNOWN   -1
 
#define ALCHEMY_CPU_AU1000   0
 
#define ALCHEMY_CPU_AU1500   1
 
#define ALCHEMY_CPU_AU1100   2
 
#define ALCHEMY_CPU_AU1550   3
 
#define ALCHEMY_CPU_AU1200   4
 
#define ALCHEMY_CPU_AU1300   5
 
#define AU1000_INTC0_INT_BASE   (MIPS_CPU_IRQ_BASE + 8)
 
#define AU1000_INTC0_INT_LAST   (AU1000_INTC0_INT_BASE + 31)
 
#define AU1000_INTC1_INT_BASE   (AU1000_INTC0_INT_LAST + 1)
 
#define AU1000_INTC1_INT_LAST   (AU1000_INTC1_INT_BASE + 31)
 
#define AU1000_MAX_INTR   AU1000_INTC1_INT_LAST
 
#define ALCHEMY_GPIC_INT_BASE   (MIPS_CPU_IRQ_BASE + 8)
 
#define ALCHEMY_GPIC_INT_NUM   128
 
#define ALCHEMY_GPIC_INT_LAST   (ALCHEMY_GPIC_INT_BASE + ALCHEMY_GPIC_INT_NUM - 1)
 
#define AU1300_FIRST_INT   (ALCHEMY_GPIC_INT_BASE)
 
#define AU1300_UART1_INT   (AU1300_FIRST_INT + 17)
 
#define AU1300_UART2_INT   (AU1300_FIRST_INT + 25)
 
#define AU1300_UART3_INT   (AU1300_FIRST_INT + 27)
 
#define AU1300_SD1_INT   (AU1300_FIRST_INT + 32)
 
#define AU1300_SD2_INT   (AU1300_FIRST_INT + 38)
 
#define AU1300_PSC0_INT   (AU1300_FIRST_INT + 48)
 
#define AU1300_PSC1_INT   (AU1300_FIRST_INT + 52)
 
#define AU1300_PSC2_INT   (AU1300_FIRST_INT + 56)
 
#define AU1300_PSC3_INT   (AU1300_FIRST_INT + 60)
 
#define AU1300_NAND_INT   (AU1300_FIRST_INT + 62)
 
#define AU1300_DDMA_INT   (AU1300_FIRST_INT + 75)
 
#define AU1300_MMU_INT   (AU1300_FIRST_INT + 76)
 
#define AU1300_MPU_INT   (AU1300_FIRST_INT + 77)
 
#define AU1300_GPU_INT   (AU1300_FIRST_INT + 78)
 
#define AU1300_UDMA_INT   (AU1300_FIRST_INT + 79)
 
#define AU1300_TOY_INT   (AU1300_FIRST_INT + 80)
 
#define AU1300_TOY_MATCH0_INT   (AU1300_FIRST_INT + 81)
 
#define AU1300_TOY_MATCH1_INT   (AU1300_FIRST_INT + 82)
 
#define AU1300_TOY_MATCH2_INT   (AU1300_FIRST_INT + 83)
 
#define AU1300_RTC_INT   (AU1300_FIRST_INT + 84)
 
#define AU1300_RTC_MATCH0_INT   (AU1300_FIRST_INT + 85)
 
#define AU1300_RTC_MATCH1_INT   (AU1300_FIRST_INT + 86)
 
#define AU1300_RTC_MATCH2_INT   (AU1300_FIRST_INT + 87)
 
#define AU1300_UART0_INT   (AU1300_FIRST_INT + 88)
 
#define AU1300_SD0_INT   (AU1300_FIRST_INT + 89)
 
#define AU1300_USB_INT   (AU1300_FIRST_INT + 90)
 
#define AU1300_LCD_INT   (AU1300_FIRST_INT + 91)
 
#define AU1300_BSA_INT   (AU1300_FIRST_INT + 92)
 
#define AU1300_MPE_INT   (AU1300_FIRST_INT + 93)
 
#define AU1300_ITE_INT   (AU1300_FIRST_INT + 94)
 
#define AU1300_AES_INT   (AU1300_FIRST_INT + 95)
 
#define AU1300_CIM_INT   (AU1300_FIRST_INT + 96)
 
#define AU1000_AC97_PHYS_ADDR   0x10000000 /* 012 */
 
#define AU1300_ROM_PHYS_ADDR   0x10000000 /* 5 */
 
#define AU1300_OTP_PHYS_ADDR   0x10002000 /* 5 */
 
#define AU1300_VSS_PHYS_ADDR   0x10003000 /* 5 */
 
#define AU1300_UART0_PHYS_ADDR   0x10100000 /* 5 */
 
#define AU1300_UART1_PHYS_ADDR   0x10101000 /* 5 */
 
#define AU1300_UART2_PHYS_ADDR   0x10102000 /* 5 */
 
#define AU1300_UART3_PHYS_ADDR   0x10103000 /* 5 */
 
#define AU1000_USB_OHCI_PHYS_ADDR   0x10100000 /* 012 */
 
#define AU1000_USB_UDC_PHYS_ADDR   0x10200000 /* 0123 */
 
#define AU1300_GPIC_PHYS_ADDR   0x10200000 /* 5 */
 
#define AU1000_IRDA_PHYS_ADDR   0x10300000 /* 02 */
 
#define AU1200_AES_PHYS_ADDR   0x10300000 /* 45 */
 
#define AU1000_IC0_PHYS_ADDR   0x10400000 /* 01234 */
 
#define AU1300_GPU_PHYS_ADDR   0x10500000 /* 5 */
 
#define AU1000_MAC0_PHYS_ADDR   0x10500000 /* 023 */
 
#define AU1000_MAC1_PHYS_ADDR   0x10510000 /* 023 */
 
#define AU1000_MACEN_PHYS_ADDR   0x10520000 /* 023 */
 
#define AU1100_SD0_PHYS_ADDR   0x10600000 /* 245 */
 
#define AU1300_SD1_PHYS_ADDR   0x10601000 /* 5 */
 
#define AU1300_SD2_PHYS_ADDR   0x10602000 /* 5 */
 
#define AU1100_SD1_PHYS_ADDR   0x10680000 /* 24 */
 
#define AU1300_SYS_PHYS_ADDR   0x10900000 /* 5 */
 
#define AU1550_PSC2_PHYS_ADDR   0x10A00000 /* 3 */
 
#define AU1550_PSC3_PHYS_ADDR   0x10B00000 /* 3 */
 
#define AU1300_PSC0_PHYS_ADDR   0x10A00000 /* 5 */
 
#define AU1300_PSC1_PHYS_ADDR   0x10A01000 /* 5 */
 
#define AU1300_PSC2_PHYS_ADDR   0x10A02000 /* 5 */
 
#define AU1300_PSC3_PHYS_ADDR   0x10A03000 /* 5 */
 
#define AU1000_I2S_PHYS_ADDR   0x11000000 /* 02 */
 
#define AU1500_MAC0_PHYS_ADDR   0x11500000 /* 1 */
 
#define AU1500_MAC1_PHYS_ADDR   0x11510000 /* 1 */
 
#define AU1500_MACEN_PHYS_ADDR   0x11520000 /* 1 */
 
#define AU1000_UART0_PHYS_ADDR   0x11100000 /* 01234 */
 
#define AU1200_SWCNT_PHYS_ADDR   0x1110010C /* 4 */
 
#define AU1000_UART1_PHYS_ADDR   0x11200000 /* 0234 */
 
#define AU1000_UART2_PHYS_ADDR   0x11300000 /* 0 */
 
#define AU1000_UART3_PHYS_ADDR   0x11400000 /* 0123 */
 
#define AU1000_SSI0_PHYS_ADDR   0x11600000 /* 02 */
 
#define AU1000_SSI1_PHYS_ADDR   0x11680000 /* 02 */
 
#define AU1500_GPIO2_PHYS_ADDR   0x11700000 /* 1234 */
 
#define AU1000_IC1_PHYS_ADDR   0x11800000 /* 01234 */
 
#define AU1000_SYS_PHYS_ADDR   0x11900000 /* 012345 */
 
#define AU1550_PSC0_PHYS_ADDR   0x11A00000 /* 34 */
 
#define AU1550_PSC1_PHYS_ADDR   0x11B00000 /* 34 */
 
#define AU1000_MEM_PHYS_ADDR   0x14000000 /* 01234 */
 
#define AU1000_STATIC_MEM_PHYS_ADDR   0x14001000 /* 01234 */
 
#define AU1300_UDMA_PHYS_ADDR   0x14001800 /* 5 */
 
#define AU1000_DMA_PHYS_ADDR   0x14002000 /* 012 */
 
#define AU1550_DBDMA_PHYS_ADDR   0x14002000 /* 345 */
 
#define AU1550_DBDMA_CONF_PHYS_ADDR   0x14003000 /* 345 */
 
#define AU1000_MACDMA0_PHYS_ADDR   0x14004000 /* 0123 */
 
#define AU1000_MACDMA1_PHYS_ADDR   0x14004200 /* 0123 */
 
#define AU1200_CIM_PHYS_ADDR   0x14004000 /* 45 */
 
#define AU1500_PCI_PHYS_ADDR   0x14005000 /* 13 */
 
#define AU1550_PE_PHYS_ADDR   0x14008000 /* 3 */
 
#define AU1200_MAEBE_PHYS_ADDR   0x14010000 /* 4 */
 
#define AU1200_MAEFE_PHYS_ADDR   0x14012000 /* 4 */
 
#define AU1300_MAEITE_PHYS_ADDR   0x14010000 /* 5 */
 
#define AU1300_MAEMPE_PHYS_ADDR   0x14014000 /* 5 */
 
#define AU1550_USB_OHCI_PHYS_ADDR   0x14020000 /* 3 */
 
#define AU1200_USB_CTL_PHYS_ADDR   0x14020000 /* 4 */
 
#define AU1200_USB_OTG_PHYS_ADDR   0x14020020 /* 4 */
 
#define AU1200_USB_OHCI_PHYS_ADDR   0x14020100 /* 4 */
 
#define AU1200_USB_EHCI_PHYS_ADDR   0x14020200 /* 4 */
 
#define AU1200_USB_UDC_PHYS_ADDR   0x14022000 /* 4 */
 
#define AU1300_USB_EHCI_PHYS_ADDR   0x14020000 /* 5 */
 
#define AU1300_USB_OHCI0_PHYS_ADDR   0x14020400 /* 5 */
 
#define AU1300_USB_OHCI1_PHYS_ADDR   0x14020800 /* 5 */
 
#define AU1300_USB_CTL_PHYS_ADDR   0x14021000 /* 5 */
 
#define AU1300_USB_OTG_PHYS_ADDR   0x14022000 /* 5 */
 
#define AU1300_MAEBSA_PHYS_ADDR   0x14030000 /* 5 */
 
#define AU1100_LCD_PHYS_ADDR   0x15000000 /* 2 */
 
#define AU1200_LCD_PHYS_ADDR   0x15000000 /* 45 */
 
#define AU1500_PCI_MEM_PHYS_ADDR   0x400000000ULL /* 13 */
 
#define AU1500_PCI_IO_PHYS_ADDR   0x500000000ULL /* 13 */
 
#define AU1500_PCI_CONFIG0_PHYS_ADDR   0x600000000ULL /* 13 */
 
#define AU1500_PCI_CONFIG1_PHYS_ADDR   0x680000000ULL /* 13 */
 
#define AU1000_PCMCIA_IO_PHYS_ADDR   0xF00000000ULL /* 012345 */
 
#define AU1000_PCMCIA_ATTR_PHYS_ADDR   0xF40000000ULL /* 012345 */
 
#define AU1000_PCMCIA_MEM_PHYS_ADDR   0xF80000000ULL /* 012345 */
 
#define AU1300_GPIC_PINVAL   0x0000
 
#define AU1300_GPIC_PINVALCLR   0x0010
 
#define AU1300_GPIC_IPEND   0x0020
 
#define AU1300_GPIC_PRIENC   0x0030
 
#define AU1300_GPIC_IEN   0x0040 /* int_mask in manual */
 
#define AU1300_GPIC_IDIS   0x0050 /* int_maskclr in manual */
 
#define AU1300_GPIC_DMASEL   0x0060
 
#define AU1300_GPIC_DEVSEL   0x0080
 
#define AU1300_GPIC_DEVCLR   0x0090
 
#define AU1300_GPIC_RSTVAL   0x00a0
 
#define AU1300_GPIC_PINCFG   0x1000
 
#define GPIC_GPIO_TO_BIT(gpio)   (1 << ((gpio) & 0x1f))
 
#define GPIC_GPIO_BANKOFF(gpio)   (((gpio) >> 5) * 4)
 
#define GPIC_CFG_PC_GPIN   0
 
#define GPIC_CFG_PC_DEV   1
 
#define GPIC_CFG_PC_GPOLOW   2
 
#define GPIC_CFG_PC_GPOHIGH   3
 
#define GPIC_CFG_PC_MASK   3
 
#define GPIC_CFG_IL_SET(x)   (((x) & 3) << 2)
 
#define GPIC_CFG_IL_MASK   (3 << 2)
 
#define GPIC_CFG_IC_OFF   (0 << 4)
 
#define GPIC_CFG_IC_LEVEL_LOW   (1 << 4)
 
#define GPIC_CFG_IC_LEVEL_HIGH   (2 << 4)
 
#define GPIC_CFG_IC_EDGE_FALL   (5 << 4)
 
#define GPIC_CFG_IC_EDGE_RISE   (6 << 4)
 
#define GPIC_CFG_IC_EDGE_BOTH   (7 << 4)
 
#define GPIC_CFG_IC_MASK   (7 << 4)
 
#define GPIC_CFG_IDLEWAKE   (1 << 7)
 
#define AU1000_MEM_SDMODE0   0x0000
 
#define AU1000_MEM_SDMODE1   0x0004
 
#define AU1000_MEM_SDMODE2   0x0008
 
#define AU1000_MEM_SDADDR0   0x000C
 
#define AU1000_MEM_SDADDR1   0x0010
 
#define AU1000_MEM_SDADDR2   0x0014
 
#define AU1000_MEM_SDREFCFG   0x0018
 
#define AU1000_MEM_SDPRECMD   0x001C
 
#define AU1000_MEM_SDAUTOREF   0x0020
 
#define AU1000_MEM_SDWRMD0   0x0024
 
#define AU1000_MEM_SDWRMD1   0x0028
 
#define AU1000_MEM_SDWRMD2   0x002C
 
#define AU1000_MEM_SDSLEEP   0x0030
 
#define AU1000_MEM_SDSMCKE   0x0034
 
#define MEM_SDMODE_F   (1 << 22)
 
#define MEM_SDMODE_SR   (1 << 21)
 
#define MEM_SDMODE_BS   (1 << 20)
 
#define MEM_SDMODE_RS   (3 << 18)
 
#define MEM_SDMODE_CS   (7 << 15)
 
#define MEM_SDMODE_TRAS   (15 << 11)
 
#define MEM_SDMODE_TMRD   (3 << 9)
 
#define MEM_SDMODE_TWR   (3 << 7)
 
#define MEM_SDMODE_TRP   (3 << 5)
 
#define MEM_SDMODE_TRCD   (3 << 3)
 
#define MEM_SDMODE_TCL   (7 << 0)
 
#define MEM_SDMODE_BS_2Bank   (0 << 20)
 
#define MEM_SDMODE_BS_4Bank   (1 << 20)
 
#define MEM_SDMODE_RS_11Row   (0 << 18)
 
#define MEM_SDMODE_RS_12Row   (1 << 18)
 
#define MEM_SDMODE_RS_13Row   (2 << 18)
 
#define MEM_SDMODE_RS_N(N)   ((N) << 18)
 
#define MEM_SDMODE_CS_7Col   (0 << 15)
 
#define MEM_SDMODE_CS_8Col   (1 << 15)
 
#define MEM_SDMODE_CS_9Col   (2 << 15)
 
#define MEM_SDMODE_CS_10Col   (3 << 15)
 
#define MEM_SDMODE_CS_11Col   (4 << 15)
 
#define MEM_SDMODE_CS_N(N)   ((N) << 15)
 
#define MEM_SDMODE_TRAS_N(N)   ((N) << 11)
 
#define MEM_SDMODE_TMRD_N(N)   ((N) << 9)
 
#define MEM_SDMODE_TWR_N(N)   ((N) << 7)
 
#define MEM_SDMODE_TRP_N(N)   ((N) << 5)
 
#define MEM_SDMODE_TRCD_N(N)   ((N) << 3)
 
#define MEM_SDMODE_TCL_N(N)   ((N) << 0)
 
#define MEM_SDADDR_E   (1 << 20)
 
#define MEM_SDADDR_CSBA   (0x03FF << 10)
 
#define MEM_SDADDR_CSMASK   (0x03FF << 0)
 
#define MEM_SDADDR_CSBA_N(N)   ((N) & (0x03FF << 22) >> 12)
 
#define MEM_SDADDR_CSMASK_N(N)   ((N)&(0x03FF << 22) >> 22)
 
#define MEM_SDREFCFG_TRC   (15 << 28)
 
#define MEM_SDREFCFG_TRPM   (3 << 26)
 
#define MEM_SDREFCFG_E   (1 << 25)
 
#define MEM_SDREFCFG_RE   (0x1ffffff << 0)
 
#define MEM_SDREFCFG_TRC_N(N)   ((N) << MEM_SDREFCFG_TRC)
 
#define MEM_SDREFCFG_TRPM_N(N)   ((N) << MEM_SDREFCFG_TRPM)
 
#define MEM_SDREFCFG_REF_N(N)   (N)
 
#define AU1550_MEM_SDMODE0   0x0800
 
#define AU1550_MEM_SDMODE1   0x0808
 
#define AU1550_MEM_SDMODE2   0x0810
 
#define AU1550_MEM_SDADDR0   0x0820
 
#define AU1550_MEM_SDADDR1   0x0828
 
#define AU1550_MEM_SDADDR2   0x0830
 
#define AU1550_MEM_SDCONFIGA   0x0840
 
#define AU1550_MEM_SDCONFIGB   0x0848
 
#define AU1550_MEM_SDSTAT   0x0850
 
#define AU1550_MEM_SDERRADDR   0x0858
 
#define AU1550_MEM_SDSTRIDE0   0x0860
 
#define AU1550_MEM_SDSTRIDE1   0x0868
 
#define AU1550_MEM_SDSTRIDE2   0x0870
 
#define AU1550_MEM_SDWRMD0   0x0880
 
#define AU1550_MEM_SDWRMD1   0x0888
 
#define AU1550_MEM_SDWRMD2   0x0890
 
#define AU1550_MEM_SDPRECMD   0x08C0
 
#define AU1550_MEM_SDAUTOREF   0x08C8
 
#define AU1550_MEM_SDSREF   0x08D0
 
#define AU1550_MEM_SDSLEEP   MEM_SDSREF
 
#define MEM_STCFG0   0xB4001000
 
#define MEM_STTIME0   0xB4001004
 
#define MEM_STADDR0   0xB4001008
 
#define MEM_STCFG1   0xB4001010
 
#define MEM_STTIME1   0xB4001014
 
#define MEM_STADDR1   0xB4001018
 
#define MEM_STCFG2   0xB4001020
 
#define MEM_STTIME2   0xB4001024
 
#define MEM_STADDR2   0xB4001028
 
#define MEM_STCFG3   0xB4001030
 
#define MEM_STTIME3   0xB4001034
 
#define MEM_STADDR3   0xB4001038
 
#define MEM_STNDCTL   0xB4001100
 
#define MEM_STSTAT   0xB4001104
 
#define MEM_STNAND_CMD   0x0
 
#define MEM_STNAND_ADDR   0x4
 
#define MEM_STNAND_DATA   0x20
 
#define SYS_BASE   0xB1900000
 
#define SYS_COUNTER_CNTRL   (SYS_BASE + 0x14)
 
#define SYS_CNTRL_E1S   (1 << 23)
 
#define SYS_CNTRL_T1S   (1 << 20)
 
#define SYS_CNTRL_M21   (1 << 19)
 
#define SYS_CNTRL_M11   (1 << 18)
 
#define SYS_CNTRL_M01   (1 << 17)
 
#define SYS_CNTRL_C1S   (1 << 16)
 
#define SYS_CNTRL_BP   (1 << 14)
 
#define SYS_CNTRL_EN1   (1 << 13)
 
#define SYS_CNTRL_BT1   (1 << 12)
 
#define SYS_CNTRL_EN0   (1 << 11)
 
#define SYS_CNTRL_BT0   (1 << 10)
 
#define SYS_CNTRL_E0   (1 << 8)
 
#define SYS_CNTRL_E0S   (1 << 7)
 
#define SYS_CNTRL_32S   (1 << 5)
 
#define SYS_CNTRL_T0S   (1 << 4)
 
#define SYS_CNTRL_M20   (1 << 3)
 
#define SYS_CNTRL_M10   (1 << 2)
 
#define SYS_CNTRL_M00   (1 << 1)
 
#define SYS_CNTRL_C0S   (1 << 0)
 
#define SYS_TOYTRIM   (SYS_BASE + 0)
 
#define SYS_TOYWRITE   (SYS_BASE + 4)
 
#define SYS_TOYMATCH0   (SYS_BASE + 8)
 
#define SYS_TOYMATCH1   (SYS_BASE + 0xC)
 
#define SYS_TOYMATCH2   (SYS_BASE + 0x10)
 
#define SYS_TOYREAD   (SYS_BASE + 0x40)
 
#define SYS_RTCTRIM   (SYS_BASE + 0x44)
 
#define SYS_RTCWRITE   (SYS_BASE + 0x48)
 
#define SYS_RTCMATCH0   (SYS_BASE + 0x4C)
 
#define SYS_RTCMATCH1   (SYS_BASE + 0x50)
 
#define SYS_RTCMATCH2   (SYS_BASE + 0x54)
 
#define SYS_RTCREAD   (SYS_BASE + 0x58)
 
#define I2S_DATA   0xB1000000
 
#define I2S_DATA_MASK   0xffffff
 
#define I2S_CONFIG   0xB1000004
 
#define I2S_CONFIG_XU   (1 << 25)
 
#define I2S_CONFIG_XO   (1 << 24)
 
#define I2S_CONFIG_RU   (1 << 23)
 
#define I2S_CONFIG_RO   (1 << 22)
 
#define I2S_CONFIG_TR   (1 << 21)
 
#define I2S_CONFIG_TE   (1 << 20)
 
#define I2S_CONFIG_TF   (1 << 19)
 
#define I2S_CONFIG_RR   (1 << 18)
 
#define I2S_CONFIG_RE   (1 << 17)
 
#define I2S_CONFIG_RF   (1 << 16)
 
#define I2S_CONFIG_PD   (1 << 11)
 
#define I2S_CONFIG_LB   (1 << 10)
 
#define I2S_CONFIG_IC   (1 << 9)
 
#define I2S_CONFIG_FM_BIT   7
 
#define I2S_CONFIG_FM_MASK   (0x3 << I2S_CONFIG_FM_BIT)
 
#define I2S_CONFIG_FM_I2S   (0x0 << I2S_CONFIG_FM_BIT)
 
#define I2S_CONFIG_FM_LJ   (0x1 << I2S_CONFIG_FM_BIT)
 
#define I2S_CONFIG_FM_RJ   (0x2 << I2S_CONFIG_FM_BIT)
 
#define I2S_CONFIG_TN   (1 << 6)
 
#define I2S_CONFIG_RN   (1 << 5)
 
#define I2S_CONFIG_SZ_BIT   0
 
#define I2S_CONFIG_SZ_MASK   (0x1F << I2S_CONFIG_SZ_BIT)
 
#define I2S_CONTROL   0xB1000008
 
#define I2S_CONTROL_D   (1 << 1)
 
#define I2S_CONTROL_CE   (1 << 0)
 
#define MAC_CONTROL   0x0
 
#define MAC_RX_ENABLE   (1 << 2)
 
#define MAC_TX_ENABLE   (1 << 3)
 
#define MAC_DEF_CHECK   (1 << 5)
 
#define MAC_SET_BL(X)   (((X) & 0x3) << 6)
 
#define MAC_AUTO_PAD   (1 << 8)
 
#define MAC_DISABLE_RETRY   (1 << 10)
 
#define MAC_DISABLE_BCAST   (1 << 11)
 
#define MAC_LATE_COL   (1 << 12)
 
#define MAC_HASH_MODE   (1 << 13)
 
#define MAC_HASH_ONLY   (1 << 15)
 
#define MAC_PASS_ALL   (1 << 16)
 
#define MAC_INVERSE_FILTER   (1 << 17)
 
#define MAC_PROMISCUOUS   (1 << 18)
 
#define MAC_PASS_ALL_MULTI   (1 << 19)
 
#define MAC_FULL_DUPLEX   (1 << 20)
 
#define MAC_NORMAL_MODE   0
 
#define MAC_INT_LOOPBACK   (1 << 21)
 
#define MAC_EXT_LOOPBACK   (1 << 22)
 
#define MAC_DISABLE_RX_OWN   (1 << 23)
 
#define MAC_BIG_ENDIAN   (1 << 30)
 
#define MAC_RX_ALL   (1 << 31)
 
#define MAC_ADDRESS_HIGH   0x4
 
#define MAC_ADDRESS_LOW   0x8
 
#define MAC_MCAST_HIGH   0xC
 
#define MAC_MCAST_LOW   0x10
 
#define MAC_MII_CNTRL   0x14
 
#define MAC_MII_BUSY   (1 << 0)
 
#define MAC_MII_READ   0
 
#define MAC_MII_WRITE   (1 << 1)
 
#define MAC_SET_MII_SELECT_REG(X)   (((X) & 0x1f) << 6)
 
#define MAC_SET_MII_SELECT_PHY(X)   (((X) & 0x1f) << 11)
 
#define MAC_MII_DATA   0x18
 
#define MAC_FLOW_CNTRL   0x1C
 
#define MAC_FLOW_CNTRL_BUSY   (1 << 0)
 
#define MAC_FLOW_CNTRL_ENABLE   (1 << 1)
 
#define MAC_PASS_CONTROL   (1 << 2)
 
#define MAC_SET_PAUSE(X)   (((X) & 0xffff) << 16)
 
#define MAC_VLAN1_TAG   0x20
 
#define MAC_VLAN2_TAG   0x24
 
#define MAC_EN_CLOCK_ENABLE   (1 << 0)
 
#define MAC_EN_RESET0   (1 << 1)
 
#define MAC_EN_TOSS   (0 << 2)
 
#define MAC_EN_CACHEABLE   (1 << 3)
 
#define MAC_EN_RESET1   (1 << 4)
 
#define MAC_EN_RESET2   (1 << 5)
 
#define MAC_DMA_RESET   (1 << 6)
 
#define MAC0_TX_DMA_ADDR   0xB4004000
 
#define MAC1_TX_DMA_ADDR   0xB4004200
 
#define MAC_TX_BUFF0_STATUS   0x0
 
#define TX_FRAME_ABORTED   (1 << 0)
 
#define TX_JAB_TIMEOUT   (1 << 1)
 
#define TX_NO_CARRIER   (1 << 2)
 
#define TX_LOSS_CARRIER   (1 << 3)
 
#define TX_EXC_DEF   (1 << 4)
 
#define TX_LATE_COLL_ABORT   (1 << 5)
 
#define TX_EXC_COLL   (1 << 6)
 
#define TX_UNDERRUN   (1 << 7)
 
#define TX_DEFERRED   (1 << 8)
 
#define TX_LATE_COLL   (1 << 9)
 
#define TX_COLL_CNT_MASK   (0xF << 10)
 
#define TX_PKT_RETRY   (1 << 31)
 
#define MAC_TX_BUFF0_ADDR   0x4
 
#define TX_DMA_ENABLE   (1 << 0)
 
#define TX_T_DONE   (1 << 1)
 
#define TX_GET_DMA_BUFFER(X)   (((X) >> 2) & 0x3)
 
#define MAC_TX_BUFF0_LEN   0x8
 
#define MAC_TX_BUFF1_STATUS   0x10
 
#define MAC_TX_BUFF1_ADDR   0x14
 
#define MAC_TX_BUFF1_LEN   0x18
 
#define MAC_TX_BUFF2_STATUS   0x20
 
#define MAC_TX_BUFF2_ADDR   0x24
 
#define MAC_TX_BUFF2_LEN   0x28
 
#define MAC_TX_BUFF3_STATUS   0x30
 
#define MAC_TX_BUFF3_ADDR   0x34
 
#define MAC_TX_BUFF3_LEN   0x38
 
#define MAC0_RX_DMA_ADDR   0xB4004100
 
#define MAC1_RX_DMA_ADDR   0xB4004300
 
#define MAC_RX_BUFF0_STATUS   0x0
 
#define RX_FRAME_LEN_MASK   0x3fff
 
#define RX_WDOG_TIMER   (1 << 14)
 
#define RX_RUNT   (1 << 15)
 
#define RX_OVERLEN   (1 << 16)
 
#define RX_COLL   (1 << 17)
 
#define RX_ETHER   (1 << 18)
 
#define RX_MII_ERROR   (1 << 19)
 
#define RX_DRIBBLING   (1 << 20)
 
#define RX_CRC_ERROR   (1 << 21)
 
#define RX_VLAN1   (1 << 22)
 
#define RX_VLAN2   (1 << 23)
 
#define RX_LEN_ERROR   (1 << 24)
 
#define RX_CNTRL_FRAME   (1 << 25)
 
#define RX_U_CNTRL_FRAME   (1 << 26)
 
#define RX_MCAST_FRAME   (1 << 27)
 
#define RX_BCAST_FRAME   (1 << 28)
 
#define RX_FILTER_FAIL   (1 << 29)
 
#define RX_PACKET_FILTER   (1 << 30)
 
#define RX_MISSED_FRAME   (1 << 31)
 
#define RX_ERROR
 
#define MAC_RX_BUFF0_ADDR   0x4
 
#define RX_DMA_ENABLE   (1 << 0)
 
#define RX_T_DONE   (1 << 1)
 
#define RX_GET_DMA_BUFFER(X)   (((X) >> 2) & 0x3)
 
#define RX_SET_BUFF_ADDR(X)   ((X) & 0xffffffc0)
 
#define MAC_RX_BUFF1_STATUS   0x10
 
#define MAC_RX_BUFF1_ADDR   0x14
 
#define MAC_RX_BUFF2_STATUS   0x20
 
#define MAC_RX_BUFF2_ADDR   0x24
 
#define MAC_RX_BUFF3_STATUS   0x30
 
#define MAC_RX_BUFF3_ADDR   0x34
 
#define UART_RX   0 /* Receive buffer */
 
#define UART_TX   4 /* Transmit buffer */
 
#define UART_IER   8 /* Interrupt Enable Register */
 
#define UART_IIR   0xC /* Interrupt ID Register */
 
#define UART_FCR   0x10 /* FIFO Control Register */
 
#define UART_LCR   0x14 /* Line Control Register */
 
#define UART_MCR   0x18 /* Modem Control Register */
 
#define UART_LSR   0x1C /* Line Status Register */
 
#define UART_MSR   0x20 /* Modem Status Register */
 
#define UART_CLK   0x28 /* Baud Rate Clock Divider */
 
#define UART_MOD_CNTRL   0x100 /* Module Control */
 
#define SSI0_STATUS   0xB1600000
 
#define SSI_STATUS_BF   (1 << 4)
 
#define SSI_STATUS_OF   (1 << 3)
 
#define SSI_STATUS_UF   (1 << 2)
 
#define SSI_STATUS_D   (1 << 1)
 
#define SSI_STATUS_B   (1 << 0)
 
#define SSI0_INT   0xB1600004
 
#define SSI_INT_OI   (1 << 3)
 
#define SSI_INT_UI   (1 << 2)
 
#define SSI_INT_DI   (1 << 1)
 
#define SSI0_INT_ENABLE   0xB1600008
 
#define SSI_INTE_OIE   (1 << 3)
 
#define SSI_INTE_UIE   (1 << 2)
 
#define SSI_INTE_DIE   (1 << 1)
 
#define SSI0_CONFIG   0xB1600020
 
#define SSI_CONFIG_AO   (1 << 24)
 
#define SSI_CONFIG_DO   (1 << 23)
 
#define SSI_CONFIG_ALEN_BIT   20
 
#define SSI_CONFIG_ALEN_MASK   (0x7 << 20)
 
#define SSI_CONFIG_DLEN_BIT   16
 
#define SSI_CONFIG_DLEN_MASK   (0x7 << 16)
 
#define SSI_CONFIG_DD   (1 << 11)
 
#define SSI_CONFIG_AD   (1 << 10)
 
#define SSI_CONFIG_BM_BIT   8
 
#define SSI_CONFIG_BM_MASK   (0x3 << 8)
 
#define SSI_CONFIG_CE   (1 << 7)
 
#define SSI_CONFIG_DP   (1 << 6)
 
#define SSI_CONFIG_DL   (1 << 5)
 
#define SSI_CONFIG_EP   (1 << 4)
 
#define SSI0_ADATA   0xB1600024
 
#define SSI_AD_D   (1 << 24)
 
#define SSI_AD_ADDR_BIT   16
 
#define SSI_AD_ADDR_MASK   (0xff << 16)
 
#define SSI_AD_DATA_BIT   0
 
#define SSI_AD_DATA_MASK   (0xfff << 0)
 
#define SSI0_CLKDIV   0xB1600028
 
#define SSI0_CONTROL   0xB1600100
 
#define SSI_CONTROL_CD   (1 << 1)
 
#define SSI_CONTROL_E   (1 << 0)
 
#define SSI1_STATUS   0xB1680000
 
#define SSI1_INT   0xB1680004
 
#define SSI1_INT_ENABLE   0xB1680008
 
#define SSI1_CONFIG   0xB1680020
 
#define SSI1_ADATA   0xB1680024
 
#define SSI1_CLKDIV   0xB1680028
 
#define SSI1_ENABLE   0xB1680100
 
#define SSI_STATUS_BF   (1 << 4)
 
#define SSI_STATUS_OF   (1 << 3)
 
#define SSI_STATUS_UF   (1 << 2)
 
#define SSI_STATUS_D   (1 << 1)
 
#define SSI_STATUS_B   (1 << 0)
 
#define SSI_INT_OI   (1 << 3)
 
#define SSI_INT_UI   (1 << 2)
 
#define SSI_INT_DI   (1 << 1)
 
#define SSI_INTEN_OIE   (1 << 3)
 
#define SSI_INTEN_UIE   (1 << 2)
 
#define SSI_INTEN_DIE   (1 << 1)
 
#define SSI_CONFIG_AO   (1 << 24)
 
#define SSI_CONFIG_DO   (1 << 23)
 
#define SSI_CONFIG_ALEN   (7 << 20)
 
#define SSI_CONFIG_DLEN   (15 << 16)
 
#define SSI_CONFIG_DD   (1 << 11)
 
#define SSI_CONFIG_AD   (1 << 10)
 
#define SSI_CONFIG_BM   (3 << 8)
 
#define SSI_CONFIG_CE   (1 << 7)
 
#define SSI_CONFIG_DP   (1 << 6)
 
#define SSI_CONFIG_DL   (1 << 5)
 
#define SSI_CONFIG_EP   (1 << 4)
 
#define SSI_CONFIG_ALEN_N(N)   ((N-1) << 20)
 
#define SSI_CONFIG_DLEN_N(N)   ((N-1) << 16)
 
#define SSI_CONFIG_BM_HI   (0 << 8)
 
#define SSI_CONFIG_BM_LO   (1 << 8)
 
#define SSI_CONFIG_BM_CY   (2 << 8)
 
#define SSI_ADATA_D   (1 << 24)
 
#define SSI_ADATA_ADDR   (0xFF << 16)
 
#define SSI_ADATA_DATA   0x0FFF
 
#define SSI_ADATA_ADDR_N(N)   (N << 16)
 
#define SSI_ENABLE_CD   (1 << 1)
 
#define SSI_ENABLE_E   (1 << 0)
 
#define AU1000_IRDA_PHY_MODE_OFF   0
 
#define AU1000_IRDA_PHY_MODE_SIR   1
 
#define AU1000_IRDA_PHY_MODE_FIR   2
 
#define SYS_PINFUNC   0xB190002C
 
#define SYS_PF_USB   (1 << 15) /* 2nd USB device/host */
 
#define SYS_PF_U3   (1 << 14) /* GPIO23/U3TXD */
 
#define SYS_PF_U2   (1 << 13) /* GPIO22/U2TXD */
 
#define SYS_PF_U1   (1 << 12) /* GPIO21/U1TXD */
 
#define SYS_PF_SRC   (1 << 11) /* GPIO6/SROMCKE */
 
#define SYS_PF_CK5   (1 << 10) /* GPIO3/CLK5 */
 
#define SYS_PF_CK4   (1 << 9) /* GPIO2/CLK4 */
 
#define SYS_PF_IRF   (1 << 8) /* GPIO15/IRFIRSEL */
 
#define SYS_PF_UR3   (1 << 7) /* GPIO[14:9]/UART3 */
 
#define SYS_PF_I2D   (1 << 6) /* GPIO8/I2SDI */
 
#define SYS_PF_I2S   (1 << 5) /* I2S/GPIO[29:31] */
 
#define SYS_PF_NI2   (1 << 4) /* NI2/GPIO[24:28] */
 
#define SYS_PF_U0   (1 << 3) /* U0TXD/GPIO20 */
 
#define SYS_PF_RD   (1 << 2) /* IRTXD/GPIO19 */
 
#define SYS_PF_A97   (1 << 1) /* AC97/SSL1 */
 
#define SYS_PF_S0   (1 << 0) /* SSI_0/GPIO[16:18] */
 
#define SYS_PF_PC   (1 << 18) /* PCMCIA/GPIO[207:204] */
 
#define SYS_PF_LCD   (1 << 17) /* extern lcd/GPIO[203:200] */
 
#define SYS_PF_CS   (1 << 16) /* EXTCLK0/32KHz to gpio2 */
 
#define SYS_PF_EX0   (1 << 9) /* GPIO2/clock */
 
#define SYS_PF_PSC2_MASK   (7 << 17)
 
#define SYS_PF_PSC2_AC97   0
 
#define SYS_PF_PSC2_SPI   0
 
#define SYS_PF_PSC2_I2S   (1 << 17)
 
#define SYS_PF_PSC2_SMBUS   (3 << 17)
 
#define SYS_PF_PSC2_GPIO   (7 << 17)
 
#define SYS_PF_PSC3_MASK   (7 << 20)
 
#define SYS_PF_PSC3_AC97   0
 
#define SYS_PF_PSC3_SPI   0
 
#define SYS_PF_PSC3_I2S   (1 << 20)
 
#define SYS_PF_PSC3_SMBUS   (3 << 20)
 
#define SYS_PF_PSC3_GPIO   (7 << 20)
 
#define SYS_PF_PSC1_S1   (1 << 1)
 
#define SYS_PF_MUST_BE_SET   ((1 << 5) | (1 << 2))
 
#define SYS_PINFUNC_DMA   (1 << 31)
 
#define SYS_PINFUNC_S0A   (1 << 30)
 
#define SYS_PINFUNC_S1A   (1 << 29)
 
#define SYS_PINFUNC_LP0   (1 << 28)
 
#define SYS_PINFUNC_LP1   (1 << 27)
 
#define SYS_PINFUNC_LD16   (1 << 26)
 
#define SYS_PINFUNC_LD8   (1 << 25)
 
#define SYS_PINFUNC_LD1   (1 << 24)
 
#define SYS_PINFUNC_LD0   (1 << 23)
 
#define SYS_PINFUNC_P1A   (3 << 21)
 
#define SYS_PINFUNC_P1B   (1 << 20)
 
#define SYS_PINFUNC_FS3   (1 << 19)
 
#define SYS_PINFUNC_P0A   (3 << 17)
 
#define SYS_PINFUNC_CS   (1 << 16)
 
#define SYS_PINFUNC_CIM   (1 << 15)
 
#define SYS_PINFUNC_P1C   (1 << 14)
 
#define SYS_PINFUNC_U1T   (1 << 12)
 
#define SYS_PINFUNC_U1R   (1 << 11)
 
#define SYS_PINFUNC_EX1   (1 << 10)
 
#define SYS_PINFUNC_EX0   (1 << 9)
 
#define SYS_PINFUNC_U0R   (1 << 8)
 
#define SYS_PINFUNC_MC   (1 << 7)
 
#define SYS_PINFUNC_S0B   (1 << 6)
 
#define SYS_PINFUNC_S0C   (1 << 5)
 
#define SYS_PINFUNC_P0B   (1 << 4)
 
#define SYS_PINFUNC_U0T   (1 << 3)
 
#define SYS_PINFUNC_S1B   (1 << 2)
 
#define SYS_SCRATCH0   0xB1900018
 
#define SYS_SCRATCH1   0xB190001C
 
#define SYS_WAKEMSK   0xB1900034
 
#define SYS_ENDIAN   0xB1900038
 
#define SYS_POWERCTRL   0xB190003C
 
#define SYS_WAKESRC   0xB190005C
 
#define SYS_SLPPWR   0xB1900078
 
#define SYS_SLEEP   0xB190007C
 
#define SYS_WAKEMSK_D2   (1 << 9)
 
#define SYS_WAKEMSK_M2   (1 << 8)
 
#define SYS_WAKEMSK_GPIO(x)   (1 << (x))
 
#define SYS_FREQCTRL0   0xB1900020
 
#define SYS_FC_FRDIV2_BIT   22
 
#define SYS_FC_FRDIV2_MASK   (0xff << SYS_FC_FRDIV2_BIT)
 
#define SYS_FC_FE2   (1 << 21)
 
#define SYS_FC_FS2   (1 << 20)
 
#define SYS_FC_FRDIV1_BIT   12
 
#define SYS_FC_FRDIV1_MASK   (0xff << SYS_FC_FRDIV1_BIT)
 
#define SYS_FC_FE1   (1 << 11)
 
#define SYS_FC_FS1   (1 << 10)
 
#define SYS_FC_FRDIV0_BIT   2
 
#define SYS_FC_FRDIV0_MASK   (0xff << SYS_FC_FRDIV0_BIT)
 
#define SYS_FC_FE0   (1 << 1)
 
#define SYS_FC_FS0   (1 << 0)
 
#define SYS_FREQCTRL1   0xB1900024
 
#define SYS_FC_FRDIV5_BIT   22
 
#define SYS_FC_FRDIV5_MASK   (0xff << SYS_FC_FRDIV5_BIT)
 
#define SYS_FC_FE5   (1 << 21)
 
#define SYS_FC_FS5   (1 << 20)
 
#define SYS_FC_FRDIV4_BIT   12
 
#define SYS_FC_FRDIV4_MASK   (0xff << SYS_FC_FRDIV4_BIT)
 
#define SYS_FC_FE4   (1 << 11)
 
#define SYS_FC_FS4   (1 << 10)
 
#define SYS_FC_FRDIV3_BIT   2
 
#define SYS_FC_FRDIV3_MASK   (0xff << SYS_FC_FRDIV3_BIT)
 
#define SYS_FC_FE3   (1 << 1)
 
#define SYS_FC_FS3   (1 << 0)
 
#define SYS_CLKSRC   0xB1900028
 
#define SYS_CS_ME1_BIT   27
 
#define SYS_CS_ME1_MASK   (0x7 << SYS_CS_ME1_BIT)
 
#define SYS_CS_DE1   (1 << 26)
 
#define SYS_CS_CE1   (1 << 25)
 
#define SYS_CS_ME0_BIT   22
 
#define SYS_CS_ME0_MASK   (0x7 << SYS_CS_ME0_BIT)
 
#define SYS_CS_DE0   (1 << 21)
 
#define SYS_CS_CE0   (1 << 20)
 
#define SYS_CS_MI2_BIT   17
 
#define SYS_CS_MI2_MASK   (0x7 << SYS_CS_MI2_BIT)
 
#define SYS_CS_DI2   (1 << 16)
 
#define SYS_CS_CI2   (1 << 15)
 
#define SYS_CS_ML_BIT   7
 
#define SYS_CS_ML_MASK   (0x7 << SYS_CS_ML_BIT)
 
#define SYS_CS_DL   (1 << 6)
 
#define SYS_CS_CL   (1 << 5)
 
#define SYS_CS_MUH_BIT   12
 
#define SYS_CS_MUH_MASK   (0x7 << SYS_CS_MUH_BIT)
 
#define SYS_CS_DUH   (1 << 11)
 
#define SYS_CS_CUH   (1 << 10)
 
#define SYS_CS_MUD_BIT   7
 
#define SYS_CS_MUD_MASK   (0x7 << SYS_CS_MUD_BIT)
 
#define SYS_CS_DUD   (1 << 6)
 
#define SYS_CS_CUD   (1 << 5)
 
#define SYS_CS_MIR_BIT   2
 
#define SYS_CS_MIR_MASK   (0x7 << SYS_CS_MIR_BIT)
 
#define SYS_CS_DIR   (1 << 1)
 
#define SYS_CS_CIR   (1 << 0)
 
#define SYS_CS_MUX_AUX   0x1
 
#define SYS_CS_MUX_FQ0   0x2
 
#define SYS_CS_MUX_FQ1   0x3
 
#define SYS_CS_MUX_FQ2   0x4
 
#define SYS_CS_MUX_FQ3   0x5
 
#define SYS_CS_MUX_FQ4   0x6
 
#define SYS_CS_MUX_FQ5   0x7
 
#define SYS_CPUPLL   0xB1900060
 
#define SYS_AUXPLL   0xB1900064
 
#define AC97C_CONFIG   0xB0000000
 
#define AC97C_RECV_SLOTS_BIT   13
 
#define AC97C_RECV_SLOTS_MASK   (0x3ff << AC97C_RECV_SLOTS_BIT)
 
#define AC97C_XMIT_SLOTS_BIT   3
 
#define AC97C_XMIT_SLOTS_MASK   (0x3ff << AC97C_XMIT_SLOTS_BIT)
 
#define AC97C_SG   (1 << 2)
 
#define AC97C_SYNC   (1 << 1)
 
#define AC97C_RESET   (1 << 0)
 
#define AC97C_STATUS   0xB0000004
 
#define AC97C_XU   (1 << 11)
 
#define AC97C_XO   (1 << 10)
 
#define AC97C_RU   (1 << 9)
 
#define AC97C_RO   (1 << 8)
 
#define AC97C_READY   (1 << 7)
 
#define AC97C_CP   (1 << 6)
 
#define AC97C_TR   (1 << 5)
 
#define AC97C_TE   (1 << 4)
 
#define AC97C_TF   (1 << 3)
 
#define AC97C_RR   (1 << 2)
 
#define AC97C_RE   (1 << 1)
 
#define AC97C_RF   (1 << 0)
 
#define AC97C_DATA   0xB0000008
 
#define AC97C_CMD   0xB000000C
 
#define AC97C_WD_BIT   16
 
#define AC97C_READ   (1 << 7)
 
#define AC97C_INDEX_MASK   0x7f
 
#define AC97C_CNTRL   0xB0000010
 
#define AC97C_RS   (1 << 1)
 
#define AC97C_CE   (1 << 0)
 
#define ALCHEMY_PCI_MEMWIN_START   (AU1500_PCI_MEM_PHYS_ADDR >> 4)
 
#define ALCHEMY_PCI_MEMWIN_END   (ALCHEMY_PCI_MEMWIN_START + 0x0FFFFFFF)
 
#define ALCHEMY_PCI_IOWIN_START   0x00001000
 
#define ALCHEMY_PCI_IOWIN_END   0x0000FFFF
 
#define IOPORT_RESOURCE_START   0x10000000
 
#define IOPORT_RESOURCE_END   0xffffffff
 
#define IOMEM_RESOURCE_START   0x10000000
 
#define IOMEM_RESOURCE_END   0xfffffffffULL
 
#define PCI_REG_CMEM   0x0000
 
#define PCI_REG_CONFIG   0x0004
 
#define PCI_REG_B2BMASK_CCH   0x0008
 
#define PCI_REG_B2BBASE0_VID   0x000C
 
#define PCI_REG_B2BBASE1_SID   0x0010
 
#define PCI_REG_MWMASK_DEV   0x0014
 
#define PCI_REG_MWBASE_REV_CCL   0x0018
 
#define PCI_REG_ERR_ADDR   0x001C
 
#define PCI_REG_SPEC_INTACK   0x0020
 
#define PCI_REG_ID   0x0100
 
#define PCI_REG_STATCMD   0x0104
 
#define PCI_REG_CLASSREV   0x0108
 
#define PCI_REG_PARAM   0x010C
 
#define PCI_REG_MBAR   0x0110
 
#define PCI_REG_TIMEOUT   0x0140
 
#define PCI_CMEM_E   (1 << 28) /* enable cacheable memory */
 
#define PCI_CMEM_CMBASE(x)   (((x) & 0x3fff) << 14)
 
#define PCI_CMEM_CMMASK(x)   ((x) & 0x3fff)
 
#define PCI_CONFIG_ERD   (1 << 27) /* pci error during R/W */
 
#define PCI_CONFIG_ET   (1 << 26) /* error in target mode */
 
#define PCI_CONFIG_EF   (1 << 25) /* fatal error */
 
#define PCI_CONFIG_EP   (1 << 24) /* parity error */
 
#define PCI_CONFIG_EM   (1 << 23) /* multiple errors */
 
#define PCI_CONFIG_BM   (1 << 22) /* bad master error */
 
#define PCI_CONFIG_PD   (1 << 20) /* PCI Disable */
 
#define PCI_CONFIG_BME   (1 << 19) /* Byte Mask Enable for reads */
 
#define PCI_CONFIG_NC   (1 << 16) /* mark mem access non-coherent */
 
#define PCI_CONFIG_IA   (1 << 15) /* INTA# enabled (target mode) */
 
#define PCI_CONFIG_IP   (1 << 13) /* int on PCI_PERR# */
 
#define PCI_CONFIG_IS   (1 << 12) /* int on PCI_SERR# */
 
#define PCI_CONFIG_IMM   (1 << 11) /* int on master abort */
 
#define PCI_CONFIG_ITM   (1 << 10) /* int on target abort (as master) */
 
#define PCI_CONFIG_ITT   (1 << 9) /* int on target abort (as target) */
 
#define PCI_CONFIG_IPB   (1 << 8) /* int on PERR# in bus master acc */
 
#define PCI_CONFIG_SIC_NO   (0 << 6) /* no byte mask changes */
 
#define PCI_CONFIG_SIC_BA_ADR   (1 << 6) /* on byte/hw acc, invert adr bits */
 
#define PCI_CONFIG_SIC_HWA_DAT   (2 << 6) /* on halfword acc, swap data */
 
#define PCI_CONFIG_SIC_ALL   (3 << 6) /* swap data bytes on all accesses */
 
#define PCI_CONFIG_ST   (1 << 5) /* swap data by target transactions */
 
#define PCI_CONFIG_SM   (1 << 4) /* swap data from PCI ctl */
 
#define PCI_CONFIG_AEN   (1 << 3) /* enable internal arbiter */
 
#define PCI_CONFIG_R2H   (1 << 2) /* REQ2# to hi-prio arbiter */
 
#define PCI_CONFIG_R1H   (1 << 1) /* REQ1# to hi-prio arbiter */
 
#define PCI_CONFIG_CH   (1 << 0) /* PCI ctl to hi-prio arbiter */
 
#define PCI_B2BMASK_B2BMASK(x)   (((x) & 0xffff) << 16)
 
#define PCI_B2BMASK_CCH(x)   ((x) & 0xffff) /* 16 upper bits of class code */
 
#define PCI_B2BBASE0_VID_B0(x)   (((x) & 0xffff) << 16)
 
#define PCI_B2BBASE0_VID_SV(x)   ((x) & 0xffff)
 
#define PCI_B2BBASE1_SID_B1(x)   (((x) & 0xffff) << 16)
 
#define PCI_B2BBASE1_SID_SI(x)   ((x) & 0xffff)
 
#define PCI_MWMASKDEV_MWMASK(x)   (((x) & 0xffff) << 16)
 
#define PCI_MWMASKDEV_DEVID(x)   ((x) & 0xffff)
 
#define PCI_MWBASEREVCCL_BASE(x)   (((x) & 0xffff) << 16)
 
#define PCI_MWBASEREVCCL_REV(x)   (((x) & 0xff) << 8)
 
#define PCI_MWBASEREVCCL_CCL(x)   ((x) & 0xff)
 
#define PCI_ID_DID(x)   (((x) & 0xffff) << 16)
 
#define PCI_ID_VID(x)   ((x) & 0xffff)
 
#define PCI_STATCMD_STATUS(x)   (((x) & 0xffff) << 16)
 
#define PCI_STATCMD_CMD(x)   ((x) & 0xffff)
 
#define PCI_CLASSREV_CLASS(x)   (((x) & 0x00ffffff) << 8)
 
#define PCI_CLASSREV_REV(x)   ((x) & 0xff)
 
#define PCI_PARAM_BIST(x)   (((x) & 0xff) << 24)
 
#define PCI_PARAM_HT(x)   (((x) & 0xff) << 16)
 
#define PCI_PARAM_LT(x)   (((x) & 0xff) << 8)
 
#define PCI_PARAM_CLS(x)   ((x) & 0xff)
 
#define PCI_TIMEOUT_RETRIES(x)   (((x) & 0xff) << 8) /* max retries */
 
#define PCI_TIMEOUT_TO(x)   ((x) & 0xff) /* target ready timeout */
 

Enumerations

enum  alchemy_usb_block {
  ALCHEMY_USB_OHCI0, ALCHEMY_USB_UDC0, ALCHEMY_USB_EHCI0, ALCHEMY_USB_OTG0,
  ALCHEMY_USB_OHCI1
}
 
enum  au1300_multifunc_pins {
  AU1300_PIN_WAKE0 = 0, AU1300_PIN_WAKE1, AU1300_PIN_WAKE2, AU1300_PIN_WAKE3,
  AU1300_PIN_EXTCLK0, AU1300_PIN_EXTCLK1, AU1300_PIN_SD0DAT4, AU1300_PIN_SD0DAT5,
  AU1300_PIN_SD0DAT6, AU1300_PIN_SD0DAT7, AU1300_PIN_FG3AUX, AU1300_PIN_U1RI,
  AU1300_PIN_U1DCD, AU1300_PIN_U1DSR, AU1300_PIN_U1CTS, AU1300_PIN_U1RTS,
  AU1300_PIN_U1DTR, AU1300_PIN_U1RX, AU1300_PIN_U1TX, AU1300_PIN_U0RI,
  AU1300_PIN_U0DCD, AU1300_PIN_U0DSR, AU1300_PIN_U0CTS, AU1300_PIN_U0RTS,
  AU1300_PIN_U0DTR, AU1300_PIN_U2RX, AU1300_PIN_U2TX, AU1300_PIN_U3RX,
  AU1300_PIN_U3TX, AU1300_PIN_LCDPWM0, AU1300_PIN_LCDPWM1, AU1300_PIN_LCDCLKIN,
  AU1300_PIN_SD1DAT0, AU1300_PIN_SD1DAT1, AU1300_PIN_SD1DAT2, AU1300_PIN_SD1DAT3,
  AU1300_PIN_SD1CMD, AU1300_PIN_SD1CLK, AU1300_PIN_SD2DAT0, AU1300_PIN_SD2DAT1,
  AU1300_PIN_SD2DAT2, AU1300_PIN_SD2DAT3, AU1300_PIN_SD2CMD, AU1300_PIN_SD2CLK,
  AU1300_PIN_PSC0CLK, AU1300_PIN_PSC1CLK, AU1300_PIN_PSC0SYNC0, AU1300_PIN_PSC0SYNC1,
  AU1300_PIN_PSC0D0, AU1300_PIN_PSC0D1, AU1300_PIN_PSC1SYNC0, AU1300_PIN_PSC1SYNC1,
  AU1300_PIN_PSC1D0, AU1300_PIN_PSC1D1, AU1300_PIN_PSC2SYNC0, AU1300_PIN_PSC2SYNC1,
  AU1300_PIN_PSC2D0, AU1300_PIN_PSC2D1, AU1300_PIN_PSC3SYNC0, AU1300_PIN_PSC3SYNC1,
  AU1300_PIN_PSC3D0, AU1300_PIN_PSC3D1, AU1300_PIN_PCE2, AU1300_PIN_PCE1,
  AU1300_PIN_PIOS16, AU1300_PIN_PIOR, AU1300_PIN_PWE, AU1300_PIN_PWAIT,
  AU1300_PIN_PREG, AU1300_PIN_POE, AU1300_PIN_PIOW, AU1300_PIN_CIMLS,
  AU1300_PIN_CIMFS, AU1300_PIN_PSC2CLK, AU1300_PIN_PSC3CLK
}
 
enum  au1300_vss_block { AU1300_VSS_MPE = 0, AU1300_VSS_BSA, AU1300_VSS_GPE, AU1300_VSS_MGP }
 
enum  soc_au1000_ints {
  AU1000_FIRST_INT = AU1000_INTC0_INT_BASE, AU1000_UART0_INT = AU1000_FIRST_INT, AU1000_UART1_INT, AU1000_UART2_INT,
  AU1000_UART3_INT, AU1000_SSI0_INT, AU1000_SSI1_INT, AU1000_DMA_INT_BASE,
  AU1000_TOY_INT = AU1000_FIRST_INT + 14, AU1000_TOY_MATCH0_INT, AU1000_TOY_MATCH1_INT, AU1000_TOY_MATCH2_INT,
  AU1000_RTC_INT, AU1000_RTC_MATCH0_INT, AU1000_RTC_MATCH1_INT, AU1000_RTC_MATCH2_INT,
  AU1000_IRDA_TX_INT, AU1000_IRDA_RX_INT, AU1000_USB_DEV_REQ_INT, AU1000_USB_DEV_SUS_INT,
  AU1000_USB_HOST_INT, AU1000_ACSYNC_INT, AU1000_MAC0_DMA_INT, AU1000_MAC1_DMA_INT,
  AU1000_I2S_UO_INT, AU1000_AC97C_INT, AU1000_GPIO0_INT, AU1000_GPIO1_INT,
  AU1000_GPIO2_INT, AU1000_GPIO3_INT, AU1000_GPIO4_INT, AU1000_GPIO5_INT,
  AU1000_GPIO6_INT, AU1000_GPIO7_INT, AU1000_GPIO8_INT, AU1000_GPIO9_INT,
  AU1000_GPIO10_INT, AU1000_GPIO11_INT, AU1000_GPIO12_INT, AU1000_GPIO13_INT,
  AU1000_GPIO14_INT, AU1000_GPIO15_INT, AU1000_GPIO16_INT, AU1000_GPIO17_INT,
  AU1000_GPIO18_INT, AU1000_GPIO19_INT, AU1000_GPIO20_INT, AU1000_GPIO21_INT,
  AU1000_GPIO22_INT, AU1000_GPIO23_INT, AU1000_GPIO24_INT, AU1000_GPIO25_INT,
  AU1000_GPIO26_INT, AU1000_GPIO27_INT, AU1000_GPIO28_INT, AU1000_GPIO29_INT,
  AU1000_GPIO30_INT, AU1000_GPIO31_INT
}
 
enum  soc_au1100_ints {
  AU1100_FIRST_INT = AU1000_INTC0_INT_BASE, AU1100_UART0_INT = AU1100_FIRST_INT, AU1100_UART1_INT, AU1100_SD_INT,
  AU1100_UART3_INT, AU1100_SSI0_INT, AU1100_SSI1_INT, AU1100_DMA_INT_BASE,
  AU1100_TOY_INT = AU1100_FIRST_INT + 14, AU1100_TOY_MATCH0_INT, AU1100_TOY_MATCH1_INT, AU1100_TOY_MATCH2_INT,
  AU1100_RTC_INT, AU1100_RTC_MATCH0_INT, AU1100_RTC_MATCH1_INT, AU1100_RTC_MATCH2_INT,
  AU1100_IRDA_TX_INT, AU1100_IRDA_RX_INT, AU1100_USB_DEV_REQ_INT, AU1100_USB_DEV_SUS_INT,
  AU1100_USB_HOST_INT, AU1100_ACSYNC_INT, AU1100_MAC0_DMA_INT, AU1100_GPIO208_215_INT,
  AU1100_LCD_INT, AU1100_AC97C_INT, AU1100_GPIO0_INT, AU1100_GPIO1_INT,
  AU1100_GPIO2_INT, AU1100_GPIO3_INT, AU1100_GPIO4_INT, AU1100_GPIO5_INT,
  AU1100_GPIO6_INT, AU1100_GPIO7_INT, AU1100_GPIO8_INT, AU1100_GPIO9_INT,
  AU1100_GPIO10_INT, AU1100_GPIO11_INT, AU1100_GPIO12_INT, AU1100_GPIO13_INT,
  AU1100_GPIO14_INT, AU1100_GPIO15_INT, AU1100_GPIO16_INT, AU1100_GPIO17_INT,
  AU1100_GPIO18_INT, AU1100_GPIO19_INT, AU1100_GPIO20_INT, AU1100_GPIO21_INT,
  AU1100_GPIO22_INT, AU1100_GPIO23_INT, AU1100_GPIO24_INT, AU1100_GPIO25_INT,
  AU1100_GPIO26_INT, AU1100_GPIO27_INT, AU1100_GPIO28_INT, AU1100_GPIO29_INT,
  AU1100_GPIO30_INT, AU1100_GPIO31_INT
}
 
enum  soc_au1500_ints {
  AU1500_FIRST_INT = AU1000_INTC0_INT_BASE, AU1500_UART0_INT = AU1500_FIRST_INT, AU1500_PCI_INTA, AU1500_PCI_INTB,
  AU1500_UART3_INT, AU1500_PCI_INTC, AU1500_PCI_INTD, AU1500_DMA_INT_BASE,
  AU1500_TOY_INT = AU1500_FIRST_INT + 14, AU1500_TOY_MATCH0_INT, AU1500_TOY_MATCH1_INT, AU1500_TOY_MATCH2_INT,
  AU1500_RTC_INT, AU1500_RTC_MATCH0_INT, AU1500_RTC_MATCH1_INT, AU1500_RTC_MATCH2_INT,
  AU1500_PCI_ERR_INT, AU1500_RESERVED_INT, AU1500_USB_DEV_REQ_INT, AU1500_USB_DEV_SUS_INT,
  AU1500_USB_HOST_INT, AU1500_ACSYNC_INT, AU1500_MAC0_DMA_INT, AU1500_MAC1_DMA_INT,
  AU1500_AC97C_INT = AU1500_FIRST_INT + 31, AU1500_GPIO0_INT, AU1500_GPIO1_INT, AU1500_GPIO2_INT,
  AU1500_GPIO3_INT, AU1500_GPIO4_INT, AU1500_GPIO5_INT, AU1500_GPIO6_INT,
  AU1500_GPIO7_INT, AU1500_GPIO8_INT, AU1500_GPIO9_INT, AU1500_GPIO10_INT,
  AU1500_GPIO11_INT, AU1500_GPIO12_INT, AU1500_GPIO13_INT, AU1500_GPIO14_INT,
  AU1500_GPIO15_INT, AU1500_GPIO200_INT, AU1500_GPIO201_INT, AU1500_GPIO202_INT,
  AU1500_GPIO203_INT, AU1500_GPIO20_INT, AU1500_GPIO204_INT, AU1500_GPIO205_INT,
  AU1500_GPIO23_INT, AU1500_GPIO24_INT, AU1500_GPIO25_INT, AU1500_GPIO26_INT,
  AU1500_GPIO27_INT, AU1500_GPIO28_INT, AU1500_GPIO206_INT, AU1500_GPIO207_INT,
  AU1500_GPIO208_215_INT
}
 
enum  soc_au1550_ints {
  AU1550_FIRST_INT = AU1000_INTC0_INT_BASE, AU1550_UART0_INT = AU1550_FIRST_INT, AU1550_PCI_INTA, AU1550_PCI_INTB,
  AU1550_DDMA_INT, AU1550_CRYPTO_INT, AU1550_PCI_INTC, AU1550_PCI_INTD,
  AU1550_PCI_RST_INT, AU1550_UART1_INT, AU1550_UART3_INT, AU1550_PSC0_INT,
  AU1550_PSC1_INT, AU1550_PSC2_INT, AU1550_PSC3_INT, AU1550_TOY_INT,
  AU1550_TOY_MATCH0_INT, AU1550_TOY_MATCH1_INT, AU1550_TOY_MATCH2_INT, AU1550_RTC_INT,
  AU1550_RTC_MATCH0_INT, AU1550_RTC_MATCH1_INT, AU1550_RTC_MATCH2_INT, AU1550_NAND_INT = AU1550_FIRST_INT + 23,
  AU1550_USB_DEV_REQ_INT, AU1550_USB_DEV_SUS_INT, AU1550_USB_HOST_INT, AU1550_MAC0_DMA_INT,
  AU1550_MAC1_DMA_INT, AU1550_GPIO0_INT = AU1550_FIRST_INT + 32, AU1550_GPIO1_INT, AU1550_GPIO2_INT,
  AU1550_GPIO3_INT, AU1550_GPIO4_INT, AU1550_GPIO5_INT, AU1550_GPIO6_INT,
  AU1550_GPIO7_INT, AU1550_GPIO8_INT, AU1550_GPIO9_INT, AU1550_GPIO10_INT,
  AU1550_GPIO11_INT, AU1550_GPIO12_INT, AU1550_GPIO13_INT, AU1550_GPIO14_INT,
  AU1550_GPIO15_INT, AU1550_GPIO200_INT, AU1550_GPIO201_205_INT, AU1550_GPIO16_INT,
  AU1550_GPIO17_INT, AU1550_GPIO20_INT, AU1550_GPIO21_INT, AU1550_GPIO22_INT,
  AU1550_GPIO23_INT, AU1550_GPIO24_INT, AU1550_GPIO25_INT, AU1550_GPIO26_INT,
  AU1550_GPIO27_INT, AU1550_GPIO28_INT, AU1550_GPIO206_INT, AU1550_GPIO207_INT,
  AU1550_GPIO208_215_INT
}
 
enum  soc_au1200_ints {
  AU1200_FIRST_INT = AU1000_INTC0_INT_BASE, AU1200_UART0_INT = AU1200_FIRST_INT, AU1200_SWT_INT, AU1200_SD_INT,
  AU1200_DDMA_INT, AU1200_MAE_BE_INT, AU1200_GPIO200_INT, AU1200_GPIO201_INT,
  AU1200_GPIO202_INT, AU1200_UART1_INT, AU1200_MAE_FE_INT, AU1200_PSC0_INT,
  AU1200_PSC1_INT, AU1200_AES_INT, AU1200_CAMERA_INT, AU1200_TOY_INT,
  AU1200_TOY_MATCH0_INT, AU1200_TOY_MATCH1_INT, AU1200_TOY_MATCH2_INT, AU1200_RTC_INT,
  AU1200_RTC_MATCH0_INT, AU1200_RTC_MATCH1_INT, AU1200_RTC_MATCH2_INT, AU1200_GPIO203_INT,
  AU1200_NAND_INT, AU1200_GPIO204_INT, AU1200_GPIO205_INT, AU1200_GPIO206_INT,
  AU1200_GPIO207_INT, AU1200_GPIO208_215_INT, AU1200_USB_INT, AU1200_LCD_INT,
  AU1200_MAE_BOTH_INT, AU1200_GPIO0_INT, AU1200_GPIO1_INT, AU1200_GPIO2_INT,
  AU1200_GPIO3_INT, AU1200_GPIO4_INT, AU1200_GPIO5_INT, AU1200_GPIO6_INT,
  AU1200_GPIO7_INT, AU1200_GPIO8_INT, AU1200_GPIO9_INT, AU1200_GPIO10_INT,
  AU1200_GPIO11_INT, AU1200_GPIO12_INT, AU1200_GPIO13_INT, AU1200_GPIO14_INT,
  AU1200_GPIO15_INT, AU1200_GPIO16_INT, AU1200_GPIO17_INT, AU1200_GPIO18_INT,
  AU1200_GPIO19_INT, AU1200_GPIO20_INT, AU1200_GPIO21_INT, AU1200_GPIO22_INT,
  AU1200_GPIO23_INT, AU1200_GPIO24_INT, AU1200_GPIO25_INT, AU1200_GPIO26_INT,
  AU1200_GPIO27_INT, AU1200_GPIO28_INT, AU1200_GPIO29_INT, AU1200_GPIO30_INT,
  AU1200_GPIO31_INT
}
 

Functions

void set_au1x00_speed (unsigned int new_freq)
 
unsigned int get_au1x00_speed (void)
 
void set_au1x00_uart_baud_base (unsigned long new_baud_base)
 
unsigned long get_au1x00_uart_baud_base (void)
 
unsigned long au1xxx_calc_clock (void)
 
void alchemy_sleep_au1000 (void)
 
void alchemy_sleep_au1550 (void)
 
void alchemy_sleep_au1300 (void)
 
void au_sleep (void)
 
int alchemy_usb_control (int block, int enable)
 
void au1300_pinfunc_to_gpio (enum au1300_multifunc_pins gpio)
 
void au1300_pinfunc_to_dev (enum au1300_multifunc_pins gpio)
 
void au1300_set_irq_priority (unsigned int irq, int p)
 
void au1300_set_dbdma_gpio (int dchan, unsigned int gpio)
 
void au1300_vss_block_control (int block, int enable)
 

Macro Definition Documentation

#define AC97C_CE   (1 << 0)

Definition at line 1466 of file au1000.h.

#define AC97C_CMD   0xB000000C

Definition at line 1460 of file au1000.h.

#define AC97C_CNTRL   0xB0000010

Definition at line 1464 of file au1000.h.

#define AC97C_CONFIG   0xB0000000

Definition at line 1438 of file au1000.h.

#define AC97C_CP   (1 << 6)

Definition at line 1452 of file au1000.h.

#define AC97C_DATA   0xB0000008

Definition at line 1459 of file au1000.h.

#define AC97C_INDEX_MASK   0x7f

Definition at line 1463 of file au1000.h.

#define AC97C_RE   (1 << 1)

Definition at line 1457 of file au1000.h.

#define AC97C_READ   (1 << 7)

Definition at line 1462 of file au1000.h.

#define AC97C_READY   (1 << 7)

Definition at line 1451 of file au1000.h.

#define AC97C_RECV_SLOTS_BIT   13

Definition at line 1439 of file au1000.h.

#define AC97C_RECV_SLOTS_MASK   (0x3ff << AC97C_RECV_SLOTS_BIT)

Definition at line 1440 of file au1000.h.

#define AC97C_RESET   (1 << 0)

Definition at line 1445 of file au1000.h.

#define AC97C_RF   (1 << 0)

Definition at line 1458 of file au1000.h.

#define AC97C_RO   (1 << 8)

Definition at line 1450 of file au1000.h.

#define AC97C_RR   (1 << 2)

Definition at line 1456 of file au1000.h.

#define AC97C_RS   (1 << 1)

Definition at line 1465 of file au1000.h.

#define AC97C_RU   (1 << 9)

Definition at line 1449 of file au1000.h.

#define AC97C_SG   (1 << 2)

Definition at line 1443 of file au1000.h.

#define AC97C_STATUS   0xB0000004

Definition at line 1446 of file au1000.h.

#define AC97C_SYNC   (1 << 1)

Definition at line 1444 of file au1000.h.

#define AC97C_TE   (1 << 4)

Definition at line 1454 of file au1000.h.

#define AC97C_TF   (1 << 3)

Definition at line 1455 of file au1000.h.

#define AC97C_TR   (1 << 5)

Definition at line 1453 of file au1000.h.

#define AC97C_WD_BIT   16

Definition at line 1461 of file au1000.h.

#define AC97C_XMIT_SLOTS_BIT   3

Definition at line 1441 of file au1000.h.

#define AC97C_XMIT_SLOTS_MASK   (0x3ff << AC97C_XMIT_SLOTS_BIT)

Definition at line 1442 of file au1000.h.

#define AC97C_XO   (1 << 10)

Definition at line 1448 of file au1000.h.

#define AC97C_XU   (1 << 11)

Definition at line 1447 of file au1000.h.

#define ALCHEMY_CPU_AU1000   0

Definition at line 134 of file au1000.h.

#define ALCHEMY_CPU_AU1100   2

Definition at line 136 of file au1000.h.

#define ALCHEMY_CPU_AU1200   4

Definition at line 138 of file au1000.h.

#define ALCHEMY_CPU_AU1300   5

Definition at line 139 of file au1000.h.

#define ALCHEMY_CPU_AU1500   1

Definition at line 135 of file au1000.h.

#define ALCHEMY_CPU_AU1550   3

Definition at line 137 of file au1000.h.

#define ALCHEMY_CPU_UNKNOWN   -1

Definition at line 133 of file au1000.h.

#define ALCHEMY_GPIC_INT_BASE   (MIPS_CPU_IRQ_BASE + 8)

Definition at line 355 of file au1000.h.

#define ALCHEMY_GPIC_INT_LAST   (ALCHEMY_GPIC_INT_BASE + ALCHEMY_GPIC_INT_NUM - 1)

Definition at line 357 of file au1000.h.

#define ALCHEMY_GPIC_INT_NUM   128

Definition at line 356 of file au1000.h.

#define ALCHEMY_PCI_IOWIN_END   0x0000FFFF

Definition at line 1482 of file au1000.h.

#define ALCHEMY_PCI_IOWIN_START   0x00001000

Definition at line 1481 of file au1000.h.

#define ALCHEMY_PCI_MEMWIN_END   (ALCHEMY_PCI_MEMWIN_START + 0x0FFFFFFF)

Definition at line 1476 of file au1000.h.

#define ALCHEMY_PCI_MEMWIN_START   (AU1500_PCI_MEM_PHYS_ADDR >> 4)

Definition at line 1475 of file au1000.h.

#define AU1000_AC97_PHYS_ADDR   0x10000000 /* 012 */

Definition at line 721 of file au1000.h.

#define AU1000_DMA_PHYS_ADDR   0x14002000 /* 012 */

Definition at line 769 of file au1000.h.

#define AU1000_I2S_PHYS_ADDR   0x11000000 /* 02 */

Definition at line 750 of file au1000.h.

#define AU1000_IC0_PHYS_ADDR   0x10400000 /* 01234 */

Definition at line 734 of file au1000.h.

#define AU1000_IC1_PHYS_ADDR   0x11800000 /* 01234 */

Definition at line 762 of file au1000.h.

#define AU1000_INTC0_INT_BASE   (MIPS_CPU_IRQ_BASE + 8)

Definition at line 348 of file au1000.h.

#define AU1000_INTC0_INT_LAST   (AU1000_INTC0_INT_BASE + 31)

Definition at line 349 of file au1000.h.

#define AU1000_INTC1_INT_BASE   (AU1000_INTC0_INT_LAST + 1)

Definition at line 350 of file au1000.h.

#define AU1000_INTC1_INT_LAST   (AU1000_INTC1_INT_BASE + 31)

Definition at line 351 of file au1000.h.

#define AU1000_IRDA_PHY_MODE_FIR   2

Definition at line 1276 of file au1000.h.

#define AU1000_IRDA_PHY_MODE_OFF   0

Definition at line 1274 of file au1000.h.

#define AU1000_IRDA_PHY_MODE_SIR   1

Definition at line 1275 of file au1000.h.

#define AU1000_IRDA_PHYS_ADDR   0x10300000 /* 02 */

Definition at line 732 of file au1000.h.

#define AU1000_MAC0_PHYS_ADDR   0x10500000 /* 023 */

Definition at line 736 of file au1000.h.

#define AU1000_MAC1_PHYS_ADDR   0x10510000 /* 023 */

Definition at line 737 of file au1000.h.

#define AU1000_MACDMA0_PHYS_ADDR   0x14004000 /* 0123 */

Definition at line 772 of file au1000.h.

#define AU1000_MACDMA1_PHYS_ADDR   0x14004200 /* 0123 */

Definition at line 773 of file au1000.h.

#define AU1000_MACEN_PHYS_ADDR   0x10520000 /* 023 */

Definition at line 738 of file au1000.h.

#define AU1000_MAX_INTR   AU1000_INTC1_INT_LAST

Definition at line 352 of file au1000.h.

#define AU1000_MEM_PHYS_ADDR   0x14000000 /* 01234 */

Definition at line 766 of file au1000.h.

#define AU1000_MEM_SDADDR0   0x000C

Definition at line 858 of file au1000.h.

#define AU1000_MEM_SDADDR1   0x0010

Definition at line 859 of file au1000.h.

#define AU1000_MEM_SDADDR2   0x0014

Definition at line 860 of file au1000.h.

#define AU1000_MEM_SDAUTOREF   0x0020

Definition at line 863 of file au1000.h.

#define AU1000_MEM_SDMODE0   0x0000

Definition at line 855 of file au1000.h.

#define AU1000_MEM_SDMODE1   0x0004

Definition at line 856 of file au1000.h.

#define AU1000_MEM_SDMODE2   0x0008

Definition at line 857 of file au1000.h.

#define AU1000_MEM_SDPRECMD   0x001C

Definition at line 862 of file au1000.h.

#define AU1000_MEM_SDREFCFG   0x0018

Definition at line 861 of file au1000.h.

#define AU1000_MEM_SDSLEEP   0x0030

Definition at line 867 of file au1000.h.

#define AU1000_MEM_SDSMCKE   0x0034

Definition at line 868 of file au1000.h.

#define AU1000_MEM_SDWRMD0   0x0024

Definition at line 864 of file au1000.h.

#define AU1000_MEM_SDWRMD1   0x0028

Definition at line 865 of file au1000.h.

#define AU1000_MEM_SDWRMD2   0x002C

Definition at line 866 of file au1000.h.

#define AU1000_PCMCIA_ATTR_PHYS_ADDR   0xF40000000ULL /* 012345 */

Definition at line 800 of file au1000.h.

#define AU1000_PCMCIA_IO_PHYS_ADDR   0xF00000000ULL /* 012345 */

Definition at line 799 of file au1000.h.

#define AU1000_PCMCIA_MEM_PHYS_ADDR   0xF80000000ULL /* 012345 */

Definition at line 801 of file au1000.h.

#define AU1000_SSI0_PHYS_ADDR   0x11600000 /* 02 */

Definition at line 759 of file au1000.h.

#define AU1000_SSI1_PHYS_ADDR   0x11680000 /* 02 */

Definition at line 760 of file au1000.h.

#define AU1000_STATIC_MEM_PHYS_ADDR   0x14001000 /* 01234 */

Definition at line 767 of file au1000.h.

#define AU1000_SYS_PHYS_ADDR   0x11900000 /* 012345 */

Definition at line 763 of file au1000.h.

#define AU1000_UART0_PHYS_ADDR   0x11100000 /* 01234 */

Definition at line 754 of file au1000.h.

#define AU1000_UART1_PHYS_ADDR   0x11200000 /* 0234 */

Definition at line 756 of file au1000.h.

#define AU1000_UART2_PHYS_ADDR   0x11300000 /* 0 */

Definition at line 757 of file au1000.h.

#define AU1000_UART3_PHYS_ADDR   0x11400000 /* 0123 */

Definition at line 758 of file au1000.h.

#define AU1000_USB_OHCI_PHYS_ADDR   0x10100000 /* 012 */

Definition at line 729 of file au1000.h.

#define AU1000_USB_UDC_PHYS_ADDR   0x10200000 /* 0123 */

Definition at line 730 of file au1000.h.

#define AU1100_LCD_PHYS_ADDR   0x15000000 /* 2 */

Definition at line 793 of file au1000.h.

#define AU1100_SD0_PHYS_ADDR   0x10600000 /* 245 */

Definition at line 739 of file au1000.h.

#define AU1100_SD1_PHYS_ADDR   0x10680000 /* 24 */

Definition at line 742 of file au1000.h.

#define AU1200_AES_PHYS_ADDR   0x10300000 /* 45 */

Definition at line 733 of file au1000.h.

#define AU1200_CIM_PHYS_ADDR   0x14004000 /* 45 */

Definition at line 774 of file au1000.h.

#define AU1200_LCD_PHYS_ADDR   0x15000000 /* 45 */

Definition at line 794 of file au1000.h.

#define AU1200_MAEBE_PHYS_ADDR   0x14010000 /* 4 */

Definition at line 777 of file au1000.h.

#define AU1200_MAEFE_PHYS_ADDR   0x14012000 /* 4 */

Definition at line 778 of file au1000.h.

#define AU1200_SWCNT_PHYS_ADDR   0x1110010C /* 4 */

Definition at line 755 of file au1000.h.

#define AU1200_USB_CTL_PHYS_ADDR   0x14020000 /* 4 */

Definition at line 782 of file au1000.h.

#define AU1200_USB_EHCI_PHYS_ADDR   0x14020200 /* 4 */

Definition at line 785 of file au1000.h.

#define AU1200_USB_OHCI_PHYS_ADDR   0x14020100 /* 4 */

Definition at line 784 of file au1000.h.

#define AU1200_USB_OTG_PHYS_ADDR   0x14020020 /* 4 */

Definition at line 783 of file au1000.h.

#define AU1200_USB_UDC_PHYS_ADDR   0x14022000 /* 4 */

Definition at line 786 of file au1000.h.

#define AU1300_AES_INT   (AU1300_FIRST_INT + 95)

Definition at line 711 of file au1000.h.

#define AU1300_BSA_INT   (AU1300_FIRST_INT + 92)

Definition at line 708 of file au1000.h.

#define AU1300_CIM_INT   (AU1300_FIRST_INT + 96)

Definition at line 712 of file au1000.h.

#define AU1300_DDMA_INT   (AU1300_FIRST_INT + 75)

Definition at line 691 of file au1000.h.

#define AU1300_FIRST_INT   (ALCHEMY_GPIC_INT_BASE)

Definition at line 680 of file au1000.h.

#define AU1300_GPIC_DEVCLR   0x0090

Definition at line 818 of file au1000.h.

#define AU1300_GPIC_DEVSEL   0x0080

Definition at line 817 of file au1000.h.

#define AU1300_GPIC_DMASEL   0x0060

Definition at line 816 of file au1000.h.

#define AU1300_GPIC_IDIS   0x0050 /* int_maskclr in manual */

Definition at line 815 of file au1000.h.

#define AU1300_GPIC_IEN   0x0040 /* int_mask in manual */

Definition at line 814 of file au1000.h.

#define AU1300_GPIC_IPEND   0x0020

Definition at line 812 of file au1000.h.

#define AU1300_GPIC_PHYS_ADDR   0x10200000 /* 5 */

Definition at line 731 of file au1000.h.

#define AU1300_GPIC_PINCFG   0x1000

Definition at line 821 of file au1000.h.

#define AU1300_GPIC_PINVAL   0x0000

Definition at line 810 of file au1000.h.

#define AU1300_GPIC_PINVALCLR   0x0010

Definition at line 811 of file au1000.h.

#define AU1300_GPIC_PRIENC   0x0030

Definition at line 813 of file au1000.h.

#define AU1300_GPIC_RSTVAL   0x00a0

Definition at line 819 of file au1000.h.

#define AU1300_GPU_INT   (AU1300_FIRST_INT + 78)

Definition at line 694 of file au1000.h.

#define AU1300_GPU_PHYS_ADDR   0x10500000 /* 5 */

Definition at line 735 of file au1000.h.

#define AU1300_ITE_INT   (AU1300_FIRST_INT + 94)

Definition at line 710 of file au1000.h.

#define AU1300_LCD_INT   (AU1300_FIRST_INT + 91)

Definition at line 707 of file au1000.h.

#define AU1300_MAEBSA_PHYS_ADDR   0x14030000 /* 5 */

Definition at line 792 of file au1000.h.

#define AU1300_MAEITE_PHYS_ADDR   0x14010000 /* 5 */

Definition at line 779 of file au1000.h.

#define AU1300_MAEMPE_PHYS_ADDR   0x14014000 /* 5 */

Definition at line 780 of file au1000.h.

#define AU1300_MMU_INT   (AU1300_FIRST_INT + 76)

Definition at line 692 of file au1000.h.

#define AU1300_MPE_INT   (AU1300_FIRST_INT + 93)

Definition at line 709 of file au1000.h.

#define AU1300_MPU_INT   (AU1300_FIRST_INT + 77)

Definition at line 693 of file au1000.h.

#define AU1300_NAND_INT   (AU1300_FIRST_INT + 62)

Definition at line 690 of file au1000.h.

#define AU1300_OTP_PHYS_ADDR   0x10002000 /* 5 */

Definition at line 723 of file au1000.h.

#define AU1300_PSC0_INT   (AU1300_FIRST_INT + 48)

Definition at line 686 of file au1000.h.

#define AU1300_PSC0_PHYS_ADDR   0x10A00000 /* 5 */

Definition at line 746 of file au1000.h.

#define AU1300_PSC1_INT   (AU1300_FIRST_INT + 52)

Definition at line 687 of file au1000.h.

#define AU1300_PSC1_PHYS_ADDR   0x10A01000 /* 5 */

Definition at line 747 of file au1000.h.

#define AU1300_PSC2_INT   (AU1300_FIRST_INT + 56)

Definition at line 688 of file au1000.h.

#define AU1300_PSC2_PHYS_ADDR   0x10A02000 /* 5 */

Definition at line 748 of file au1000.h.

#define AU1300_PSC3_INT   (AU1300_FIRST_INT + 60)

Definition at line 689 of file au1000.h.

#define AU1300_PSC3_PHYS_ADDR   0x10A03000 /* 5 */

Definition at line 749 of file au1000.h.

#define AU1300_ROM_PHYS_ADDR   0x10000000 /* 5 */

Definition at line 722 of file au1000.h.

#define AU1300_RTC_INT   (AU1300_FIRST_INT + 84)

Definition at line 700 of file au1000.h.

#define AU1300_RTC_MATCH0_INT   (AU1300_FIRST_INT + 85)

Definition at line 701 of file au1000.h.

#define AU1300_RTC_MATCH1_INT   (AU1300_FIRST_INT + 86)

Definition at line 702 of file au1000.h.

#define AU1300_RTC_MATCH2_INT   (AU1300_FIRST_INT + 87)

Definition at line 703 of file au1000.h.

#define AU1300_SD0_INT   (AU1300_FIRST_INT + 89)

Definition at line 705 of file au1000.h.

#define AU1300_SD1_INT   (AU1300_FIRST_INT + 32)

Definition at line 684 of file au1000.h.

#define AU1300_SD1_PHYS_ADDR   0x10601000 /* 5 */

Definition at line 740 of file au1000.h.

#define AU1300_SD2_INT   (AU1300_FIRST_INT + 38)

Definition at line 685 of file au1000.h.

#define AU1300_SD2_PHYS_ADDR   0x10602000 /* 5 */

Definition at line 741 of file au1000.h.

#define AU1300_SYS_PHYS_ADDR   0x10900000 /* 5 */

Definition at line 743 of file au1000.h.

#define AU1300_TOY_INT   (AU1300_FIRST_INT + 80)

Definition at line 696 of file au1000.h.

#define AU1300_TOY_MATCH0_INT   (AU1300_FIRST_INT + 81)

Definition at line 697 of file au1000.h.

#define AU1300_TOY_MATCH1_INT   (AU1300_FIRST_INT + 82)

Definition at line 698 of file au1000.h.

#define AU1300_TOY_MATCH2_INT   (AU1300_FIRST_INT + 83)

Definition at line 699 of file au1000.h.

#define AU1300_UART0_INT   (AU1300_FIRST_INT + 88)

Definition at line 704 of file au1000.h.

#define AU1300_UART0_PHYS_ADDR   0x10100000 /* 5 */

Definition at line 725 of file au1000.h.

#define AU1300_UART1_INT   (AU1300_FIRST_INT + 17)

Definition at line 681 of file au1000.h.

#define AU1300_UART1_PHYS_ADDR   0x10101000 /* 5 */

Definition at line 726 of file au1000.h.

#define AU1300_UART2_INT   (AU1300_FIRST_INT + 25)

Definition at line 682 of file au1000.h.

#define AU1300_UART2_PHYS_ADDR   0x10102000 /* 5 */

Definition at line 727 of file au1000.h.

#define AU1300_UART3_INT   (AU1300_FIRST_INT + 27)

Definition at line 683 of file au1000.h.

#define AU1300_UART3_PHYS_ADDR   0x10103000 /* 5 */

Definition at line 728 of file au1000.h.

#define AU1300_UDMA_INT   (AU1300_FIRST_INT + 79)

Definition at line 695 of file au1000.h.

#define AU1300_UDMA_PHYS_ADDR   0x14001800 /* 5 */

Definition at line 768 of file au1000.h.

#define AU1300_USB_CTL_PHYS_ADDR   0x14021000 /* 5 */

Definition at line 790 of file au1000.h.

#define AU1300_USB_EHCI_PHYS_ADDR   0x14020000 /* 5 */

Definition at line 787 of file au1000.h.

#define AU1300_USB_INT   (AU1300_FIRST_INT + 90)

Definition at line 706 of file au1000.h.

#define AU1300_USB_OHCI0_PHYS_ADDR   0x14020400 /* 5 */

Definition at line 788 of file au1000.h.

#define AU1300_USB_OHCI1_PHYS_ADDR   0x14020800 /* 5 */

Definition at line 789 of file au1000.h.

#define AU1300_USB_OTG_PHYS_ADDR   0x14022000 /* 5 */

Definition at line 791 of file au1000.h.

#define AU1300_VSS_PHYS_ADDR   0x10003000 /* 5 */

Definition at line 724 of file au1000.h.

#define AU1500_GPIO2_PHYS_ADDR   0x11700000 /* 1234 */

Definition at line 761 of file au1000.h.

#define AU1500_MAC0_PHYS_ADDR   0x11500000 /* 1 */

Definition at line 751 of file au1000.h.

#define AU1500_MAC1_PHYS_ADDR   0x11510000 /* 1 */

Definition at line 752 of file au1000.h.

#define AU1500_MACEN_PHYS_ADDR   0x11520000 /* 1 */

Definition at line 753 of file au1000.h.

#define AU1500_PCI_CONFIG0_PHYS_ADDR   0x600000000ULL /* 13 */

Definition at line 797 of file au1000.h.

#define AU1500_PCI_CONFIG1_PHYS_ADDR   0x680000000ULL /* 13 */

Definition at line 798 of file au1000.h.

#define AU1500_PCI_IO_PHYS_ADDR   0x500000000ULL /* 13 */

Definition at line 796 of file au1000.h.

#define AU1500_PCI_MEM_PHYS_ADDR   0x400000000ULL /* 13 */

Definition at line 795 of file au1000.h.

#define AU1500_PCI_PHYS_ADDR   0x14005000 /* 13 */

Definition at line 775 of file au1000.h.

#define AU1550_DBDMA_CONF_PHYS_ADDR   0x14003000 /* 345 */

Definition at line 771 of file au1000.h.

#define AU1550_DBDMA_PHYS_ADDR   0x14002000 /* 345 */

Definition at line 770 of file au1000.h.

#define AU1550_MEM_SDADDR0   0x0820

Definition at line 922 of file au1000.h.

#define AU1550_MEM_SDADDR1   0x0828

Definition at line 923 of file au1000.h.

#define AU1550_MEM_SDADDR2   0x0830

Definition at line 924 of file au1000.h.

#define AU1550_MEM_SDAUTOREF   0x08C8

Definition at line 936 of file au1000.h.

#define AU1550_MEM_SDCONFIGA   0x0840

Definition at line 925 of file au1000.h.

#define AU1550_MEM_SDCONFIGB   0x0848

Definition at line 926 of file au1000.h.

#define AU1550_MEM_SDERRADDR   0x0858

Definition at line 928 of file au1000.h.

#define AU1550_MEM_SDMODE0   0x0800

Definition at line 919 of file au1000.h.

#define AU1550_MEM_SDMODE1   0x0808

Definition at line 920 of file au1000.h.

#define AU1550_MEM_SDMODE2   0x0810

Definition at line 921 of file au1000.h.

#define AU1550_MEM_SDPRECMD   0x08C0

Definition at line 935 of file au1000.h.

#define AU1550_MEM_SDSLEEP   MEM_SDSREF

Definition at line 938 of file au1000.h.

#define AU1550_MEM_SDSREF   0x08D0

Definition at line 937 of file au1000.h.

#define AU1550_MEM_SDSTAT   0x0850

Definition at line 927 of file au1000.h.

#define AU1550_MEM_SDSTRIDE0   0x0860

Definition at line 929 of file au1000.h.

#define AU1550_MEM_SDSTRIDE1   0x0868

Definition at line 930 of file au1000.h.

#define AU1550_MEM_SDSTRIDE2   0x0870

Definition at line 931 of file au1000.h.

#define AU1550_MEM_SDWRMD0   0x0880

Definition at line 932 of file au1000.h.

#define AU1550_MEM_SDWRMD1   0x0888

Definition at line 933 of file au1000.h.

#define AU1550_MEM_SDWRMD2   0x0890

Definition at line 934 of file au1000.h.

#define AU1550_PE_PHYS_ADDR   0x14008000 /* 3 */

Definition at line 776 of file au1000.h.

#define AU1550_PSC0_PHYS_ADDR   0x11A00000 /* 34 */

Definition at line 764 of file au1000.h.

#define AU1550_PSC1_PHYS_ADDR   0x11B00000 /* 34 */

Definition at line 765 of file au1000.h.

#define AU1550_PSC2_PHYS_ADDR   0x10A00000 /* 3 */

Definition at line 744 of file au1000.h.

#define AU1550_PSC3_PHYS_ADDR   0x10B00000 /* 3 */

Definition at line 745 of file au1000.h.

#define AU1550_USB_OHCI_PHYS_ADDR   0x14020000 /* 3 */

Definition at line 781 of file au1000.h.

#define GPIC_CFG_IC_EDGE_BOTH   (7 << 4)

Definition at line 846 of file au1000.h.

#define GPIC_CFG_IC_EDGE_FALL   (5 << 4)

Definition at line 844 of file au1000.h.

#define GPIC_CFG_IC_EDGE_RISE   (6 << 4)

Definition at line 845 of file au1000.h.

#define GPIC_CFG_IC_LEVEL_HIGH   (2 << 4)

Definition at line 843 of file au1000.h.

#define GPIC_CFG_IC_LEVEL_LOW   (1 << 4)

Definition at line 842 of file au1000.h.

#define GPIC_CFG_IC_MASK   (7 << 4)

Definition at line 847 of file au1000.h.

#define GPIC_CFG_IC_OFF   (0 << 4)

Definition at line 841 of file au1000.h.

#define GPIC_CFG_IDLEWAKE   (1 << 7)

Definition at line 850 of file au1000.h.

#define GPIC_CFG_IL_MASK   (3 << 2)

Definition at line 838 of file au1000.h.

#define GPIC_CFG_IL_SET (   x)    (((x) & 3) << 2)

Definition at line 837 of file au1000.h.

#define GPIC_CFG_PC_DEV   1

Definition at line 831 of file au1000.h.

#define GPIC_CFG_PC_GPIN   0

Definition at line 830 of file au1000.h.

#define GPIC_CFG_PC_GPOHIGH   3

Definition at line 833 of file au1000.h.

#define GPIC_CFG_PC_GPOLOW   2

Definition at line 832 of file au1000.h.

#define GPIC_CFG_PC_MASK   3

Definition at line 834 of file au1000.h.

#define GPIC_GPIO_BANKOFF (   gpio)    (((gpio) >> 5) * 4)

Definition at line 826 of file au1000.h.

#define GPIC_GPIO_TO_BIT (   gpio)    (1 << ((gpio) & 0x1f))

Definition at line 823 of file au1000.h.

#define I2S_CONFIG   0xB1000004

Definition at line 1007 of file au1000.h.

#define I2S_CONFIG_FM_BIT   7

Definition at line 1021 of file au1000.h.

#define I2S_CONFIG_FM_I2S   (0x0 << I2S_CONFIG_FM_BIT)

Definition at line 1023 of file au1000.h.

#define I2S_CONFIG_FM_LJ   (0x1 << I2S_CONFIG_FM_BIT)

Definition at line 1024 of file au1000.h.

#define I2S_CONFIG_FM_MASK   (0x3 << I2S_CONFIG_FM_BIT)

Definition at line 1022 of file au1000.h.

#define I2S_CONFIG_FM_RJ   (0x2 << I2S_CONFIG_FM_BIT)

Definition at line 1025 of file au1000.h.

#define I2S_CONFIG_IC   (1 << 9)

Definition at line 1020 of file au1000.h.

#define I2S_CONFIG_LB   (1 << 10)

Definition at line 1019 of file au1000.h.

#define I2S_CONFIG_PD   (1 << 11)

Definition at line 1018 of file au1000.h.

#define I2S_CONFIG_RE   (1 << 17)

Definition at line 1016 of file au1000.h.

#define I2S_CONFIG_RF   (1 << 16)

Definition at line 1017 of file au1000.h.

#define I2S_CONFIG_RN   (1 << 5)

Definition at line 1027 of file au1000.h.

#define I2S_CONFIG_RO   (1 << 22)

Definition at line 1011 of file au1000.h.

#define I2S_CONFIG_RR   (1 << 18)

Definition at line 1015 of file au1000.h.

#define I2S_CONFIG_RU   (1 << 23)

Definition at line 1010 of file au1000.h.

#define I2S_CONFIG_SZ_BIT   0

Definition at line 1028 of file au1000.h.

#define I2S_CONFIG_SZ_MASK   (0x1F << I2S_CONFIG_SZ_BIT)

Definition at line 1029 of file au1000.h.

#define I2S_CONFIG_TE   (1 << 20)

Definition at line 1013 of file au1000.h.

#define I2S_CONFIG_TF   (1 << 19)

Definition at line 1014 of file au1000.h.

#define I2S_CONFIG_TN   (1 << 6)

Definition at line 1026 of file au1000.h.

#define I2S_CONFIG_TR   (1 << 21)

Definition at line 1012 of file au1000.h.

#define I2S_CONFIG_XO   (1 << 24)

Definition at line 1009 of file au1000.h.

#define I2S_CONFIG_XU   (1 << 25)

Definition at line 1008 of file au1000.h.

#define I2S_CONTROL   0xB1000008

Definition at line 1031 of file au1000.h.

#define I2S_CONTROL_CE   (1 << 0)

Definition at line 1033 of file au1000.h.

#define I2S_CONTROL_D   (1 << 1)

Definition at line 1032 of file au1000.h.

#define I2S_DATA   0xB1000000

Definition at line 1005 of file au1000.h.

#define I2S_DATA_MASK   0xffffff

Definition at line 1006 of file au1000.h.

#define IOMEM_RESOURCE_END   0xfffffffffULL

Definition at line 1497 of file au1000.h.

#define IOMEM_RESOURCE_START   0x10000000

Definition at line 1496 of file au1000.h.

#define IOPORT_RESOURCE_END   0xffffffff

Definition at line 1495 of file au1000.h.

#define IOPORT_RESOURCE_START   0x10000000

Definition at line 1494 of file au1000.h.

#define MAC0_RX_DMA_ADDR   0xB4004100

Definition at line 1123 of file au1000.h.

#define MAC0_TX_DMA_ADDR   0xB4004000

Definition at line 1092 of file au1000.h.

#define MAC1_RX_DMA_ADDR   0xB4004300

Definition at line 1124 of file au1000.h.

#define MAC1_TX_DMA_ADDR   0xB4004200

Definition at line 1093 of file au1000.h.

#define MAC_ADDRESS_HIGH   0x4

Definition at line 1061 of file au1000.h.

#define MAC_ADDRESS_LOW   0x8

Definition at line 1062 of file au1000.h.

#define MAC_AUTO_PAD   (1 << 8)

Definition at line 1044 of file au1000.h.

#define MAC_BIG_ENDIAN   (1 << 30)

Definition at line 1059 of file au1000.h.

#define MAC_CONTROL   0x0

Definition at line 1039 of file au1000.h.

#define MAC_DEF_CHECK   (1 << 5)

Definition at line 1042 of file au1000.h.

#define MAC_DISABLE_BCAST   (1 << 11)

Definition at line 1046 of file au1000.h.

#define MAC_DISABLE_RETRY   (1 << 10)

Definition at line 1045 of file au1000.h.

#define MAC_DISABLE_RX_OWN   (1 << 23)

Definition at line 1058 of file au1000.h.

#define MAC_DMA_RESET   (1 << 6)

Definition at line 1088 of file au1000.h.

#define MAC_EN_CACHEABLE   (1 << 3)

Definition at line 1085 of file au1000.h.

#define MAC_EN_CLOCK_ENABLE   (1 << 0)

Definition at line 1082 of file au1000.h.

#define MAC_EN_RESET0   (1 << 1)

Definition at line 1083 of file au1000.h.

#define MAC_EN_RESET1   (1 << 4)

Definition at line 1086 of file au1000.h.

#define MAC_EN_RESET2   (1 << 5)

Definition at line 1087 of file au1000.h.

#define MAC_EN_TOSS   (0 << 2)

Definition at line 1084 of file au1000.h.

#define MAC_EXT_LOOPBACK   (1 << 22)

Definition at line 1057 of file au1000.h.

#define MAC_FLOW_CNTRL   0x1C

Definition at line 1072 of file au1000.h.

#define MAC_FLOW_CNTRL_BUSY   (1 << 0)

Definition at line 1073 of file au1000.h.

#define MAC_FLOW_CNTRL_ENABLE   (1 << 1)

Definition at line 1074 of file au1000.h.

#define MAC_FULL_DUPLEX   (1 << 20)

Definition at line 1054 of file au1000.h.

#define MAC_HASH_MODE   (1 << 13)

Definition at line 1048 of file au1000.h.

#define MAC_HASH_ONLY   (1 << 15)

Definition at line 1049 of file au1000.h.

#define MAC_INT_LOOPBACK   (1 << 21)

Definition at line 1056 of file au1000.h.

#define MAC_INVERSE_FILTER   (1 << 17)

Definition at line 1051 of file au1000.h.

#define MAC_LATE_COL   (1 << 12)

Definition at line 1047 of file au1000.h.

#define MAC_MCAST_HIGH   0xC

Definition at line 1063 of file au1000.h.

#define MAC_MCAST_LOW   0x10

Definition at line 1064 of file au1000.h.

#define MAC_MII_BUSY   (1 << 0)

Definition at line 1066 of file au1000.h.

#define MAC_MII_CNTRL   0x14

Definition at line 1065 of file au1000.h.

#define MAC_MII_DATA   0x18

Definition at line 1071 of file au1000.h.

#define MAC_MII_READ   0

Definition at line 1067 of file au1000.h.

#define MAC_MII_WRITE   (1 << 1)

Definition at line 1068 of file au1000.h.

#define MAC_NORMAL_MODE   0

Definition at line 1055 of file au1000.h.

#define MAC_PASS_ALL   (1 << 16)

Definition at line 1050 of file au1000.h.

#define MAC_PASS_ALL_MULTI   (1 << 19)

Definition at line 1053 of file au1000.h.

#define MAC_PASS_CONTROL   (1 << 2)

Definition at line 1075 of file au1000.h.

#define MAC_PROMISCUOUS   (1 << 18)

Definition at line 1052 of file au1000.h.

#define MAC_RX_ALL   (1 << 31)

Definition at line 1060 of file au1000.h.

#define MAC_RX_BUFF0_ADDR   0x4

Definition at line 1150 of file au1000.h.

#define MAC_RX_BUFF0_STATUS   0x0

Definition at line 1126 of file au1000.h.

#define MAC_RX_BUFF1_ADDR   0x14

Definition at line 1156 of file au1000.h.

#define MAC_RX_BUFF1_STATUS   0x10

Definition at line 1155 of file au1000.h.

#define MAC_RX_BUFF2_ADDR   0x24

Definition at line 1158 of file au1000.h.

#define MAC_RX_BUFF2_STATUS   0x20

Definition at line 1157 of file au1000.h.

#define MAC_RX_BUFF3_ADDR   0x34

Definition at line 1160 of file au1000.h.

#define MAC_RX_BUFF3_STATUS   0x30

Definition at line 1159 of file au1000.h.

#define MAC_RX_ENABLE   (1 << 2)

Definition at line 1040 of file au1000.h.

#define MAC_SET_BL (   X)    (((X) & 0x3) << 6)

Definition at line 1043 of file au1000.h.

#define MAC_SET_MII_SELECT_PHY (   X)    (((X) & 0x1f) << 11)

Definition at line 1070 of file au1000.h.

#define MAC_SET_MII_SELECT_REG (   X)    (((X) & 0x1f) << 6)

Definition at line 1069 of file au1000.h.

#define MAC_SET_PAUSE (   X)    (((X) & 0xffff) << 16)

Definition at line 1076 of file au1000.h.

#define MAC_TX_BUFF0_ADDR   0x4

Definition at line 1108 of file au1000.h.

#define MAC_TX_BUFF0_LEN   0x8

Definition at line 1112 of file au1000.h.

#define MAC_TX_BUFF0_STATUS   0x0

Definition at line 1095 of file au1000.h.

#define MAC_TX_BUFF1_ADDR   0x14

Definition at line 1114 of file au1000.h.

#define MAC_TX_BUFF1_LEN   0x18

Definition at line 1115 of file au1000.h.

#define MAC_TX_BUFF1_STATUS   0x10

Definition at line 1113 of file au1000.h.

#define MAC_TX_BUFF2_ADDR   0x24

Definition at line 1117 of file au1000.h.

#define MAC_TX_BUFF2_LEN   0x28

Definition at line 1118 of file au1000.h.

#define MAC_TX_BUFF2_STATUS   0x20

Definition at line 1116 of file au1000.h.

#define MAC_TX_BUFF3_ADDR   0x34

Definition at line 1120 of file au1000.h.

#define MAC_TX_BUFF3_LEN   0x38

Definition at line 1121 of file au1000.h.

#define MAC_TX_BUFF3_STATUS   0x30

Definition at line 1119 of file au1000.h.

#define MAC_TX_ENABLE   (1 << 3)

Definition at line 1041 of file au1000.h.

#define MAC_VLAN1_TAG   0x20

Definition at line 1077 of file au1000.h.

#define MAC_VLAN2_TAG   0x24

Definition at line 1078 of file au1000.h.

#define MEM_SDADDR_CSBA   (0x03FF << 10)

Definition at line 904 of file au1000.h.

#define MEM_SDADDR_CSBA_N (   N)    ((N) & (0x03FF << 22) >> 12)

Definition at line 906 of file au1000.h.

#define MEM_SDADDR_CSMASK   (0x03FF << 0)

Definition at line 905 of file au1000.h.

#define MEM_SDADDR_CSMASK_N (   N)    ((N)&(0x03FF << 22) >> 22)

Definition at line 907 of file au1000.h.

#define MEM_SDADDR_E   (1 << 20)

Definition at line 903 of file au1000.h.

#define MEM_SDMODE_BS   (1 << 20)

Definition at line 873 of file au1000.h.

#define MEM_SDMODE_BS_2Bank   (0 << 20)

Definition at line 883 of file au1000.h.

#define MEM_SDMODE_BS_4Bank   (1 << 20)

Definition at line 884 of file au1000.h.

#define MEM_SDMODE_CS   (7 << 15)

Definition at line 875 of file au1000.h.

#define MEM_SDMODE_CS_10Col   (3 << 15)

Definition at line 892 of file au1000.h.

#define MEM_SDMODE_CS_11Col   (4 << 15)

Definition at line 893 of file au1000.h.

#define MEM_SDMODE_CS_7Col   (0 << 15)

Definition at line 889 of file au1000.h.

#define MEM_SDMODE_CS_8Col   (1 << 15)

Definition at line 890 of file au1000.h.

#define MEM_SDMODE_CS_9Col   (2 << 15)

Definition at line 891 of file au1000.h.

#define MEM_SDMODE_CS_N (   N)    ((N) << 15)

Definition at line 894 of file au1000.h.

#define MEM_SDMODE_F   (1 << 22)

Definition at line 871 of file au1000.h.

#define MEM_SDMODE_RS   (3 << 18)

Definition at line 874 of file au1000.h.

#define MEM_SDMODE_RS_11Row   (0 << 18)

Definition at line 885 of file au1000.h.

#define MEM_SDMODE_RS_12Row   (1 << 18)

Definition at line 886 of file au1000.h.

#define MEM_SDMODE_RS_13Row   (2 << 18)

Definition at line 887 of file au1000.h.

#define MEM_SDMODE_RS_N (   N)    ((N) << 18)

Definition at line 888 of file au1000.h.

#define MEM_SDMODE_SR   (1 << 21)

Definition at line 872 of file au1000.h.

#define MEM_SDMODE_TCL   (7 << 0)

Definition at line 881 of file au1000.h.

#define MEM_SDMODE_TCL_N (   N)    ((N) << 0)

Definition at line 900 of file au1000.h.

#define MEM_SDMODE_TMRD   (3 << 9)

Definition at line 877 of file au1000.h.

#define MEM_SDMODE_TMRD_N (   N)    ((N) << 9)

Definition at line 896 of file au1000.h.

#define MEM_SDMODE_TRAS   (15 << 11)

Definition at line 876 of file au1000.h.

#define MEM_SDMODE_TRAS_N (   N)    ((N) << 11)

Definition at line 895 of file au1000.h.

#define MEM_SDMODE_TRCD   (3 << 3)

Definition at line 880 of file au1000.h.

#define MEM_SDMODE_TRCD_N (   N)    ((N) << 3)

Definition at line 899 of file au1000.h.

#define MEM_SDMODE_TRP   (3 << 5)

Definition at line 879 of file au1000.h.

#define MEM_SDMODE_TRP_N (   N)    ((N) << 5)

Definition at line 898 of file au1000.h.

#define MEM_SDMODE_TWR   (3 << 7)

Definition at line 878 of file au1000.h.

#define MEM_SDMODE_TWR_N (   N)    ((N) << 7)

Definition at line 897 of file au1000.h.

#define MEM_SDREFCFG_E   (1 << 25)

Definition at line 912 of file au1000.h.

#define MEM_SDREFCFG_RE   (0x1ffffff << 0)

Definition at line 913 of file au1000.h.

#define MEM_SDREFCFG_REF_N (   N)    (N)

Definition at line 916 of file au1000.h.

#define MEM_SDREFCFG_TRC   (15 << 28)

Definition at line 910 of file au1000.h.

#define MEM_SDREFCFG_TRC_N (   N)    ((N) << MEM_SDREFCFG_TRC)

Definition at line 914 of file au1000.h.

#define MEM_SDREFCFG_TRPM   (3 << 26)

Definition at line 911 of file au1000.h.

#define MEM_SDREFCFG_TRPM_N (   N)    ((N) << MEM_SDREFCFG_TRPM)

Definition at line 915 of file au1000.h.

#define MEM_STADDR0   0xB4001008

Definition at line 943 of file au1000.h.

#define MEM_STADDR1   0xB4001018

Definition at line 947 of file au1000.h.

#define MEM_STADDR2   0xB4001028

Definition at line 951 of file au1000.h.

#define MEM_STADDR3   0xB4001038

Definition at line 955 of file au1000.h.

#define MEM_STCFG0   0xB4001000

Definition at line 941 of file au1000.h.

#define MEM_STCFG1   0xB4001010

Definition at line 945 of file au1000.h.

#define MEM_STCFG2   0xB4001020

Definition at line 949 of file au1000.h.

#define MEM_STCFG3   0xB4001030

Definition at line 953 of file au1000.h.

#define MEM_STNAND_ADDR   0x4

Definition at line 961 of file au1000.h.

#define MEM_STNAND_CMD   0x0

Definition at line 960 of file au1000.h.

#define MEM_STNAND_DATA   0x20

Definition at line 962 of file au1000.h.

#define MEM_STNDCTL   0xB4001100

Definition at line 957 of file au1000.h.

#define MEM_STSTAT   0xB4001104

Definition at line 958 of file au1000.h.

#define MEM_STTIME0   0xB4001004

Definition at line 942 of file au1000.h.

#define MEM_STTIME1   0xB4001014

Definition at line 946 of file au1000.h.

#define MEM_STTIME2   0xB4001024

Definition at line 950 of file au1000.h.

#define MEM_STTIME3   0xB4001034

Definition at line 954 of file au1000.h.

#define PCI_B2BBASE0_VID_B0 (   x)    (((x) & 0xffff) << 16)

Definition at line 1550 of file au1000.h.

#define PCI_B2BBASE0_VID_SV (   x)    ((x) & 0xffff)

Definition at line 1551 of file au1000.h.

#define PCI_B2BBASE1_SID_B1 (   x)    (((x) & 0xffff) << 16)

Definition at line 1552 of file au1000.h.

#define PCI_B2BBASE1_SID_SI (   x)    ((x) & 0xffff)

Definition at line 1553 of file au1000.h.

#define PCI_B2BMASK_B2BMASK (   x)    (((x) & 0xffff) << 16)

Definition at line 1548 of file au1000.h.

#define PCI_B2BMASK_CCH (   x)    ((x) & 0xffff) /* 16 upper bits of class code */

Definition at line 1549 of file au1000.h.

#define PCI_CLASSREV_CLASS (   x)    (((x) & 0x00ffffff) << 8)

Definition at line 1563 of file au1000.h.

#define PCI_CLASSREV_REV (   x)    ((x) & 0xff)

Definition at line 1564 of file au1000.h.

#define PCI_CMEM_CMBASE (   x)    (((x) & 0x3fff) << 14)

Definition at line 1520 of file au1000.h.

#define PCI_CMEM_CMMASK (   x)    ((x) & 0x3fff)

Definition at line 1521 of file au1000.h.

#define PCI_CMEM_E   (1 << 28) /* enable cacheable memory */

Definition at line 1519 of file au1000.h.

#define PCI_CONFIG_AEN   (1 << 3) /* enable internal arbiter */

Definition at line 1544 of file au1000.h.

#define PCI_CONFIG_BM   (1 << 22) /* bad master error */

Definition at line 1527 of file au1000.h.

#define PCI_CONFIG_BME   (1 << 19) /* Byte Mask Enable for reads */

Definition at line 1529 of file au1000.h.

#define PCI_CONFIG_CH   (1 << 0) /* PCI ctl to hi-prio arbiter */

Definition at line 1547 of file au1000.h.

#define PCI_CONFIG_EF   (1 << 25) /* fatal error */

Definition at line 1524 of file au1000.h.

#define PCI_CONFIG_EM   (1 << 23) /* multiple errors */

Definition at line 1526 of file au1000.h.

#define PCI_CONFIG_EP   (1 << 24) /* parity error */

Definition at line 1525 of file au1000.h.

#define PCI_CONFIG_ERD   (1 << 27) /* pci error during R/W */

Definition at line 1522 of file au1000.h.

#define PCI_CONFIG_ET   (1 << 26) /* error in target mode */

Definition at line 1523 of file au1000.h.

#define PCI_CONFIG_IA   (1 << 15) /* INTA# enabled (target mode) */

Definition at line 1531 of file au1000.h.

#define PCI_CONFIG_IMM   (1 << 11) /* int on master abort */

Definition at line 1534 of file au1000.h.

#define PCI_CONFIG_IP   (1 << 13) /* int on PCI_PERR# */

Definition at line 1532 of file au1000.h.

#define PCI_CONFIG_IPB   (1 << 8) /* int on PERR# in bus master acc */

Definition at line 1537 of file au1000.h.

#define PCI_CONFIG_IS   (1 << 12) /* int on PCI_SERR# */

Definition at line 1533 of file au1000.h.

#define PCI_CONFIG_ITM   (1 << 10) /* int on target abort (as master) */

Definition at line 1535 of file au1000.h.

#define PCI_CONFIG_ITT   (1 << 9) /* int on target abort (as target) */

Definition at line 1536 of file au1000.h.

#define PCI_CONFIG_NC   (1 << 16) /* mark mem access non-coherent */

Definition at line 1530 of file au1000.h.

#define PCI_CONFIG_PD   (1 << 20) /* PCI Disable */

Definition at line 1528 of file au1000.h.

#define PCI_CONFIG_R1H   (1 << 1) /* REQ1# to hi-prio arbiter */

Definition at line 1546 of file au1000.h.

#define PCI_CONFIG_R2H   (1 << 2) /* REQ2# to hi-prio arbiter */

Definition at line 1545 of file au1000.h.

#define PCI_CONFIG_SIC_ALL   (3 << 6) /* swap data bytes on all accesses */

Definition at line 1541 of file au1000.h.

#define PCI_CONFIG_SIC_BA_ADR   (1 << 6) /* on byte/hw acc, invert adr bits */

Definition at line 1539 of file au1000.h.

#define PCI_CONFIG_SIC_HWA_DAT   (2 << 6) /* on halfword acc, swap data */

Definition at line 1540 of file au1000.h.

#define PCI_CONFIG_SIC_NO   (0 << 6) /* no byte mask changes */

Definition at line 1538 of file au1000.h.

#define PCI_CONFIG_SM   (1 << 4) /* swap data from PCI ctl */

Definition at line 1543 of file au1000.h.

#define PCI_CONFIG_ST   (1 << 5) /* swap data by target transactions */

Definition at line 1542 of file au1000.h.

#define PCI_ID_DID (   x)    (((x) & 0xffff) << 16)

Definition at line 1559 of file au1000.h.

#define PCI_ID_VID (   x)    ((x) & 0xffff)

Definition at line 1560 of file au1000.h.

#define PCI_MWBASEREVCCL_BASE (   x)    (((x) & 0xffff) << 16)

Definition at line 1556 of file au1000.h.

#define PCI_MWBASEREVCCL_CCL (   x)    ((x) & 0xff)

Definition at line 1558 of file au1000.h.

#define PCI_MWBASEREVCCL_REV (   x)    (((x) & 0xff) << 8)

Definition at line 1557 of file au1000.h.

#define PCI_MWMASKDEV_DEVID (   x)    ((x) & 0xffff)

Definition at line 1555 of file au1000.h.

#define PCI_MWMASKDEV_MWMASK (   x)    (((x) & 0xffff) << 16)

Definition at line 1554 of file au1000.h.

#define PCI_PARAM_BIST (   x)    (((x) & 0xff) << 24)

Definition at line 1565 of file au1000.h.

#define PCI_PARAM_CLS (   x)    ((x) & 0xff)

Definition at line 1568 of file au1000.h.

#define PCI_PARAM_HT (   x)    (((x) & 0xff) << 16)

Definition at line 1566 of file au1000.h.

#define PCI_PARAM_LT (   x)    (((x) & 0xff) << 8)

Definition at line 1567 of file au1000.h.

#define PCI_REG_B2BBASE0_VID   0x000C

Definition at line 1505 of file au1000.h.

#define PCI_REG_B2BBASE1_SID   0x0010

Definition at line 1506 of file au1000.h.

#define PCI_REG_B2BMASK_CCH   0x0008

Definition at line 1504 of file au1000.h.

#define PCI_REG_CLASSREV   0x0108

Definition at line 1513 of file au1000.h.

#define PCI_REG_CMEM   0x0000

Definition at line 1502 of file au1000.h.

#define PCI_REG_CONFIG   0x0004

Definition at line 1503 of file au1000.h.

#define PCI_REG_ERR_ADDR   0x001C

Definition at line 1509 of file au1000.h.

#define PCI_REG_ID   0x0100

Definition at line 1511 of file au1000.h.

#define PCI_REG_MBAR   0x0110

Definition at line 1515 of file au1000.h.

#define PCI_REG_MWBASE_REV_CCL   0x0018

Definition at line 1508 of file au1000.h.

#define PCI_REG_MWMASK_DEV   0x0014

Definition at line 1507 of file au1000.h.

#define PCI_REG_PARAM   0x010C

Definition at line 1514 of file au1000.h.

#define PCI_REG_SPEC_INTACK   0x0020

Definition at line 1510 of file au1000.h.

#define PCI_REG_STATCMD   0x0104

Definition at line 1512 of file au1000.h.

#define PCI_REG_TIMEOUT   0x0140

Definition at line 1516 of file au1000.h.

#define PCI_STATCMD_CMD (   x)    ((x) & 0xffff)

Definition at line 1562 of file au1000.h.

#define PCI_STATCMD_STATUS (   x)    (((x) & 0xffff) << 16)

Definition at line 1561 of file au1000.h.

#define PCI_TIMEOUT_RETRIES (   x)    (((x) & 0xff) << 8) /* max retries */

Definition at line 1569 of file au1000.h.

#define PCI_TIMEOUT_TO (   x)    ((x) & 0xff) /* target ready timeout */

Definition at line 1570 of file au1000.h.

#define RX_BCAST_FRAME   (1 << 28)

Definition at line 1142 of file au1000.h.

#define RX_CNTRL_FRAME   (1 << 25)

Definition at line 1139 of file au1000.h.

#define RX_COLL   (1 << 17)

Definition at line 1131 of file au1000.h.

#define RX_CRC_ERROR   (1 << 21)

Definition at line 1135 of file au1000.h.

#define RX_DMA_ENABLE   (1 << 0)

Definition at line 1151 of file au1000.h.

#define RX_DRIBBLING   (1 << 20)

Definition at line 1134 of file au1000.h.

#define RX_ERROR
Value:
(RX_WDOG_TIMER | RX_RUNT | RX_OVERLEN | \
RX_COLL | RX_MII_ERROR | RX_CRC_ERROR | \
RX_LEN_ERROR | RX_U_CNTRL_FRAME | RX_MISSED_FRAME)

Definition at line 1147 of file au1000.h.

#define RX_ETHER   (1 << 18)

Definition at line 1132 of file au1000.h.

#define RX_FILTER_FAIL   (1 << 29)

Definition at line 1143 of file au1000.h.

#define RX_FRAME_LEN_MASK   0x3fff

Definition at line 1127 of file au1000.h.

#define RX_GET_DMA_BUFFER (   X)    (((X) >> 2) & 0x3)

Definition at line 1153 of file au1000.h.

#define RX_LEN_ERROR   (1 << 24)

Definition at line 1138 of file au1000.h.

#define RX_MCAST_FRAME   (1 << 27)

Definition at line 1141 of file au1000.h.

#define RX_MII_ERROR   (1 << 19)

Definition at line 1133 of file au1000.h.

#define RX_MISSED_FRAME   (1 << 31)

Definition at line 1145 of file au1000.h.

#define RX_OVERLEN   (1 << 16)

Definition at line 1130 of file au1000.h.

#define RX_PACKET_FILTER   (1 << 30)

Definition at line 1144 of file au1000.h.

#define RX_RUNT   (1 << 15)

Definition at line 1129 of file au1000.h.

#define RX_SET_BUFF_ADDR (   X)    ((X) & 0xffffffc0)

Definition at line 1154 of file au1000.h.

#define RX_T_DONE   (1 << 1)

Definition at line 1152 of file au1000.h.

#define RX_U_CNTRL_FRAME   (1 << 26)

Definition at line 1140 of file au1000.h.

#define RX_VLAN1   (1 << 22)

Definition at line 1136 of file au1000.h.

#define RX_VLAN2   (1 << 23)

Definition at line 1137 of file au1000.h.

#define RX_WDOG_TIMER   (1 << 14)

Definition at line 1128 of file au1000.h.

#define SSI0_ADATA   0xB1600024

Definition at line 1204 of file au1000.h.

#define SSI0_CLKDIV   0xB1600028

Definition at line 1210 of file au1000.h.

#define SSI0_CONFIG   0xB1600020

Definition at line 1189 of file au1000.h.

#define SSI0_CONTROL   0xB1600100

Definition at line 1211 of file au1000.h.

#define SSI0_INT   0xB1600004

Definition at line 1181 of file au1000.h.

#define SSI0_INT_ENABLE   0xB1600008

Definition at line 1185 of file au1000.h.

#define SSI0_STATUS   0xB1600000

Definition at line 1175 of file au1000.h.

#define SSI1_ADATA   0xB1680024

Definition at line 1220 of file au1000.h.

#define SSI1_CLKDIV   0xB1680028

Definition at line 1221 of file au1000.h.

#define SSI1_CONFIG   0xB1680020

Definition at line 1219 of file au1000.h.

#define SSI1_ENABLE   0xB1680100

Definition at line 1222 of file au1000.h.

#define SSI1_INT   0xB1680004

Definition at line 1217 of file au1000.h.

#define SSI1_INT_ENABLE   0xB1680008

Definition at line 1218 of file au1000.h.

#define SSI1_STATUS   0xB1680000

Definition at line 1216 of file au1000.h.

#define SSI_AD_ADDR_BIT   16

Definition at line 1206 of file au1000.h.

#define SSI_AD_ADDR_MASK   (0xff << 16)

Definition at line 1207 of file au1000.h.

#define SSI_AD_D   (1 << 24)

Definition at line 1205 of file au1000.h.

#define SSI_AD_DATA_BIT   0

Definition at line 1208 of file au1000.h.

#define SSI_AD_DATA_MASK   (0xfff << 0)

Definition at line 1209 of file au1000.h.

#define SSI_ADATA_ADDR   (0xFF << 16)

Definition at line 1261 of file au1000.h.

#define SSI_ADATA_ADDR_N (   N)    (N << 16)

Definition at line 1263 of file au1000.h.

#define SSI_ADATA_D   (1 << 24)

Definition at line 1260 of file au1000.h.

#define SSI_ADATA_DATA   0x0FFF

Definition at line 1262 of file au1000.h.

#define SSI_CONFIG_AD   (1 << 10)

Definition at line 1248 of file au1000.h.

#define SSI_CONFIG_AD   (1 << 10)

Definition at line 1248 of file au1000.h.

#define SSI_CONFIG_ALEN   (7 << 20)

Definition at line 1245 of file au1000.h.

#define SSI_CONFIG_ALEN_BIT   20

Definition at line 1192 of file au1000.h.

#define SSI_CONFIG_ALEN_MASK   (0x7 << 20)

Definition at line 1193 of file au1000.h.

#define SSI_CONFIG_ALEN_N (   N)    ((N-1) << 20)

Definition at line 1254 of file au1000.h.

#define SSI_CONFIG_AO   (1 << 24)

Definition at line 1243 of file au1000.h.

#define SSI_CONFIG_AO   (1 << 24)

Definition at line 1243 of file au1000.h.

#define SSI_CONFIG_BM   (3 << 8)

Definition at line 1249 of file au1000.h.

#define SSI_CONFIG_BM_BIT   8

Definition at line 1198 of file au1000.h.

#define SSI_CONFIG_BM_CY   (2 << 8)

Definition at line 1258 of file au1000.h.

#define SSI_CONFIG_BM_HI   (0 << 8)

Definition at line 1256 of file au1000.h.

#define SSI_CONFIG_BM_LO   (1 << 8)

Definition at line 1257 of file au1000.h.

#define SSI_CONFIG_BM_MASK   (0x3 << 8)

Definition at line 1199 of file au1000.h.

#define SSI_CONFIG_CE   (1 << 7)

Definition at line 1250 of file au1000.h.

#define SSI_CONFIG_CE   (1 << 7)

Definition at line 1250 of file au1000.h.

#define SSI_CONFIG_DD   (1 << 11)

Definition at line 1247 of file au1000.h.

#define SSI_CONFIG_DD   (1 << 11)

Definition at line 1247 of file au1000.h.

#define SSI_CONFIG_DL   (1 << 5)

Definition at line 1252 of file au1000.h.

#define SSI_CONFIG_DL   (1 << 5)

Definition at line 1252 of file au1000.h.

#define SSI_CONFIG_DLEN   (15 << 16)

Definition at line 1246 of file au1000.h.

#define SSI_CONFIG_DLEN_BIT   16

Definition at line 1194 of file au1000.h.

#define SSI_CONFIG_DLEN_MASK   (0x7 << 16)

Definition at line 1195 of file au1000.h.

#define SSI_CONFIG_DLEN_N (   N)    ((N-1) << 16)

Definition at line 1255 of file au1000.h.

#define SSI_CONFIG_DO   (1 << 23)

Definition at line 1244 of file au1000.h.

#define SSI_CONFIG_DO   (1 << 23)

Definition at line 1244 of file au1000.h.

#define SSI_CONFIG_DP   (1 << 6)

Definition at line 1251 of file au1000.h.

#define SSI_CONFIG_DP   (1 << 6)

Definition at line 1251 of file au1000.h.

#define SSI_CONFIG_EP   (1 << 4)

Definition at line 1253 of file au1000.h.

#define SSI_CONFIG_EP   (1 << 4)

Definition at line 1253 of file au1000.h.

#define SSI_CONTROL_CD   (1 << 1)

Definition at line 1212 of file au1000.h.

#define SSI_CONTROL_E   (1 << 0)

Definition at line 1213 of file au1000.h.

#define SSI_ENABLE_CD   (1 << 1)

Definition at line 1265 of file au1000.h.

#define SSI_ENABLE_E   (1 << 0)

Definition at line 1266 of file au1000.h.

#define SSI_INT_DI   (1 << 1)

Definition at line 1236 of file au1000.h.

#define SSI_INT_DI   (1 << 1)

Definition at line 1236 of file au1000.h.

#define SSI_INT_OI   (1 << 3)

Definition at line 1234 of file au1000.h.

#define SSI_INT_OI   (1 << 3)

Definition at line 1234 of file au1000.h.

#define SSI_INT_UI   (1 << 2)

Definition at line 1235 of file au1000.h.

#define SSI_INT_UI   (1 << 2)

Definition at line 1235 of file au1000.h.

#define SSI_INTE_DIE   (1 << 1)

Definition at line 1188 of file au1000.h.

#define SSI_INTE_OIE   (1 << 3)

Definition at line 1186 of file au1000.h.

#define SSI_INTE_UIE   (1 << 2)

Definition at line 1187 of file au1000.h.

#define SSI_INTEN_DIE   (1 << 1)

Definition at line 1241 of file au1000.h.

#define SSI_INTEN_OIE   (1 << 3)

Definition at line 1239 of file au1000.h.

#define SSI_INTEN_UIE   (1 << 2)

Definition at line 1240 of file au1000.h.

#define SSI_STATUS_B   (1 << 0)

Definition at line 1231 of file au1000.h.

#define SSI_STATUS_B   (1 << 0)

Definition at line 1231 of file au1000.h.

#define SSI_STATUS_BF   (1 << 4)

Definition at line 1227 of file au1000.h.

#define SSI_STATUS_BF   (1 << 4)

Definition at line 1227 of file au1000.h.

#define SSI_STATUS_D   (1 << 1)

Definition at line 1230 of file au1000.h.

#define SSI_STATUS_D   (1 << 1)

Definition at line 1230 of file au1000.h.

#define SSI_STATUS_OF   (1 << 3)

Definition at line 1228 of file au1000.h.

#define SSI_STATUS_OF   (1 << 3)

Definition at line 1228 of file au1000.h.

#define SSI_STATUS_UF   (1 << 2)

Definition at line 1229 of file au1000.h.

#define SSI_STATUS_UF   (1 << 2)

Definition at line 1229 of file au1000.h.

#define SYS_AUXPLL   0xB1900064

Definition at line 1435 of file au1000.h.

#define SYS_BASE   0xB1900000

Definition at line 966 of file au1000.h.

#define SYS_CLKSRC   0xB1900028

Definition at line 1394 of file au1000.h.

#define SYS_CNTRL_32S   (1 << 5)

Definition at line 981 of file au1000.h.

#define SYS_CNTRL_BP   (1 << 14)

Definition at line 974 of file au1000.h.

#define SYS_CNTRL_BT0   (1 << 10)

Definition at line 978 of file au1000.h.

#define SYS_CNTRL_BT1   (1 << 12)

Definition at line 976 of file au1000.h.

#define SYS_CNTRL_C0S   (1 << 0)

Definition at line 986 of file au1000.h.

#define SYS_CNTRL_C1S   (1 << 16)

Definition at line 973 of file au1000.h.

#define SYS_CNTRL_E0   (1 << 8)

Definition at line 979 of file au1000.h.

#define SYS_CNTRL_E0S   (1 << 7)

Definition at line 980 of file au1000.h.

#define SYS_CNTRL_E1S   (1 << 23)

Definition at line 968 of file au1000.h.

#define SYS_CNTRL_EN0   (1 << 11)

Definition at line 977 of file au1000.h.

#define SYS_CNTRL_EN1   (1 << 13)

Definition at line 975 of file au1000.h.

#define SYS_CNTRL_M00   (1 << 1)

Definition at line 985 of file au1000.h.

#define SYS_CNTRL_M01   (1 << 17)

Definition at line 972 of file au1000.h.

#define SYS_CNTRL_M10   (1 << 2)

Definition at line 984 of file au1000.h.

#define SYS_CNTRL_M11   (1 << 18)

Definition at line 971 of file au1000.h.

#define SYS_CNTRL_M20   (1 << 3)

Definition at line 983 of file au1000.h.

#define SYS_CNTRL_M21   (1 << 19)

Definition at line 970 of file au1000.h.

#define SYS_CNTRL_T0S   (1 << 4)

Definition at line 982 of file au1000.h.

#define SYS_CNTRL_T1S   (1 << 20)

Definition at line 969 of file au1000.h.

#define SYS_COUNTER_CNTRL   (SYS_BASE + 0x14)

Definition at line 967 of file au1000.h.

#define SYS_CPUPLL   0xB1900060

Definition at line 1434 of file au1000.h.

#define SYS_CS_CE0   (1 << 20)

Definition at line 1402 of file au1000.h.

#define SYS_CS_CE1   (1 << 25)

Definition at line 1398 of file au1000.h.

#define SYS_CS_CI2   (1 << 15)

Definition at line 1406 of file au1000.h.

#define SYS_CS_CIR   (1 << 0)

Definition at line 1425 of file au1000.h.

#define SYS_CS_CL   (1 << 5)

Definition at line 1411 of file au1000.h.

#define SYS_CS_CUD   (1 << 5)

Definition at line 1420 of file au1000.h.

#define SYS_CS_CUH   (1 << 10)

Definition at line 1416 of file au1000.h.

#define SYS_CS_DE0   (1 << 21)

Definition at line 1401 of file au1000.h.

#define SYS_CS_DE1   (1 << 26)

Definition at line 1397 of file au1000.h.

#define SYS_CS_DI2   (1 << 16)

Definition at line 1405 of file au1000.h.

#define SYS_CS_DIR   (1 << 1)

Definition at line 1424 of file au1000.h.

#define SYS_CS_DL   (1 << 6)

Definition at line 1410 of file au1000.h.

#define SYS_CS_DUD   (1 << 6)

Definition at line 1419 of file au1000.h.

#define SYS_CS_DUH   (1 << 11)

Definition at line 1415 of file au1000.h.

#define SYS_CS_ME0_BIT   22

Definition at line 1399 of file au1000.h.

#define SYS_CS_ME0_MASK   (0x7 << SYS_CS_ME0_BIT)

Definition at line 1400 of file au1000.h.

#define SYS_CS_ME1_BIT   27

Definition at line 1395 of file au1000.h.

#define SYS_CS_ME1_MASK   (0x7 << SYS_CS_ME1_BIT)

Definition at line 1396 of file au1000.h.

#define SYS_CS_MI2_BIT   17

Definition at line 1403 of file au1000.h.

#define SYS_CS_MI2_MASK   (0x7 << SYS_CS_MI2_BIT)

Definition at line 1404 of file au1000.h.

#define SYS_CS_MIR_BIT   2

Definition at line 1422 of file au1000.h.

#define SYS_CS_MIR_MASK   (0x7 << SYS_CS_MIR_BIT)

Definition at line 1423 of file au1000.h.

#define SYS_CS_ML_BIT   7

Definition at line 1408 of file au1000.h.

#define SYS_CS_ML_MASK   (0x7 << SYS_CS_ML_BIT)

Definition at line 1409 of file au1000.h.

#define SYS_CS_MUD_BIT   7

Definition at line 1417 of file au1000.h.

#define SYS_CS_MUD_MASK   (0x7 << SYS_CS_MUD_BIT)

Definition at line 1418 of file au1000.h.

#define SYS_CS_MUH_BIT   12

Definition at line 1413 of file au1000.h.

#define SYS_CS_MUH_MASK   (0x7 << SYS_CS_MUH_BIT)

Definition at line 1414 of file au1000.h.

#define SYS_CS_MUX_AUX   0x1

Definition at line 1427 of file au1000.h.

#define SYS_CS_MUX_FQ0   0x2

Definition at line 1428 of file au1000.h.

#define SYS_CS_MUX_FQ1   0x3

Definition at line 1429 of file au1000.h.

#define SYS_CS_MUX_FQ2   0x4

Definition at line 1430 of file au1000.h.

#define SYS_CS_MUX_FQ3   0x5

Definition at line 1431 of file au1000.h.

#define SYS_CS_MUX_FQ4   0x6

Definition at line 1432 of file au1000.h.

#define SYS_CS_MUX_FQ5   0x7

Definition at line 1433 of file au1000.h.

#define SYS_ENDIAN   0xB1900038

Definition at line 1357 of file au1000.h.

#define SYS_FC_FE0   (1 << 1)

Definition at line 1379 of file au1000.h.

#define SYS_FC_FE1   (1 << 11)

Definition at line 1375 of file au1000.h.

#define SYS_FC_FE2   (1 << 21)

Definition at line 1371 of file au1000.h.

#define SYS_FC_FE3   (1 << 1)

Definition at line 1392 of file au1000.h.

#define SYS_FC_FE4   (1 << 11)

Definition at line 1388 of file au1000.h.

#define SYS_FC_FE5   (1 << 21)

Definition at line 1384 of file au1000.h.

#define SYS_FC_FRDIV0_BIT   2

Definition at line 1377 of file au1000.h.

#define SYS_FC_FRDIV0_MASK   (0xff << SYS_FC_FRDIV0_BIT)

Definition at line 1378 of file au1000.h.

#define SYS_FC_FRDIV1_BIT   12

Definition at line 1373 of file au1000.h.

#define SYS_FC_FRDIV1_MASK   (0xff << SYS_FC_FRDIV1_BIT)

Definition at line 1374 of file au1000.h.

#define SYS_FC_FRDIV2_BIT   22

Definition at line 1369 of file au1000.h.

#define SYS_FC_FRDIV2_MASK   (0xff << SYS_FC_FRDIV2_BIT)

Definition at line 1370 of file au1000.h.

#define SYS_FC_FRDIV3_BIT   2

Definition at line 1390 of file au1000.h.

#define SYS_FC_FRDIV3_MASK   (0xff << SYS_FC_FRDIV3_BIT)

Definition at line 1391 of file au1000.h.

#define SYS_FC_FRDIV4_BIT   12

Definition at line 1386 of file au1000.h.

#define SYS_FC_FRDIV4_MASK   (0xff << SYS_FC_FRDIV4_BIT)

Definition at line 1387 of file au1000.h.

#define SYS_FC_FRDIV5_BIT   22

Definition at line 1382 of file au1000.h.

#define SYS_FC_FRDIV5_MASK   (0xff << SYS_FC_FRDIV5_BIT)

Definition at line 1383 of file au1000.h.

#define SYS_FC_FS0   (1 << 0)

Definition at line 1380 of file au1000.h.

#define SYS_FC_FS1   (1 << 10)

Definition at line 1376 of file au1000.h.

#define SYS_FC_FS2   (1 << 20)

Definition at line 1372 of file au1000.h.

#define SYS_FC_FS3   (1 << 0)

Definition at line 1393 of file au1000.h.

#define SYS_FC_FS4   (1 << 10)

Definition at line 1389 of file au1000.h.

#define SYS_FC_FS5   (1 << 20)

Definition at line 1385 of file au1000.h.

#define SYS_FREQCTRL0   0xB1900020

Definition at line 1368 of file au1000.h.

#define SYS_FREQCTRL1   0xB1900024

Definition at line 1381 of file au1000.h.

#define SYS_PF_A97   (1 << 1) /* AC97/SSL1 */

Definition at line 1299 of file au1000.h.

#define SYS_PF_CK4   (1 << 9) /* GPIO2/CLK4 */

Definition at line 1291 of file au1000.h.

#define SYS_PF_CK5   (1 << 10) /* GPIO3/CLK5 */

Definition at line 1290 of file au1000.h.

#define SYS_PF_CS   (1 << 16) /* EXTCLK0/32KHz to gpio2 */

Definition at line 1305 of file au1000.h.

#define SYS_PF_EX0   (1 << 9) /* GPIO2/clock */

Definition at line 1306 of file au1000.h.

#define SYS_PF_I2D   (1 << 6) /* GPIO8/I2SDI */

Definition at line 1294 of file au1000.h.

#define SYS_PF_I2S   (1 << 5) /* I2S/GPIO[29:31] */

Definition at line 1295 of file au1000.h.

#define SYS_PF_IRF   (1 << 8) /* GPIO15/IRFIRSEL */

Definition at line 1292 of file au1000.h.

#define SYS_PF_LCD   (1 << 17) /* extern lcd/GPIO[203:200] */

Definition at line 1304 of file au1000.h.

#define SYS_PF_MUST_BE_SET   ((1 << 5) | (1 << 2))

Definition at line 1322 of file au1000.h.

#define SYS_PF_NI2   (1 << 4) /* NI2/GPIO[24:28] */

Definition at line 1296 of file au1000.h.

#define SYS_PF_PC   (1 << 18) /* PCMCIA/GPIO[207:204] */

Definition at line 1303 of file au1000.h.

#define SYS_PF_PSC1_S1   (1 << 1)

Definition at line 1321 of file au1000.h.

#define SYS_PF_PSC2_AC97   0

Definition at line 1310 of file au1000.h.

#define SYS_PF_PSC2_GPIO   (7 << 17)

Definition at line 1314 of file au1000.h.

#define SYS_PF_PSC2_I2S   (1 << 17)

Definition at line 1312 of file au1000.h.

#define SYS_PF_PSC2_MASK   (7 << 17)

Definition at line 1309 of file au1000.h.

#define SYS_PF_PSC2_SMBUS   (3 << 17)

Definition at line 1313 of file au1000.h.

#define SYS_PF_PSC2_SPI   0

Definition at line 1311 of file au1000.h.

#define SYS_PF_PSC3_AC97   0

Definition at line 1316 of file au1000.h.

#define SYS_PF_PSC3_GPIO   (7 << 20)

Definition at line 1320 of file au1000.h.

#define SYS_PF_PSC3_I2S   (1 << 20)

Definition at line 1318 of file au1000.h.

#define SYS_PF_PSC3_MASK   (7 << 20)

Definition at line 1315 of file au1000.h.

#define SYS_PF_PSC3_SMBUS   (3 << 20)

Definition at line 1319 of file au1000.h.

#define SYS_PF_PSC3_SPI   0

Definition at line 1317 of file au1000.h.

#define SYS_PF_RD   (1 << 2) /* IRTXD/GPIO19 */

Definition at line 1298 of file au1000.h.

#define SYS_PF_S0   (1 << 0) /* SSI_0/GPIO[16:18] */

Definition at line 1300 of file au1000.h.

#define SYS_PF_SRC   (1 << 11) /* GPIO6/SROMCKE */

Definition at line 1289 of file au1000.h.

#define SYS_PF_U0   (1 << 3) /* U0TXD/GPIO20 */

Definition at line 1297 of file au1000.h.

#define SYS_PF_U1   (1 << 12) /* GPIO21/U1TXD */

Definition at line 1288 of file au1000.h.

#define SYS_PF_U2   (1 << 13) /* GPIO22/U2TXD */

Definition at line 1287 of file au1000.h.

#define SYS_PF_U3   (1 << 14) /* GPIO23/U3TXD */

Definition at line 1286 of file au1000.h.

#define SYS_PF_UR3   (1 << 7) /* GPIO[14:9]/UART3 */

Definition at line 1293 of file au1000.h.

#define SYS_PF_USB   (1 << 15) /* 2nd USB device/host */

Definition at line 1285 of file au1000.h.

#define SYS_PINFUNC   0xB190002C

Definition at line 1284 of file au1000.h.

#define SYS_PINFUNC_CIM   (1 << 15)

Definition at line 1339 of file au1000.h.

#define SYS_PINFUNC_CS   (1 << 16)

Definition at line 1338 of file au1000.h.

#define SYS_PINFUNC_DMA   (1 << 31)

Definition at line 1325 of file au1000.h.

#define SYS_PINFUNC_EX0   (1 << 9)

Definition at line 1344 of file au1000.h.

#define SYS_PINFUNC_EX1   (1 << 10)

Definition at line 1343 of file au1000.h.

#define SYS_PINFUNC_FS3   (1 << 19)

Definition at line 1336 of file au1000.h.

#define SYS_PINFUNC_LD0   (1 << 23)

Definition at line 1333 of file au1000.h.

#define SYS_PINFUNC_LD1   (1 << 24)

Definition at line 1332 of file au1000.h.

#define SYS_PINFUNC_LD16   (1 << 26)

Definition at line 1330 of file au1000.h.

#define SYS_PINFUNC_LD8   (1 << 25)

Definition at line 1331 of file au1000.h.

#define SYS_PINFUNC_LP0   (1 << 28)

Definition at line 1328 of file au1000.h.

#define SYS_PINFUNC_LP1   (1 << 27)

Definition at line 1329 of file au1000.h.

#define SYS_PINFUNC_MC   (1 << 7)

Definition at line 1346 of file au1000.h.

#define SYS_PINFUNC_P0A   (3 << 17)

Definition at line 1337 of file au1000.h.

#define SYS_PINFUNC_P0B   (1 << 4)

Definition at line 1349 of file au1000.h.

#define SYS_PINFUNC_P1A   (3 << 21)

Definition at line 1334 of file au1000.h.

#define SYS_PINFUNC_P1B   (1 << 20)

Definition at line 1335 of file au1000.h.

#define SYS_PINFUNC_P1C   (1 << 14)

Definition at line 1340 of file au1000.h.

#define SYS_PINFUNC_S0A   (1 << 30)

Definition at line 1326 of file au1000.h.

#define SYS_PINFUNC_S0B   (1 << 6)

Definition at line 1347 of file au1000.h.

#define SYS_PINFUNC_S0C   (1 << 5)

Definition at line 1348 of file au1000.h.

#define SYS_PINFUNC_S1A   (1 << 29)

Definition at line 1327 of file au1000.h.

#define SYS_PINFUNC_S1B   (1 << 2)

Definition at line 1351 of file au1000.h.

#define SYS_PINFUNC_U0R   (1 << 8)

Definition at line 1345 of file au1000.h.

#define SYS_PINFUNC_U0T   (1 << 3)

Definition at line 1350 of file au1000.h.

#define SYS_PINFUNC_U1R   (1 << 11)

Definition at line 1342 of file au1000.h.

#define SYS_PINFUNC_U1T   (1 << 12)

Definition at line 1341 of file au1000.h.

#define SYS_POWERCTRL   0xB190003C

Definition at line 1358 of file au1000.h.

#define SYS_RTCMATCH0   (SYS_BASE + 0x4C)

Definition at line 999 of file au1000.h.

#define SYS_RTCMATCH1   (SYS_BASE + 0x50)

Definition at line 1000 of file au1000.h.

#define SYS_RTCMATCH2   (SYS_BASE + 0x54)

Definition at line 1001 of file au1000.h.

#define SYS_RTCREAD   (SYS_BASE + 0x58)

Definition at line 1002 of file au1000.h.

#define SYS_RTCTRIM   (SYS_BASE + 0x44)

Definition at line 997 of file au1000.h.

#define SYS_RTCWRITE   (SYS_BASE + 0x48)

Definition at line 998 of file au1000.h.

#define SYS_SCRATCH0   0xB1900018

Definition at line 1354 of file au1000.h.

#define SYS_SCRATCH1   0xB190001C

Definition at line 1355 of file au1000.h.

#define SYS_SLEEP   0xB190007C

Definition at line 1361 of file au1000.h.

#define SYS_SLPPWR   0xB1900078

Definition at line 1360 of file au1000.h.

#define SYS_TOYMATCH0   (SYS_BASE + 8)

Definition at line 991 of file au1000.h.

#define SYS_TOYMATCH1   (SYS_BASE + 0xC)

Definition at line 992 of file au1000.h.

#define SYS_TOYMATCH2   (SYS_BASE + 0x10)

Definition at line 993 of file au1000.h.

#define SYS_TOYREAD   (SYS_BASE + 0x40)

Definition at line 994 of file au1000.h.

#define SYS_TOYTRIM   (SYS_BASE + 0)

Definition at line 989 of file au1000.h.

#define SYS_TOYWRITE   (SYS_BASE + 4)

Definition at line 990 of file au1000.h.

#define SYS_WAKEMSK   0xB1900034

Definition at line 1356 of file au1000.h.

#define SYS_WAKEMSK_D2   (1 << 9)

Definition at line 1363 of file au1000.h.

#define SYS_WAKEMSK_GPIO (   x)    (1 << (x))

Definition at line 1365 of file au1000.h.

#define SYS_WAKEMSK_M2   (1 << 8)

Definition at line 1364 of file au1000.h.

#define SYS_WAKESRC   0xB190005C

Definition at line 1359 of file au1000.h.

#define TX_COLL_CNT_MASK   (0xF << 10)

Definition at line 1106 of file au1000.h.

#define TX_DEFERRED   (1 << 8)

Definition at line 1104 of file au1000.h.

#define TX_DMA_ENABLE   (1 << 0)

Definition at line 1109 of file au1000.h.

#define TX_EXC_COLL   (1 << 6)

Definition at line 1102 of file au1000.h.

#define TX_EXC_DEF   (1 << 4)

Definition at line 1100 of file au1000.h.

#define TX_FRAME_ABORTED   (1 << 0)

Definition at line 1096 of file au1000.h.

#define TX_GET_DMA_BUFFER (   X)    (((X) >> 2) & 0x3)

Definition at line 1111 of file au1000.h.

#define TX_JAB_TIMEOUT   (1 << 1)

Definition at line 1097 of file au1000.h.

#define TX_LATE_COLL   (1 << 9)

Definition at line 1105 of file au1000.h.

#define TX_LATE_COLL_ABORT   (1 << 5)

Definition at line 1101 of file au1000.h.

#define TX_LOSS_CARRIER   (1 << 3)

Definition at line 1099 of file au1000.h.

#define TX_NO_CARRIER   (1 << 2)

Definition at line 1098 of file au1000.h.

#define TX_PKT_RETRY   (1 << 31)

Definition at line 1107 of file au1000.h.

#define TX_T_DONE   (1 << 1)

Definition at line 1110 of file au1000.h.

#define TX_UNDERRUN   (1 << 7)

Definition at line 1103 of file au1000.h.

#define UART_CLK   0x28 /* Baud Rate Clock Divider */

Definition at line 1171 of file au1000.h.

#define UART_FCR   0x10 /* FIFO Control Register */

Definition at line 1166 of file au1000.h.

#define UART_IER   8 /* Interrupt Enable Register */

Definition at line 1164 of file au1000.h.

#define UART_IIR   0xC /* Interrupt ID Register */

Definition at line 1165 of file au1000.h.

#define UART_LCR   0x14 /* Line Control Register */

Definition at line 1167 of file au1000.h.

#define UART_LSR   0x1C /* Line Status Register */

Definition at line 1169 of file au1000.h.

#define UART_MCR   0x18 /* Modem Control Register */

Definition at line 1168 of file au1000.h.

#define UART_MOD_CNTRL   0x100 /* Module Control */

Definition at line 1172 of file au1000.h.

#define UART_MSR   0x20 /* Modem Status Register */

Definition at line 1170 of file au1000.h.

#define UART_RX   0 /* Receive buffer */

Definition at line 1162 of file au1000.h.

#define UART_TX   4 /* Transmit buffer */

Definition at line 1163 of file au1000.h.

Enumeration Type Documentation

enum alchemy_usb_block
Enumerator:
ALCHEMY_USB_OHCI0 
ALCHEMY_USB_UDC0 
ALCHEMY_USB_EHCI0 
ALCHEMY_USB_OTG0 
ALCHEMY_USB_OHCI1 

Definition at line 255 of file au1000.h.

enum au1300_multifunc_pins
Enumerator:
AU1300_PIN_WAKE0 
AU1300_PIN_WAKE1 
AU1300_PIN_WAKE2 
AU1300_PIN_WAKE3 
AU1300_PIN_EXTCLK0 
AU1300_PIN_EXTCLK1 
AU1300_PIN_SD0DAT4 
AU1300_PIN_SD0DAT5 
AU1300_PIN_SD0DAT6 
AU1300_PIN_SD0DAT7 
AU1300_PIN_FG3AUX 
AU1300_PIN_U1RI 
AU1300_PIN_U1DCD 
AU1300_PIN_U1DSR 
AU1300_PIN_U1CTS 
AU1300_PIN_U1RTS 
AU1300_PIN_U1DTR 
AU1300_PIN_U1RX 
AU1300_PIN_U1TX 
AU1300_PIN_U0RI 
AU1300_PIN_U0DCD 
AU1300_PIN_U0DSR 
AU1300_PIN_U0CTS 
AU1300_PIN_U0RTS 
AU1300_PIN_U0DTR 
AU1300_PIN_U2RX 
AU1300_PIN_U2TX 
AU1300_PIN_U3RX 
AU1300_PIN_U3TX 
AU1300_PIN_LCDPWM0 
AU1300_PIN_LCDPWM1 
AU1300_PIN_LCDCLKIN 
AU1300_PIN_SD1DAT0 
AU1300_PIN_SD1DAT1 
AU1300_PIN_SD1DAT2 
AU1300_PIN_SD1DAT3 
AU1300_PIN_SD1CMD 
AU1300_PIN_SD1CLK 
AU1300_PIN_SD2DAT0 
AU1300_PIN_SD2DAT1 
AU1300_PIN_SD2DAT2 
AU1300_PIN_SD2DAT3 
AU1300_PIN_SD2CMD 
AU1300_PIN_SD2CLK 
AU1300_PIN_PSC0CLK 
AU1300_PIN_PSC1CLK 
AU1300_PIN_PSC0SYNC0 
AU1300_PIN_PSC0SYNC1 
AU1300_PIN_PSC0D0 
AU1300_PIN_PSC0D1 
AU1300_PIN_PSC1SYNC0 
AU1300_PIN_PSC1SYNC1 
AU1300_PIN_PSC1D0 
AU1300_PIN_PSC1D1 
AU1300_PIN_PSC2SYNC0 
AU1300_PIN_PSC2SYNC1 
AU1300_PIN_PSC2D0 
AU1300_PIN_PSC2D1 
AU1300_PIN_PSC3SYNC0 
AU1300_PIN_PSC3SYNC1 
AU1300_PIN_PSC3D0 
AU1300_PIN_PSC3D1 
AU1300_PIN_PCE2 
AU1300_PIN_PCE1 
AU1300_PIN_PIOS16 
AU1300_PIN_PIOR 
AU1300_PIN_PWE 
AU1300_PIN_PWAIT 
AU1300_PIN_PREG 
AU1300_PIN_POE 
AU1300_PIN_PIOW 
AU1300_PIN_CIMLS 
AU1300_PIN_CIMFS 
AU1300_PIN_PSC2CLK 
AU1300_PIN_PSC3CLK 

Definition at line 278 of file au1000.h.

enum au1300_vss_block
Enumerator:
AU1300_VSS_MPE 
AU1300_VSS_BSA 
AU1300_VSS_GPE 
AU1300_VSS_MGP 

Definition at line 336 of file au1000.h.

enum soc_au1000_ints
Enumerator:
AU1000_FIRST_INT 
AU1000_UART0_INT 
AU1000_UART1_INT 
AU1000_UART2_INT 
AU1000_UART3_INT 
AU1000_SSI0_INT 
AU1000_SSI1_INT 
AU1000_DMA_INT_BASE 
AU1000_TOY_INT 
AU1000_TOY_MATCH0_INT 
AU1000_TOY_MATCH1_INT 
AU1000_TOY_MATCH2_INT 
AU1000_RTC_INT 
AU1000_RTC_MATCH0_INT 
AU1000_RTC_MATCH1_INT 
AU1000_RTC_MATCH2_INT 
AU1000_IRDA_TX_INT 
AU1000_IRDA_RX_INT 
AU1000_USB_DEV_REQ_INT 
AU1000_USB_DEV_SUS_INT 
AU1000_USB_HOST_INT 
AU1000_ACSYNC_INT 
AU1000_MAC0_DMA_INT 
AU1000_MAC1_DMA_INT 
AU1000_I2S_UO_INT 
AU1000_AC97C_INT 
AU1000_GPIO0_INT 
AU1000_GPIO1_INT 
AU1000_GPIO2_INT 
AU1000_GPIO3_INT 
AU1000_GPIO4_INT 
AU1000_GPIO5_INT 
AU1000_GPIO6_INT 
AU1000_GPIO7_INT 
AU1000_GPIO8_INT 
AU1000_GPIO9_INT 
AU1000_GPIO10_INT 
AU1000_GPIO11_INT 
AU1000_GPIO12_INT 
AU1000_GPIO13_INT 
AU1000_GPIO14_INT 
AU1000_GPIO15_INT 
AU1000_GPIO16_INT 
AU1000_GPIO17_INT 
AU1000_GPIO18_INT 
AU1000_GPIO19_INT 
AU1000_GPIO20_INT 
AU1000_GPIO21_INT 
AU1000_GPIO22_INT 
AU1000_GPIO23_INT 
AU1000_GPIO24_INT 
AU1000_GPIO25_INT 
AU1000_GPIO26_INT 
AU1000_GPIO27_INT 
AU1000_GPIO28_INT 
AU1000_GPIO29_INT 
AU1000_GPIO30_INT 
AU1000_GPIO31_INT 

Definition at line 359 of file au1000.h.

enum soc_au1100_ints
Enumerator:
AU1100_FIRST_INT 
AU1100_UART0_INT 
AU1100_UART1_INT 
AU1100_SD_INT 
AU1100_UART3_INT 
AU1100_SSI0_INT 
AU1100_SSI1_INT 
AU1100_DMA_INT_BASE 
AU1100_TOY_INT 
AU1100_TOY_MATCH0_INT 
AU1100_TOY_MATCH1_INT 
AU1100_TOY_MATCH2_INT 
AU1100_RTC_INT 
AU1100_RTC_MATCH0_INT 
AU1100_RTC_MATCH1_INT 
AU1100_RTC_MATCH2_INT 
AU1100_IRDA_TX_INT 
AU1100_IRDA_RX_INT 
AU1100_USB_DEV_REQ_INT 
AU1100_USB_DEV_SUS_INT 
AU1100_USB_HOST_INT 
AU1100_ACSYNC_INT 
AU1100_MAC0_DMA_INT 
AU1100_GPIO208_215_INT 
AU1100_LCD_INT 
AU1100_AC97C_INT 
AU1100_GPIO0_INT 
AU1100_GPIO1_INT 
AU1100_GPIO2_INT 
AU1100_GPIO3_INT 
AU1100_GPIO4_INT 
AU1100_GPIO5_INT 
AU1100_GPIO6_INT 
AU1100_GPIO7_INT 
AU1100_GPIO8_INT 
AU1100_GPIO9_INT 
AU1100_GPIO10_INT 
AU1100_GPIO11_INT 
AU1100_GPIO12_INT 
AU1100_GPIO13_INT 
AU1100_GPIO14_INT 
AU1100_GPIO15_INT 
AU1100_GPIO16_INT 
AU1100_GPIO17_INT 
AU1100_GPIO18_INT 
AU1100_GPIO19_INT 
AU1100_GPIO20_INT 
AU1100_GPIO21_INT 
AU1100_GPIO22_INT 
AU1100_GPIO23_INT 
AU1100_GPIO24_INT 
AU1100_GPIO25_INT 
AU1100_GPIO26_INT 
AU1100_GPIO27_INT 
AU1100_GPIO28_INT 
AU1100_GPIO29_INT 
AU1100_GPIO30_INT 
AU1100_GPIO31_INT 

Definition at line 421 of file au1000.h.

enum soc_au1200_ints
Enumerator:
AU1200_FIRST_INT 
AU1200_UART0_INT 
AU1200_SWT_INT 
AU1200_SD_INT 
AU1200_DDMA_INT 
AU1200_MAE_BE_INT 
AU1200_GPIO200_INT 
AU1200_GPIO201_INT 
AU1200_GPIO202_INT 
AU1200_UART1_INT 
AU1200_MAE_FE_INT 
AU1200_PSC0_INT 
AU1200_PSC1_INT 
AU1200_AES_INT 
AU1200_CAMERA_INT 
AU1200_TOY_INT 
AU1200_TOY_MATCH0_INT 
AU1200_TOY_MATCH1_INT 
AU1200_TOY_MATCH2_INT 
AU1200_RTC_INT 
AU1200_RTC_MATCH0_INT 
AU1200_RTC_MATCH1_INT 
AU1200_RTC_MATCH2_INT 
AU1200_GPIO203_INT 
AU1200_NAND_INT 
AU1200_GPIO204_INT 
AU1200_GPIO205_INT 
AU1200_GPIO206_INT 
AU1200_GPIO207_INT 
AU1200_GPIO208_215_INT 
AU1200_USB_INT 
AU1200_LCD_INT 
AU1200_MAE_BOTH_INT 
AU1200_GPIO0_INT 
AU1200_GPIO1_INT 
AU1200_GPIO2_INT 
AU1200_GPIO3_INT 
AU1200_GPIO4_INT 
AU1200_GPIO5_INT 
AU1200_GPIO6_INT 
AU1200_GPIO7_INT 
AU1200_GPIO8_INT 
AU1200_GPIO9_INT 
AU1200_GPIO10_INT 
AU1200_GPIO11_INT 
AU1200_GPIO12_INT 
AU1200_GPIO13_INT 
AU1200_GPIO14_INT 
AU1200_GPIO15_INT 
AU1200_GPIO16_INT 
AU1200_GPIO17_INT 
AU1200_GPIO18_INT 
AU1200_GPIO19_INT 
AU1200_GPIO20_INT 
AU1200_GPIO21_INT 
AU1200_GPIO22_INT 
AU1200_GPIO23_INT 
AU1200_GPIO24_INT 
AU1200_GPIO25_INT 
AU1200_GPIO26_INT 
AU1200_GPIO27_INT 
AU1200_GPIO28_INT 
AU1200_GPIO29_INT 
AU1200_GPIO30_INT 
AU1200_GPIO31_INT 

Definition at line 609 of file au1000.h.

enum soc_au1500_ints
Enumerator:
AU1500_FIRST_INT 
AU1500_UART0_INT 
AU1500_PCI_INTA 
AU1500_PCI_INTB 
AU1500_UART3_INT 
AU1500_PCI_INTC 
AU1500_PCI_INTD 
AU1500_DMA_INT_BASE 
AU1500_TOY_INT 
AU1500_TOY_MATCH0_INT 
AU1500_TOY_MATCH1_INT 
AU1500_TOY_MATCH2_INT 
AU1500_RTC_INT 
AU1500_RTC_MATCH0_INT 
AU1500_RTC_MATCH1_INT 
AU1500_RTC_MATCH2_INT 
AU1500_PCI_ERR_INT 
AU1500_RESERVED_INT 
AU1500_USB_DEV_REQ_INT 
AU1500_USB_DEV_SUS_INT 
AU1500_USB_HOST_INT 
AU1500_ACSYNC_INT 
AU1500_MAC0_DMA_INT 
AU1500_MAC1_DMA_INT 
AU1500_AC97C_INT 
AU1500_GPIO0_INT 
AU1500_GPIO1_INT 
AU1500_GPIO2_INT 
AU1500_GPIO3_INT 
AU1500_GPIO4_INT 
AU1500_GPIO5_INT 
AU1500_GPIO6_INT 
AU1500_GPIO7_INT 
AU1500_GPIO8_INT 
AU1500_GPIO9_INT 
AU1500_GPIO10_INT 
AU1500_GPIO11_INT 
AU1500_GPIO12_INT 
AU1500_GPIO13_INT 
AU1500_GPIO14_INT 
AU1500_GPIO15_INT 
AU1500_GPIO200_INT 
AU1500_GPIO201_INT 
AU1500_GPIO202_INT 
AU1500_GPIO203_INT 
AU1500_GPIO20_INT 
AU1500_GPIO204_INT 
AU1500_GPIO205_INT 
AU1500_GPIO23_INT 
AU1500_GPIO24_INT 
AU1500_GPIO25_INT 
AU1500_GPIO26_INT 
AU1500_GPIO27_INT 
AU1500_GPIO28_INT 
AU1500_GPIO206_INT 
AU1500_GPIO207_INT 
AU1500_GPIO208_215_INT 

Definition at line 483 of file au1000.h.

enum soc_au1550_ints
Enumerator:
AU1550_FIRST_INT 
AU1550_UART0_INT 
AU1550_PCI_INTA 
AU1550_PCI_INTB 
AU1550_DDMA_INT 
AU1550_CRYPTO_INT 
AU1550_PCI_INTC 
AU1550_PCI_INTD 
AU1550_PCI_RST_INT 
AU1550_UART1_INT 
AU1550_UART3_INT 
AU1550_PSC0_INT 
AU1550_PSC1_INT 
AU1550_PSC2_INT 
AU1550_PSC3_INT 
AU1550_TOY_INT 
AU1550_TOY_MATCH0_INT 
AU1550_TOY_MATCH1_INT 
AU1550_TOY_MATCH2_INT 
AU1550_RTC_INT 
AU1550_RTC_MATCH0_INT 
AU1550_RTC_MATCH1_INT 
AU1550_RTC_MATCH2_INT 
AU1550_NAND_INT 
AU1550_USB_DEV_REQ_INT 
AU1550_USB_DEV_SUS_INT 
AU1550_USB_HOST_INT 
AU1550_MAC0_DMA_INT 
AU1550_MAC1_DMA_INT 
AU1550_GPIO0_INT 
AU1550_GPIO1_INT 
AU1550_GPIO2_INT 
AU1550_GPIO3_INT 
AU1550_GPIO4_INT 
AU1550_GPIO5_INT 
AU1550_GPIO6_INT 
AU1550_GPIO7_INT 
AU1550_GPIO8_INT 
AU1550_GPIO9_INT 
AU1550_GPIO10_INT 
AU1550_GPIO11_INT 
AU1550_GPIO12_INT 
AU1550_GPIO13_INT 
AU1550_GPIO14_INT 
AU1550_GPIO15_INT 
AU1550_GPIO200_INT 
AU1550_GPIO201_205_INT 
AU1550_GPIO16_INT 
AU1550_GPIO17_INT 
AU1550_GPIO20_INT 
AU1550_GPIO21_INT 
AU1550_GPIO22_INT 
AU1550_GPIO23_INT 
AU1550_GPIO24_INT 
AU1550_GPIO25_INT 
AU1550_GPIO26_INT 
AU1550_GPIO27_INT 
AU1550_GPIO28_INT 
AU1550_GPIO206_INT 
AU1550_GPIO207_INT 
AU1550_GPIO208_215_INT 

Definition at line 544 of file au1000.h.

Function Documentation

void alchemy_sleep_au1000 ( void  )
void alchemy_sleep_au1300 ( void  )
void alchemy_sleep_au1550 ( void  )
int alchemy_usb_control ( int  block,
int  enable 
)

Definition at line 470 of file alchemy-common.c.

void au1300_pinfunc_to_dev ( enum au1300_multifunc_pins  gpio)

Definition at line 550 of file irq.c.

void au1300_pinfunc_to_gpio ( enum au1300_multifunc_pins  gpio)

Definition at line 537 of file irq.c.

void au1300_set_dbdma_gpio ( int  dchan,
unsigned int  gpio 
)

Definition at line 582 of file irq.c.

void au1300_set_irq_priority ( unsigned int  irq,
int  p 
)

Definition at line 567 of file irq.c.

void au1300_vss_block_control ( int  block,
int  enable 
)

Definition at line 69 of file vss.c.

unsigned long au1xxx_calc_clock ( void  )

Definition at line 82 of file clocks.c.

void au_sleep ( void  )

Definition at line 115 of file power.c.

unsigned int get_au1x00_speed ( void  )

Definition at line 51 of file clocks.c.

unsigned long get_au1x00_uart_baud_base ( void  )

Definition at line 62 of file clocks.c.

void set_au1x00_speed ( unsigned int  new_freq)

Definition at line 46 of file clocks.c.

void set_au1x00_uart_baud_base ( unsigned long  new_baud_base)

Definition at line 67 of file clocks.c.

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