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| #define JZ_REG_TIMER_CNT |
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(((x) * 0x10) + 0x38) |
| #define JZ_REG_TIMER_CTRL |
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(((x) * 0x10) + 0x3C) |
| #define JZ_REG_TIMER_DFR |
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(((x) * 0x10) + 0x30) |
| #define JZ_REG_TIMER_DHR |
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(((x) * 0x10) + 0x34) |
| #define JZ_REG_TIMER_ENABLE 0x00 |
| #define JZ_REG_TIMER_ENABLE_CLEAR 0x08 |
| #define JZ_REG_TIMER_ENABLE_SET 0x04 |
| #define JZ_REG_TIMER_FLAG 0x10 |
| #define JZ_REG_TIMER_FLAG_CLEAR 0x18 |
| #define JZ_REG_TIMER_FLAG_SET 0x14 |
| #define JZ_REG_TIMER_MASK 0x20 |
| #define JZ_REG_TIMER_MASK_CLEAR 0x28 |
| #define JZ_REG_TIMER_MASK_SET 0x24 |
| #define JZ_REG_TIMER_STOP 0x0C |
| #define JZ_REG_TIMER_STOP_CLEAR 0x2C |
| #define JZ_REG_TIMER_STOP_SET 0x1C |
| #define JZ_TIMER_CTRL_PRESCALE_1 (0 << 3) |
| #define JZ_TIMER_CTRL_PRESCALE_1024 (5 << 3) |
| #define JZ_TIMER_CTRL_PRESCALE_16 (2 << 3) |
| #define JZ_TIMER_CTRL_PRESCALE_256 (4 << 3) |
| #define JZ_TIMER_CTRL_PRESCALE_4 (1 << 3) |
| #define JZ_TIMER_CTRL_PRESCALE_64 (3 << 3) |
| #define JZ_TIMER_CTRL_PRESCALE_MASK 0x1c |
| #define JZ_TIMER_CTRL_PRESCALE_OFFSET 0x3 |
| #define JZ_TIMER_CTRL_PWM_ABBRUPT_SHUTDOWN BIT(9) |
| #define JZ_TIMER_CTRL_PWM_ACTIVE_LOW BIT(8) |
| #define JZ_TIMER_CTRL_PWM_ENABLE BIT(7) |
| #define JZ_TIMER_CTRL_SRC_EXT BIT(2) |
| #define JZ_TIMER_CTRL_SRC_PCLK BIT(0) |
| #define JZ_TIMER_CTRL_SRC_RTC BIT(1) |
| #define JZ_TIMER_IRQ_FULL |
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BIT(x) |
| #define JZ_TIMER_IRQ_HALF |
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BIT((x) + 0x10) |
| void jz4740_timer_disable_watchdog |
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| void jz4740_timer_enable_watchdog |
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void |
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1.8.2