|
Linux Kernel
3.7.1
|
All Data Structures Namespaces Files Functions Variables Typedefs Enumerations Enumerator Macros Groups Pages
|
Linux Kernel
3.7.1
|
Go to the source code of this file.
Data Structures | |
| struct | sgimc_regs |
Macros | |
| #define | SGIMC_CCTRL0_REFS 0x0000000f /* REFS mask */ |
| #define | SGIMC_CCTRL0_EREFRESH 0x00000010 /* Memory refresh enable */ |
| #define | SGIMC_CCTRL0_EPERRGIO 0x00000020 /* GIO parity error enable */ |
| #define | SGIMC_CCTRL0_EPERRMEM 0x00000040 /* Main mem parity error enable */ |
| #define | SGIMC_CCTRL0_EPERRCPU 0x00000080 /* CPU bus parity error enable */ |
| #define | SGIMC_CCTRL0_WDOG 0x00000100 /* Watchdog timer enable */ |
| #define | SGIMC_CCTRL0_SYSINIT 0x00000200 /* System init bit */ |
| #define | SGIMC_CCTRL0_GFXRESET 0x00000400 /* Graphics interface reset */ |
| #define | SGIMC_CCTRL0_EISALOCK 0x00000800 /* Lock CPU from memory for EISA */ |
| #define | SGIMC_CCTRL0_EPERRSCMD 0x00001000 /* SysCMD bus parity error enable */ |
| #define | SGIMC_CCTRL0_IENAB 0x00002000 /* Allow interrupts from MC */ |
| #define | SGIMC_CCTRL0_ESNOOP 0x00004000 /* Snooping I/O enable */ |
| #define | SGIMC_CCTRL0_EPROMWR 0x00008000 /* Prom writes from cpu enable */ |
| #define | SGIMC_CCTRL0_WRESETPMEM 0x00010000 /* Perform warm reset, preserves mem */ |
| #define | SGIMC_CCTRL0_LENDIAN 0x00020000 /* Put MC in little-endian mode */ |
| #define | SGIMC_CCTRL0_WRESETDMEM 0x00040000 /* Warm reset, destroys mem contents */ |
| #define | SGIMC_CCTRL0_CMEMBADPAR 0x02000000 /* Generate bad perr from cpu to mem */ |
| #define | SGIMC_CCTRL0_R4KNOCHKPARR 0x04000000 /* Don't chk parity on mem data reads */ |
| #define | SGIMC_CCTRL0_GIOBTOB 0x08000000 /* Allow GIO back to back writes */ |
| #define | SGIMC_CCTRL1_EGIOTIMEO 0x00000010 /* GIO bus timeout enable */ |
| #define | SGIMC_CCTRL1_FIXEDEHPC 0x00001000 /* Fixed HPC endianness */ |
| #define | SGIMC_CCTRL1_LITTLEHPC 0x00002000 /* Little endian HPC */ |
| #define | SGIMC_CCTRL1_FIXEDEEXP0 0x00004000 /* Fixed EXP0 endianness */ |
| #define | SGIMC_CCTRL1_LITTLEEXP0 0x00008000 /* Little endian EXP0 */ |
| #define | SGIMC_CCTRL1_FIXEDEEXP1 0x00010000 /* Fixed EXP1 endianness */ |
| #define | SGIMC_CCTRL1_LITTLEEXP1 0x00020000 /* Little endian EXP1 */ |
| #define | SGIMC_SYSID_MASKREV 0x0000000f /* Revision of MC controller */ |
| #define | SGIMC_SYSID_EPRESENT 0x00000010 /* Indicates presence of EISA bus */ |
| #define | SGIMC_EEPROM_PRE 0x00000001 /* eeprom chip PRE pin assertion */ |
| #define | SGIMC_EEPROM_CSEL 0x00000002 /* Active high, eeprom chip select */ |
| #define | SGIMC_EEPROM_SECLOCK 0x00000004 /* EEPROM serial clock */ |
| #define | SGIMC_EEPROM_SDATAO 0x00000008 /* Serial EEPROM data-out */ |
| #define | SGIMC_EEPROM_SDATAI 0x00000010 /* Serial EEPROM data-in */ |
| #define | SGIMC_GIOPAR_HPC64 0x00000001 /* HPC talks to GIO using 64-bits */ |
| #define | SGIMC_GIOPAR_GFX64 0x00000002 /* GFX talks to GIO using 64-bits */ |
| #define | SGIMC_GIOPAR_EXP064 0x00000004 /* EXP(slot0) talks using 64-bits */ |
| #define | SGIMC_GIOPAR_EXP164 0x00000008 /* EXP(slot1) talks using 64-bits */ |
| #define | SGIMC_GIOPAR_EISA64 0x00000010 /* EISA bus talks 64-bits to GIO */ |
| #define | SGIMC_GIOPAR_HPC264 0x00000020 /* 2nd HPX talks 64-bits to GIO */ |
| #define | SGIMC_GIOPAR_RTIMEGFX 0x00000040 /* GFX device has realtime attr */ |
| #define | SGIMC_GIOPAR_RTIMEEXP0 0x00000080 /* EXP(slot0) has realtime attr */ |
| #define | SGIMC_GIOPAR_RTIMEEXP1 0x00000100 /* EXP(slot1) has realtime attr */ |
| #define | SGIMC_GIOPAR_MASTEREISA 0x00000200 /* EISA bus can act as bus master */ |
| #define | SGIMC_GIOPAR_ONEBUS 0x00000400 /* Exists one GIO64 pipelined bus */ |
| #define | SGIMC_GIOPAR_MASTERGFX 0x00000800 /* GFX can act as a bus master */ |
| #define | SGIMC_GIOPAR_MASTEREXP0 0x00001000 /* EXP(slot0) can bus master */ |
| #define | SGIMC_GIOPAR_MASTEREXP1 0x00002000 /* EXP(slot1) can bus master */ |
| #define | SGIMC_GIOPAR_PLINEEXP0 0x00004000 /* EXP(slot0) has pipeline attr */ |
| #define | SGIMC_GIOPAR_PLINEEXP1 0x00008000 /* EXP(slot1) has pipeline attr */ |
| #define | SGIMC_MCONFIG_BASEADDR 0x000000ff /* Base address of bank*/ |
| #define | SGIMC_MCONFIG_RMASK 0x00001f00 /* Ram config bitmask */ |
| #define | SGIMC_MCONFIG_BVALID 0x00002000 /* Bank is valid */ |
| #define | SGIMC_MCONFIG_SBANKS 0x00004000 /* Number of subbanks */ |
| #define | SGIMC_MACC_ALIASBIG 0x20000000 /* 512MB home for alias */ |
| #define | SGIMC_CSTAT_RD 0x00000100 /* read parity error */ |
| #define | SGIMC_CSTAT_PAR 0x00000200 /* CPU parity error */ |
| #define | SGIMC_CSTAT_ADDR 0x00000400 /* memory bus error bad addr */ |
| #define | SGIMC_CSTAT_SYSAD_PAR 0x00000800 /* sysad parity error */ |
| #define | SGIMC_CSTAT_SYSCMD_PAR 0x00001000 /* syscmd parity error */ |
| #define | SGIMC_CSTAT_BAD_DATA 0x00002000 /* bad data identifier */ |
| #define | SGIMC_CSTAT_PAR_MASK 0x00001f00 /* parity error mask */ |
| #define | SGIMC_CSTAT_RD_PAR (SGIMC_CSTAT_RD | SGIMC_CSTAT_PAR) |
| #define | SGIMC_GSTAT_RD 0x00000100 /* read parity error */ |
| #define | SGIMC_GSTAT_WR 0x00000200 /* write parity error */ |
| #define | SGIMC_GSTAT_TIME 0x00000400 /* GIO bus timed out */ |
| #define | SGIMC_GSTAT_PROM 0x00000800 /* write to PROM when PROM_EN not set */ |
| #define | SGIMC_GSTAT_ADDR 0x00001000 /* parity error on addr cycle */ |
| #define | SGIMC_GSTAT_BC 0x00002000 /* parity error on byte count cycle */ |
| #define | SGIMC_GSTAT_PIO_RD 0x00004000 /* read data parity on pio */ |
| #define | SGIMC_GSTAT_PIO_WR 0x00008000 /* write data parity on pio */ |
| #define | SGIMC_BASE 0x1fa00000 /* physical */ |
| #define | SGIMC_SEG0_BADDR 0x08000000 |
| #define | SGIMC_SEG1_BADDR 0x20000000 |
| #define | SGIMC_SEG0_SIZE_ALL 0x10000000 /* 256MB */ |
| #define | SGIMC_SEG1_SIZE_IP20_IP22 0x08000000 /* 128MB */ |
| #define | SGIMC_SEG1_SIZE_IP26_IP28 0x20000000 /* 512MB */ |
Functions | |
| void | sgimc_init (void) |
Variables | |
| struct sgimc_regs * | sgimc |
| #define SGIMC_CCTRL0_CMEMBADPAR 0x02000000 /* Generate bad perr from cpu to mem */ |
| #define SGIMC_CCTRL0_EISALOCK 0x00000800 /* Lock CPU from memory for EISA */ |
| #define SGIMC_CCTRL0_EPERRCPU 0x00000080 /* CPU bus parity error enable */ |
| #define SGIMC_CCTRL0_EPERRGIO 0x00000020 /* GIO parity error enable */ |
| #define SGIMC_CCTRL0_EPERRMEM 0x00000040 /* Main mem parity error enable */ |
| #define SGIMC_CCTRL0_EPERRSCMD 0x00001000 /* SysCMD bus parity error enable */ |
| #define SGIMC_CCTRL0_EPROMWR 0x00008000 /* Prom writes from cpu enable */ |
| #define SGIMC_CCTRL0_EREFRESH 0x00000010 /* Memory refresh enable */ |
| #define SGIMC_CCTRL0_ESNOOP 0x00004000 /* Snooping I/O enable */ |
| #define SGIMC_CCTRL0_GFXRESET 0x00000400 /* Graphics interface reset */ |
| #define SGIMC_CCTRL0_GIOBTOB 0x08000000 /* Allow GIO back to back writes */ |
| #define SGIMC_CCTRL0_IENAB 0x00002000 /* Allow interrupts from MC */ |
| #define SGIMC_CCTRL0_LENDIAN 0x00020000 /* Put MC in little-endian mode */ |
| #define SGIMC_CCTRL0_R4KNOCHKPARR 0x04000000 /* Don't chk parity on mem data reads */ |
| #define SGIMC_CCTRL0_WDOG 0x00000100 /* Watchdog timer enable */ |
| #define SGIMC_CCTRL0_WRESETDMEM 0x00040000 /* Warm reset, destroys mem contents */ |
| #define SGIMC_CCTRL0_WRESETPMEM 0x00010000 /* Perform warm reset, preserves mem */ |
| #define SGIMC_CCTRL1_EGIOTIMEO 0x00000010 /* GIO bus timeout enable */ |
| #define SGIMC_CCTRL1_FIXEDEEXP0 0x00004000 /* Fixed EXP0 endianness */ |
| #define SGIMC_CCTRL1_FIXEDEEXP1 0x00010000 /* Fixed EXP1 endianness */ |
| #define SGIMC_CCTRL1_FIXEDEHPC 0x00001000 /* Fixed HPC endianness */ |
| #define SGIMC_CCTRL1_LITTLEEXP0 0x00008000 /* Little endian EXP0 */ |
| #define SGIMC_CCTRL1_LITTLEEXP1 0x00020000 /* Little endian EXP1 */ |
| #define SGIMC_CCTRL1_LITTLEHPC 0x00002000 /* Little endian HPC */ |
| #define SGIMC_CSTAT_ADDR 0x00000400 /* memory bus error bad addr */ |
| #define SGIMC_CSTAT_BAD_DATA 0x00002000 /* bad data identifier */ |
| #define SGIMC_CSTAT_PAR_MASK 0x00001f00 /* parity error mask */ |
| #define SGIMC_CSTAT_RD_PAR (SGIMC_CSTAT_RD | SGIMC_CSTAT_PAR) |
| #define SGIMC_CSTAT_SYSAD_PAR 0x00000800 /* sysad parity error */ |
| #define SGIMC_CSTAT_SYSCMD_PAR 0x00001000 /* syscmd parity error */ |
| #define SGIMC_EEPROM_CSEL 0x00000002 /* Active high, eeprom chip select */ |
| #define SGIMC_EEPROM_PRE 0x00000001 /* eeprom chip PRE pin assertion */ |
| #define SGIMC_EEPROM_SDATAI 0x00000010 /* Serial EEPROM data-in */ |
| #define SGIMC_EEPROM_SDATAO 0x00000008 /* Serial EEPROM data-out */ |
| #define SGIMC_EEPROM_SECLOCK 0x00000004 /* EEPROM serial clock */ |
| #define SGIMC_GIOPAR_EISA64 0x00000010 /* EISA bus talks 64-bits to GIO */ |
| #define SGIMC_GIOPAR_EXP064 0x00000004 /* EXP(slot0) talks using 64-bits */ |
| #define SGIMC_GIOPAR_EXP164 0x00000008 /* EXP(slot1) talks using 64-bits */ |
| #define SGIMC_GIOPAR_GFX64 0x00000002 /* GFX talks to GIO using 64-bits */ |
| #define SGIMC_GIOPAR_HPC264 0x00000020 /* 2nd HPX talks 64-bits to GIO */ |
| #define SGIMC_GIOPAR_HPC64 0x00000001 /* HPC talks to GIO using 64-bits */ |
| #define SGIMC_GIOPAR_MASTEREISA 0x00000200 /* EISA bus can act as bus master */ |
| #define SGIMC_GIOPAR_MASTEREXP0 0x00001000 /* EXP(slot0) can bus master */ |
| #define SGIMC_GIOPAR_MASTEREXP1 0x00002000 /* EXP(slot1) can bus master */ |
| #define SGIMC_GIOPAR_MASTERGFX 0x00000800 /* GFX can act as a bus master */ |
| #define SGIMC_GIOPAR_ONEBUS 0x00000400 /* Exists one GIO64 pipelined bus */ |
| #define SGIMC_GIOPAR_PLINEEXP0 0x00004000 /* EXP(slot0) has pipeline attr */ |
| #define SGIMC_GIOPAR_PLINEEXP1 0x00008000 /* EXP(slot1) has pipeline attr */ |
| #define SGIMC_GIOPAR_RTIMEEXP0 0x00000080 /* EXP(slot0) has realtime attr */ |
| #define SGIMC_GIOPAR_RTIMEEXP1 0x00000100 /* EXP(slot1) has realtime attr */ |
| #define SGIMC_GIOPAR_RTIMEGFX 0x00000040 /* GFX device has realtime attr */ |
| #define SGIMC_GSTAT_ADDR 0x00001000 /* parity error on addr cycle */ |
| #define SGIMC_GSTAT_BC 0x00002000 /* parity error on byte count cycle */ |
| #define SGIMC_GSTAT_PIO_RD 0x00004000 /* read data parity on pio */ |
| #define SGIMC_GSTAT_PIO_WR 0x00008000 /* write data parity on pio */ |
| #define SGIMC_GSTAT_PROM 0x00000800 /* write to PROM when PROM_EN not set */ |
| #define SGIMC_MACC_ALIASBIG 0x20000000 /* 512MB home for alias */ |
| #define SGIMC_MCONFIG_BASEADDR 0x000000ff /* Base address of bank*/ |
| #define SGIMC_MCONFIG_RMASK 0x00001f00 /* Ram config bitmask */ |
| #define SGIMC_MCONFIG_SBANKS 0x00004000 /* Number of subbanks */ |
| #define SGIMC_SYSID_EPRESENT 0x00000010 /* Indicates presence of EISA bus */ |
| #define SGIMC_SYSID_MASKREV 0x0000000f /* Revision of MC controller */ |
| struct sgimc_regs* sgimc |
1.8.2