16 #include <linux/kernel.h>
17 #include <linux/module.h>
24 #include <linux/bitops.h>
33 #define JZ4740_GPIO_BASE_A (32*0)
34 #define JZ4740_GPIO_BASE_B (32*1)
35 #define JZ4740_GPIO_BASE_C (32*2)
36 #define JZ4740_GPIO_BASE_D (32*3)
38 #define JZ4740_GPIO_NUM_A 32
39 #define JZ4740_GPIO_NUM_B 32
40 #define JZ4740_GPIO_NUM_C 31
41 #define JZ4740_GPIO_NUM_D 32
43 #define JZ4740_IRQ_GPIO_BASE_A (JZ4740_IRQ_GPIO(0) + JZ4740_GPIO_BASE_A)
44 #define JZ4740_IRQ_GPIO_BASE_B (JZ4740_IRQ_GPIO(0) + JZ4740_GPIO_BASE_B)
45 #define JZ4740_IRQ_GPIO_BASE_C (JZ4740_IRQ_GPIO(0) + JZ4740_GPIO_BASE_C)
46 #define JZ4740_IRQ_GPIO_BASE_D (JZ4740_IRQ_GPIO(0) + JZ4740_GPIO_BASE_D)
48 #define JZ_REG_GPIO_PIN 0x00
49 #define JZ_REG_GPIO_DATA 0x10
50 #define JZ_REG_GPIO_DATA_SET 0x14
51 #define JZ_REG_GPIO_DATA_CLEAR 0x18
52 #define JZ_REG_GPIO_MASK 0x20
53 #define JZ_REG_GPIO_MASK_SET 0x24
54 #define JZ_REG_GPIO_MASK_CLEAR 0x28
55 #define JZ_REG_GPIO_PULL 0x30
56 #define JZ_REG_GPIO_PULL_SET 0x34
57 #define JZ_REG_GPIO_PULL_CLEAR 0x38
58 #define JZ_REG_GPIO_FUNC 0x40
59 #define JZ_REG_GPIO_FUNC_SET 0x44
60 #define JZ_REG_GPIO_FUNC_CLEAR 0x48
61 #define JZ_REG_GPIO_SELECT 0x50
62 #define JZ_REG_GPIO_SELECT_SET 0x54
63 #define JZ_REG_GPIO_SELECT_CLEAR 0x58
64 #define JZ_REG_GPIO_DIRECTION 0x60
65 #define JZ_REG_GPIO_DIRECTION_SET 0x64
66 #define JZ_REG_GPIO_DIRECTION_CLEAR 0x68
67 #define JZ_REG_GPIO_TRIGGER 0x70
68 #define JZ_REG_GPIO_TRIGGER_SET 0x74
69 #define JZ_REG_GPIO_TRIGGER_CLEAR 0x78
70 #define JZ_REG_GPIO_FLAG 0x80
71 #define JZ_REG_GPIO_FLAG_CLEAR 0x14
73 #define GPIO_TO_BIT(gpio) BIT(gpio & 0x1f)
74 #define GPIO_TO_REG(gpio, reg) (gpio_to_jz_gpio_chip(gpio)->base + (reg))
75 #define CHIP_TO_REG(chip, reg) (gpio_chip_to_jz_gpio_chip(chip)->base + (reg))
91 return &jz4740_gpio_chips[gpio >> 5];
101 struct irq_chip_generic *
gc = irq_data_get_irq_chip_data(data);
105 static inline void jz_gpio_write_bit(
unsigned int gpio,
unsigned int reg)
143 for (i = 0; i < num; ++
i, ++
request) {
153 for (--request; i > 0; --
i, --
request) {
166 for (i = 0; i < num; ++
i, ++
request) {
178 for (i = 0; i < num; ++
i, ++
request) {
190 for (i = 0; i < num; ++
i, ++
request)
207 static int jz_gpio_get_value(
struct gpio_chip *
chip,
unsigned gpio)
212 static void jz_gpio_set_value(
struct gpio_chip *chip,
unsigned gpio,
int value)
219 static int jz_gpio_direction_output(
struct gpio_chip *chip,
unsigned gpio,
223 jz_gpio_set_value(chip, gpio, value);
228 static int jz_gpio_direction_input(
struct gpio_chip *chip,
unsigned gpio)
278 #define IRQ_TO_BIT(irq) BIT(irq_to_gpio(irq) & 0x1f)
280 static void jz_gpio_check_trigger_both(
struct jz_gpio_chip *chip,
unsigned int irq)
300 static void jz_gpio_irq_demux_handler(
unsigned int irq,
struct irq_desc *
desc)
303 unsigned int gpio_irq;
304 struct jz_gpio_chip *chip = irq_desc_get_handler_data(desc);
312 jz_gpio_check_trigger_both(chip, gpio_irq);
317 static inline void jz_gpio_set_irq_bit(
struct irq_data *
data,
unsigned int reg)
323 static void jz_gpio_irq_unmask(
struct irq_data *data)
327 jz_gpio_check_trigger_both(chip, data->
irq);
332 static unsigned int jz_gpio_irq_startup(
struct irq_data *data)
335 jz_gpio_irq_unmask(data);
339 static void jz_gpio_irq_shutdown(
struct irq_data *data)
348 static int jz_gpio_irq_set_type(
struct irq_data *data,
unsigned int flow_type)
351 unsigned int irq = data->
irq;
388 static int jz_gpio_irq_set_wake(
struct irq_data *data,
unsigned int on)
398 #define JZ4740_GPIO_CHIP(_bank) { \
399 .irq_base = JZ4740_IRQ_GPIO_BASE_ ## _bank, \
401 .label = "Bank " # _bank, \
402 .owner = THIS_MODULE, \
403 .set = jz_gpio_set_value, \
404 .get = jz_gpio_get_value, \
405 .direction_output = jz_gpio_direction_output, \
406 .direction_input = jz_gpio_direction_input, \
407 .base = JZ4740_GPIO_BASE_ ## _bank, \
408 .ngpio = JZ4740_GPIO_NUM_ ## _bank, \
419 static void jz4740_gpio_chip_init(
struct jz_gpio_chip *chip,
unsigned int id)
421 struct irq_chip_generic *
gc;
422 struct irq_chip_type *
ct;
428 irq_set_chained_handler(chip->
irq, jz_gpio_irq_demux_handler);
433 gc->wake_enabled = IRQ_MSK(chip->
gpio_chip.ngpio);
441 ct->chip.name =
"GPIO";
443 ct->chip.irq_unmask = jz_gpio_irq_unmask;
447 ct->chip.irq_startup = jz_gpio_irq_startup;
448 ct->chip.irq_shutdown = jz_gpio_irq_shutdown;
449 ct->chip.irq_set_type = jz_gpio_irq_set_type;
450 ct->chip.irq_set_wake = jz_gpio_irq_set_wake;
459 static int __init jz4740_gpio_init(
void)
463 for (i = 0; i <
ARRAY_SIZE(jz4740_gpio_chips); ++
i)
464 jz4740_gpio_chip_init(&jz4740_gpio_chips[i], i);
472 #ifdef CONFIG_DEBUG_FS
475 const char *
name,
unsigned int reg)
507 .
open = gpio_regs_open,
513 static int __init gpio_debugfs_init(
void)