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arch
mips
pnx8550
common
pci.c
Go to the documentation of this file.
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/*
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*
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* BRIEF MODULE DESCRIPTION
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*
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* Author:
[email protected]
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*
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* This program is free software; you can distribute it and/or modify it
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* under the terms of the GNU General Public License (Version 2) as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
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*/
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#include <linux/types.h>
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#include <linux/pci.h>
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#include <linux/kernel.h>
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#include <
linux/init.h
>
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#include <pci.h>
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#include <
glb.h
>
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#include <nand.h>
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static
struct
resource
pci_io_resource = {
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.start =
PNX8550_PCIIO
+ 0x1000,
/* reserve regacy I/O space */
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.end =
PNX8550_PCIIO
+
PNX8550_PCIIO_SIZE
,
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.name =
"pci IO space"
,
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.flags =
IORESOURCE_IO
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};
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static
struct
resource
pci_mem_resource = {
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.start =
PNX8550_PCIMEM
,
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.end =
PNX8550_PCIMEM
+
PNX8550_PCIMEM_SIZE
- 1,
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.name =
"pci memory space"
,
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.flags =
IORESOURCE_MEM
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};
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extern
struct
pci_ops
pnx8550_pci_ops
;
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static
struct
pci_controller
pnx8550_controller = {
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.pci_ops = &
pnx8550_pci_ops
,
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.io_map_base =
PNX8550_PORT_BASE
,
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.io_resource = &pci_io_resource,
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.mem_resource = &pci_mem_resource,
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};
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/* Return the total size of DRAM-memory, (RANK0 + RANK1) */
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static
inline
unsigned
long
get_system_mem_size
(
void
)
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{
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/* Read IP2031_RANK0_ADDR_LO */
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unsigned
long
dram_r0_lo =
inl
(
PCI_BASE
| 0x65010);
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/* Read IP2031_RANK1_ADDR_HI */
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unsigned
long
dram_r1_hi =
inl
(
PCI_BASE
| 0x65018);
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return
dram_r1_hi - dram_r0_lo + 1;
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}
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static
int
__init
pnx8550_pci_setup(
void
)
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{
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int
pci_mem_code;
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int
mem_size
=
get_system_mem_size
() >> 20;
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/* Clear the Global 2 Register, PCI Inta Output Enable Registers
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Bit 1:Enable DAC Powerdown
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-> 0:DACs are enabled and are working normally
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1:DACs are powerdown
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Bit 0:Enable of PCI inta output
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-> 0 = Disable PCI inta output
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1 = Enable PCI inta output
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*/
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PNX8550_GLB2_ENAB_INTA_O
= 0;
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/* Calc the PCI mem size code */
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if
(mem_size >= 128)
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pci_mem_code =
SIZE_128M
;
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else
if
(mem_size >= 64)
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pci_mem_code =
SIZE_64M
;
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else
if
(mem_size >= 32)
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pci_mem_code =
SIZE_32M
;
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else
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pci_mem_code =
SIZE_16M
;
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/* Set PCI_XIO registers */
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outl
(pci_mem_resource.
start
,
PCI_BASE
|
PCI_BASE1_LO
);
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outl
(pci_mem_resource.
end
+ 1,
PCI_BASE
|
PCI_BASE1_HI
);
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outl
(pci_io_resource.
start
,
PCI_BASE
|
PCI_BASE2_LO
);
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outl
(pci_io_resource.
end
,
PCI_BASE
|
PCI_BASE2_HI
);
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/* Send memory transaction via PCI_BASE2 */
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outl
(0x00000001,
PCI_BASE
|
PCI_IO
);
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/* Unlock the setup register */
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outl
(0xca,
PCI_BASE
|
PCI_UNLOCKREG
);
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/*
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* BAR0 of PNX8550 (pci base 10) must be zero in order for ide
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* to work, and in order for bus_to_baddr to work without any
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* hacks.
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*/
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outl
(0x00000000,
PCI_BASE
|
PCI_BASE10
);
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/*
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*These two bars are set by default or the boot code.
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* However, it's safer to set them here so we're not boot
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* code dependent.
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*/
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outl
(0x1be00000,
PCI_BASE
|
PCI_BASE14
);
/* PNX MMIO */
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outl
(
PNX8550_NAND_BASE_ADDR
,
PCI_BASE
|
PCI_BASE18
);
/* XIO */
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outl
(
PCI_EN_TA
|
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PCI_EN_PCI2MMI
|
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PCI_EN_XIO
|
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PCI_SETUP_BASE18_SIZE
(
SIZE_32M
) |
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PCI_SETUP_BASE18_EN
|
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PCI_SETUP_BASE14_EN
|
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PCI_SETUP_BASE10_PREF
|
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PCI_SETUP_BASE10_SIZE
(pci_mem_code) |
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PCI_SETUP_CFGMANAGE_EN
|
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PCI_SETUP_PCIARB_EN
,
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PCI_BASE
|
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PCI_SETUP
);
/* PCI_SETUP */
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outl
(0x00000000,
PCI_BASE
|
PCI_CTRL
);
/* PCI_CONTROL */
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register_pci_controller
(&pnx8550_controller);
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return
0;
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}
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arch_initcall
(pnx8550_pci_setup);
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