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Linux Kernel
3.7.1
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Linux Kernel
3.7.1
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#include <mach/anomaly.h>Go to the source code of this file.
| #define _disable_dcplb | ( | ) | _disable_cplb(DMEM_CONTROL, ENDCPLB) |
| #define _disable_icplb | ( | ) | _disable_cplb(IMEM_CONTROL, ENICPLB) |
| #define _enable_dcplb | ( | ) | _enable_cplb(DMEM_CONTROL, ENDCPLB) |
| #define _enable_icplb | ( | ) | _enable_cplb(IMEM_CONTROL, ENICPLB) |
| #define CPLB_CACHE_ENABLED CPLB_L1_CHBL | CPLB_DIRTY |
| #define CPLB_COMMON (CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND) |
| #define CPLB_D_PAGE_MGMT CPLB_LOCK | CPLB_ALL_ACCESS | CPLB_VALID |
| #define CPLB_DDOCACHE CPLB_DNOCACHE | CPLB_DEF_CACHE |
| #define CPLB_DEF_CACHE CPLB_L1_CHBL | CPLB_WT |
| #define CPLB_DNOCACHE CPLB_ALL_ACCESS | CPLB_VALID |
| #define CPLB_ENABLE_ANY_CPLBS |
| #define CPLB_ENABLE_CPLBS (1<<CPLB_ENABLE_CPLBS_P) |
| #define CPLB_ENABLE_DCACHE (1<<CPLB_ENABLE_DCACHE_P) |
| #define CPLB_ENABLE_DCACHE2 (1<<CPLB_ENABLE_DCACHE2_P) |
| #define CPLB_ENABLE_DCPLBS (1<<CPLB_ENABLE_DCPLBS_P) |
| #define CPLB_ENABLE_ICACHE (1<<CPLB_ENABLE_ICACHE_P) |
| #define CPLB_ENABLE_ICPLBS (1<<CPLB_ENABLE_ICPLBS_P) |
| #define CPLB_I_PAGE_MGMT CPLB_LOCK | CPLB_VALID |
| #define CPLB_IDOCACHE CPLB_INOCACHE | CPLB_L1_CHBL |
| #define CPLB_INOCACHE CPLB_USER_RD | CPLB_VALID |
| #define disable_dcplb | ( | ) | disable_cplb(DMEM_CONTROL, ENDCPLB) |
| #define disable_icplb | ( | ) | disable_cplb(IMEM_CONTROL, ENICPLB) |
| #define enable_dcplb | ( | ) | enable_cplb(DMEM_CONTROL, ENDCPLB) |
| #define enable_icplb | ( | ) | enable_cplb(IMEM_CONTROL, ENICPLB) |
| #define L1_DMEMORY (CPLB_LOCK | CPLB_COMMON) |
| #define L1_IMEMORY ( CPLB_USER_RD | CPLB_VALID | CPLB_LOCK) |
| #define L2_DMEMORY (CPLB_COMMON | PAGE_SIZE_1MB) |
| #define L2_IMEMORY ( CPLB_USER_RD | CPLB_VALID | PAGE_SIZE_1MB) |
| #define SDRAM_DGENERIC (CPLB_COMMON) |
| #define SDRAM_DNON_CHBL (CPLB_COMMON) |
| #define SDRAM_EBIU (CPLB_COMMON) |
| #define SDRAM_IGENERIC (CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_PORTPRIO) |
| #define SDRAM_IKERNEL (SDRAM_IGENERIC | CPLB_LOCK) |
| #define SDRAM_INON_CHBL ( CPLB_USER_RD | CPLB_VALID) |
| #define SDRAM_OOPS (CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY) |
1.8.2