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irq.c File Reference
#include <linux/export.h>
#include <linux/threads.h>
#include <linux/kernel_stat.h>
#include <linux/signal.h>
#include <linux/sched.h>
#include <linux/ptrace.h>
#include <linux/ioport.h>
#include <linux/interrupt.h>
#include <linux/timex.h>
#include <linux/init.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include <linux/irq.h>
#include <linux/seq_file.h>
#include <linux/cpumask.h>
#include <linux/profile.h>
#include <linux/bitops.h>
#include <linux/list.h>
#include <linux/radix-tree.h>
#include <linux/mutex.h>
#include <linux/bootmem.h>
#include <linux/pci.h>
#include <linux/debugfs.h>
#include <linux/of.h>
#include <linux/of_irq.h>
#include <asm/uaccess.h>
#include <asm/io.h>
#include <asm/pgtable.h>
#include <asm/irq.h>
#include <asm/cache.h>
#include <asm/prom.h>
#include <asm/ptrace.h>
#include <asm/machdep.h>
#include <asm/udbg.h>
#include <asm/smp.h>
#include <asm/debug.h>
#include <asm/trace.h>

Go to the source code of this file.




 DEFINE_PER_CPU_SHARED_ALIGNED (irq_cpustat_t, irq_stat)
int arch_show_interrupts (struct seq_file *p, int prec)
u64 arch_irq_stat_cpu (unsigned int cpu)
void do_IRQ (struct pt_regs *regs)
void __init init_IRQ (void)
void irq_ctx_init (void)
void do_softirq (void)
irq_hw_number_t virq_to_hw (unsigned int virq)
 EXPORT_SYMBOL_GPL (virq_to_hw)
int irq_choose_cpu (const struct cpumask *mask)
int arch_early_irq_init (void)


int __irq_offset_value
struct thread_info

Macro Definition Documentation


Definition at line 76 of file irq.c.

Function Documentation

int arch_early_irq_init ( void  )

Definition at line 667 of file irq.c.

u64 arch_irq_stat_cpu ( unsigned int  cpu)

Definition at line 376 of file irq.c.

int arch_show_interrupts ( struct seq_file p,
int  prec 

Definition at line 337 of file irq.c.

void do_IRQ ( struct pt_regs regs)

Definition at line 487 of file irq.c.

void do_softirq ( void  )

Definition at line 609 of file irq.c.

EXPORT_SYMBOL_GPL ( virq_to_hw  )
void __init init_IRQ ( void  )

The hexagon core comes with a first-level interrupt controller with 32 total possible interrupts. When the core is embedded into different systems/platforms, it is typically wrapped by macro cells that provide one or more second-level interrupt controllers that are cascaded into one or more of the first-level interrupts handled here. The precise wiring of these other irqs varies from platform to platform, and are set up & configured in the platform-specific files.

The first-level interrupt controller is wrapped by the VM, which virtualizes the interrupt controller for us. It provides a very simple, fast & efficient API, and so the fasteoi handler is appropriate for this case.

Definition at line 520 of file irq.c.

int irq_choose_cpu ( const struct cpumask mask)

Definition at line 661 of file irq.c.

void irq_ctx_init ( void  )

Definition at line 569 of file irq.c.

irq_hw_number_t virq_to_hw ( unsigned int  virq)

Definition at line 624 of file irq.c.

Variable Documentation

int __irq_offset_value

Definition at line 82 of file irq.c.

struct thread_info* hardirq_ctx [NR_CPUS] __read_mostly

Definition at line 566 of file irq.c.