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pci.h
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1 #ifndef __POWERNV_PCI_H
2 #define __POWERNV_PCI_H
3 
4 struct pci_dn;
5 
6 enum pnv_phb_type {
7  PNV_PHB_P5IOC2,
8  PNV_PHB_IODA1,
9  PNV_PHB_IODA2,
10 };
11 
12 /* Precise PHB model for error management */
13 enum pnv_phb_model {
14  PNV_PHB_MODEL_UNKNOWN,
15  PNV_PHB_MODEL_P5IOC2,
16  PNV_PHB_MODEL_P7IOC,
17 };
18 
19 #define PNV_PCI_DIAG_BUF_SIZE 4096
20 #define PNV_IODA_PE_DEV (1 << 0) /* PE has single PCI device */
21 #define PNV_IODA_PE_BUS (1 << 1) /* PE has primary PCI bus */
22 #define PNV_IODA_PE_BUS_ALL (1 << 2) /* PE has subordinate buses */
23 
24 /* Data associated with a PE, including IOMMU tracking etc.. */
25 struct pnv_ioda_pe {
26  unsigned long flags;
27 
28  /* A PE can be associated with a single device or an
29  * entire bus (& children). In the former case, pdev
30  * is populated, in the later case, pbus is.
31  */
32  struct pci_dev *pdev;
33  struct pci_bus *pbus;
34 
35  /* Effective RID (device RID for a device PE and base bus
36  * RID with devfn 0 for a bus PE)
37  */
38  unsigned int rid;
39 
40  /* PE number */
41  unsigned int pe_number;
42 
43  /* "Weight" assigned to the PE for the sake of DMA resource
44  * allocations
45  */
46  unsigned int dma_weight;
47 
48  /* "Base" iommu table, ie, 4K TCEs, 32-bit DMA */
49  int tce32_seg;
50  int tce32_segcount;
51  struct iommu_table tce32_table;
52 
53  /* XXX TODO: Add support for additional 64-bit iommus */
54 
55  /* MSIs. MVE index is identical for for 32 and 64 bit MSI
56  * and -1 if not supported. (It's actually identical to the
57  * PE number)
58  */
59  int mve_number;
60 
61  /* Link in list of PE#s */
62  struct list_head dma_link;
63  struct list_head list;
64 };
65 
66 struct pnv_phb {
67  struct pci_controller *hose;
68  enum pnv_phb_type type;
69  enum pnv_phb_model model;
70  u64 opal_id;
71  void __iomem *regs;
72  int initialized;
73  spinlock_t lock;
74 
75 #ifdef CONFIG_PCI_MSI
76  unsigned long *msi_map;
77  unsigned int msi_base;
78  unsigned int msi_count;
79  unsigned int msi_next;
80  unsigned int msi32_support;
81 #endif
82  int (*msi_setup)(struct pnv_phb *phb, struct pci_dev *dev,
83  unsigned int hwirq, unsigned int is_64,
84  struct msi_msg *msg);
85  void (*dma_dev_setup)(struct pnv_phb *phb, struct pci_dev *pdev);
86  void (*fixup_phb)(struct pci_controller *hose);
87  u32 (*bdfn_to_pe)(struct pnv_phb *phb, struct pci_bus *bus, u32 devfn);
88 
89  union {
90  struct {
91  struct iommu_table iommu_table;
92  } p5ioc2;
93 
94  struct {
95  /* Global bridge info */
96  unsigned int total_pe;
97  unsigned int m32_size;
98  unsigned int m32_segsize;
99  unsigned int m32_pci_base;
100  unsigned int io_size;
101  unsigned int io_segsize;
102  unsigned int io_pci_base;
103 
104  /* PE allocation bitmap */
105  unsigned long *pe_alloc;
106 
107  /* M32 & IO segment maps */
108  unsigned int *m32_segmap;
109  unsigned int *io_segmap;
110  struct pnv_ioda_pe *pe_array;
111 
112  /* Sorted list of used PE's based
113  * on the sequence of creation
114  */
115  struct list_head pe_list;
116 
117  /* Reverse map of PEs, will have to extend if
118  * we are to support more than 256 PEs, indexed
119  * bus { bus, devfn }
120  */
121  unsigned char pe_rmap[0x10000];
122 
123  /* 32-bit TCE tables allocation */
124  unsigned long tce32_count;
125 
126  /* Total "weight" for the sake of DMA resources
127  * allocation
128  */
129  unsigned int dma_weight;
130  unsigned int dma_pe_count;
131 
132  /* Sorted list of used PE's, sorted at
133  * boot for resource allocation purposes
134  */
135  struct list_head pe_dma_list;
136  } ioda;
137  };
138 
139  /* PHB status structure */
140  union {
141  unsigned char blob[PNV_PCI_DIAG_BUF_SIZE];
142  struct OpalIoP7IOCPhbErrorData p7ioc;
143  } diag;
144 };
145 
146 extern struct pci_ops pnv_pci_ops;
147 
148 extern void pnv_pci_setup_iommu_table(struct iommu_table *tbl,
149  void *tce_mem, u64 tce_size,
150  u64 dma_offset);
151 extern void pnv_pci_init_p5ioc2_hub(struct device_node *np);
152 extern void pnv_pci_init_ioda_hub(struct device_node *np);
153 
154 
155 #endif /* __POWERNV_PCI_H */
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