#include <linux/interrupt.h>
#include <linux/kernel_stat.h>
#include <linux/seq_file.h>
#include <asm/io.h>
Go to the source code of this file.
Definition at line 43 of file irq.c.
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#define INT_PRIORITY_SG0 4 |
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#define INT_PRIORITY_SG1 5 |
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#define INT_PRIORITY_SG2 6 |
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#define INT_PRIORITY_SG3 7 |
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Definition at line 48 of file irq.c.
The hexagon core comes with a first-level interrupt controller with 32 total possible interrupts. When the core is embedded into different systems/platforms, it is typically wrapped by macro cells that provide one or more second-level interrupt controllers that are cascaded into one or more of the first-level interrupts handled here. The precise wiring of these other irqs varies from platform to platform, and are set up & configured in the platform-specific files.
The first-level interrupt controller is wrapped by the VM, which virtualizes the interrupt controller for us. It provides a very simple, fast & efficient API, and so the fasteoi handler is appropriate for this case.
Definition at line 89 of file irq.c.
Initial value:= {
.name = "Score7-level",
.irq_mask = score_mask,
.irq_mask_ack = score_mask,
.irq_unmask = score_unmask,
}
Definition at line 79 of file irq.c.